CN112201690A - MOSFET transistor - Google Patents
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- CN112201690A CN112201690A CN202011016736.XA CN202011016736A CN112201690A CN 112201690 A CN112201690 A CN 112201690A CN 202011016736 A CN202011016736 A CN 202011016736A CN 112201690 A CN112201690 A CN 112201690A
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- 239000000758 substrate Substances 0.000 claims abstract description 54
- 239000002184 metal Substances 0.000 claims abstract description 45
- 229910052751 metal Inorganic materials 0.000 claims abstract description 45
- 238000002955 isolation Methods 0.000 claims description 15
- 230000005684 electric field Effects 0.000 abstract description 11
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 238000002360 preparation method Methods 0.000 abstract description 5
- 230000005611 electricity Effects 0.000 abstract 1
- 239000000463 material Substances 0.000 description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 229920005591 polysilicon Polymers 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910052681 coesite Inorganic materials 0.000 description 6
- 229910052906 cristobalite Inorganic materials 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 229910052682 stishovite Inorganic materials 0.000 description 6
- 229910052905 tridymite Inorganic materials 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910052776 Thorium Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910010038 TiAl Inorganic materials 0.000 description 2
- -1 TiNiAg Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910001258 titanium gold Inorganic materials 0.000 description 2
- 229910019213 POCl3 Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000005527 interface trap Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl chloride Substances ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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Abstract
The invention discloses a MOSFET transistor, which comprises: a substrate; a buffer layer; a drift region; doping a base region; a cap layer; a plurality of trenches; the plurality of grooves extend from one side of the cap layer to one side of the substrate and extend into the drift region; the heavily doped regions are positioned in the drift region and at the bottom of the groove, and the first metal layer covers a part of the table top, a part of the bottom of the groove and a side wall connected with the part of the bottom; a gate dielectric layer and a gate electrode; a first electrode and a second electrode; the MOSFET transistor has a first cell region and a second cell region. From this, through setting up slot, first primitive cell region and second primitive cell region, realized the electric field shielding of heavily doped region to the trench gate, realized the electricity of doping base region with the second electrode and connected, also parallelly connected schottky diode in the reverse direction simultaneously, on the basis that does not influence primitive cell size, can reduce the preparation degree of difficulty of MOSFET transistor, can reduce the manufacturing cost of MOSFET transistor, can also reduce MOSFET transistor on-resistance.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a MOSFET transistor.
Background
Compared with Si, the wide bandgap Semiconductor material SiC has a bandgap width of about 3 times, a critical breakdown electric Field strength of 10 times, and a thermal conductivity of 3 times, so that a SiC MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) has advantages of higher withstand voltage, higher operating frequency, higher temperature resistance, and the like compared with a Si-based IGBT (Insulated Gate Bipolar Transistor). Both theoretically and practically, SiC MOSFETs have been demonstrated to have switching frequencies above 10 and better switching efficiency than Si-based IGBTs. However, the cost of the SiC MOSFET is high due to the high cost of the existing SiC material, the immature technology and the great difficulty of the preparation process
On the other hand, in many applications, such as full-bridge applications, the transistor needs to be connected with a freewheeling diode in an anti-parallel manner to work together, for example, a Si-based IGBT module commonly used at present is connected with a Si fast recovery diode in an anti-parallel manner as a freewheeling diode. Since the SiC MOSFET has a high turn-on voltage of the internal parasitic pn diode and a large loss, an antiparallel SiC schottky diode is often required as a freewheeling diode. If the free wheel diode is integrated in one device (MOSFET transistor), not only the integration level and the reliability of the chip can be improved, but also the cost of the chip can be effectively reduced. However, in the prior art, when a schottky diode is integrated into a MOSFET chip, the cell size is increased, which results in an increase in on-resistance.
Disclosure of Invention
The present invention is directed to solving at least one of the problems of the prior art. Therefore, an object of the present invention is to provide a MOSFET transistor, which includes a trench, a first cell region and a second cell region, and compared with the prior art, the MOSFET transistor implements electric field shielding of a trench gate by a heavily doped region, implements electrical connection between a doped base region and a second electrode, and simultaneously connects a schottky diode in anti-parallel, so that on the basis of not affecting the cell size, the difficulty of manufacturing the MOSFET transistor can be reduced, the production cost of the MOSFET transistor can be reduced, and the on-resistance of the MOSFET transistor can be reduced.
The MOSFET transistor according to the present invention comprises: a substrate; a buffer layer on one side of the substrate; the drift region is positioned on one side of the buffer layer far away from the substrate; the doped base region is positioned on one side of the drift region, which is far away from the buffer layer; the cap layer is positioned on one side of the doped base region, which is far away from the drift region; a plurality of trenches extending from one side of the cap layer to one side of the substrate and into the drift region; a plurality of heavily doped regions at least within the drift region and at the bottom of the trench; the first metal layer covers part of the table top, part of the bottom and the side wall connected with the part of the bottom of the groove; the gate dielectric layer and the gate are positioned in the groove, and an isolation medium is arranged between the gate and the first metal layer at intervals; the first electrode is positioned on one side, far away from the buffer layer, of the substrate, and the second electrode is filled in the groove and is in contact with the first metal layer; the MOSFET transistor is provided with a first cell region and a second cell region, and a part of the heavily doped region in the second cell region further extends to the side wall of the groove at one side with the first metal layer.
According to the MOSFET transistor, the groove, the first cell region and the second cell region are arranged, compared with the prior art, the heavy doping region is used for shielding an electric field of a groove gate, and the reliability of a device gate is improved. The electric connection of the doped base region and the second electrode is realized, and the Schottky diode is connected in parallel in an anti-parallel mode, so that the preparation difficulty of the MOSFET transistor can be reduced, the production cost of the MOSFET transistor can be reduced, and the on-resistance of the MOSFET transistor can be reduced on the basis of not influencing the size of a primitive cell.
In some examples of the invention, ohmic contact is formed between the first metal layer in the second cell region and the heavily doped region at the side wall of the groove and at the bottom of the groove, and ohmic contact is formed between the first metal layer and the cap layer on the partial table-board; schottky contact is formed between the first metal layer in the first cell region and the drift region, and ohmic contact is formed between the Schottky contact and the cap layer on the part of the table-board.
In some examples of the invention, the substrate, the buffer layer, the drift region and the cap layer have a first doping type, and the doped base region and the heavily doped region have a second doping type.
In some examples of the invention, the substrate and the cap layer are both heavily doped and the drift region is lightly doped.
In some examples of the invention, a distance D between an orthographic projection of the heavily doped region on the substrate and an orthographic projection of the gate sidewall of the trench on the substrate satisfies: d is more than or equal to 0 and less than or equal to Th, and Th is the sum of the widths of the grid and the isolation medium.
In some examples of the invention, the doped base region has a thickness of not less than 0.2 microns.
In some examples of the invention, the depth of the trench is greater than the thickness of the doped base region.
In some examples of the invention, the depth of the portion of the trench extending into the drift region is not less than 0.2 microns.
In some examples of the invention, the MOSFET transistor further comprises: the lightly doped conducting layer is positioned in the drift region and between two adjacent heavily doped regions, the doping type of the lightly doped conducting layer is the same as that of the drift region, and the doping concentration of the lightly doped conducting layer is greater than that of the drift region.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a schematic structural diagram of a first cell region of a MOSFET transistor according to an embodiment of the invention;
fig. 2 is a schematic structural diagram of a second cell region of a MOSFET transistor according to an embodiment of the invention;
fig. 3 is a schematic structural diagram of a first cell region and a second cell region of a MOSFET transistor according to an embodiment of the present invention;
fig. 4 is a perspective view of a first cell region and a second cell region of a MOSFET transistor according to an embodiment of the invention;
fig. 5 is a circuit configuration diagram of a MOSFET transistor chip according to an embodiment of the invention.
Reference numerals:
a MOSFET transistor 100;
a gate 1; a first electrode 2; a second electrode 3;
a substrate 10; a buffer layer 20; a drift region 30; a doped base region 40; a cap layer 50; a trench 60; a heavily doped region 70; a first metal layer 80; a gate dielectric layer 90; an isolation medium 11;
a first cell region 110; a second cell region 120; an ohmic contact 130; a Schottky contact 140;
a Schottky diode 200; the conductive layer 300 is lightly doped.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
A MOSFET transistor 100 according to an embodiment of the invention is described below with reference to fig. 1-5.
As shown in fig. 1 to 5, a MOSFET transistor 100 according to an embodiment of the present invention includes: the semiconductor device comprises a substrate 10, a buffer layer 20, a drift region 30, a doped base region 40, a cap layer 50, a plurality of trenches 60, a plurality of heavily doped regions 70, a first metal layer 80, a gate dielectric layer 90, a gate 1, a first electrode 2 and a second electrode 3. The doping type of the substrate 10 may be n-type heavily doped low resistivity, and the buffer layer 20 is located at one side of the substrate 10, it should be noted that the buffer layer 20 may be located above the substrate 10 in the up-down direction shown in fig. 1. The drift region 30 is located on a side of the buffer layer 20 away from the substrate 10, and it should be explained that, in the up-down direction shown in fig. 1, the drift region 30 may be located above the buffer layer 20, the buffer layer 20 may be located between the drift region 30 and the substrate 10, and a side of the drift region 30 may be in contact with the buffer layer 20. The doped base region 40 is located on a side of the drift region 30 away from the buffer layer 20, and it should be noted that the doped base region 40 may be located above the drift region 30 in the up-down direction shown in fig. 1. The cap layer 50 is located on a side of the doped base region 40 away from the drift region 30, and it should be explained that, in the up-down direction shown in fig. 1, the cap layer 50 may be located above the doped base region 40, and a side of the doped base region 40 may be in contact with the cap layer 50, and a doping type of the cap layer 50 may be n-type heavy doping. The plurality of trenches 60 extend from the cap layer 50 side to the substrate 10 side and extend into the drift region 30. in the up, down, left, and right directions shown in fig. 1, the trenches 60 may extend downward from the left side of the cap layer 50, the trenches 60 may extend downward from the right side of the cap layer 50, and the plurality of trenches 60 may also extend downward from both the left and right sides of the cap layer 50. The heavily doped region 70 is located at least within the drift region 30 and at the bottom of the trench 60, it being to be explained that the heavily doped region 70 may be a heavily doped concentration p-region, at least a portion of the heavily doped region 70 being located within the drift region 30 and at least a portion of the heavily doped region 70 being located at the bottom of the trench 60. The first metal layer 80 covers a part of the bottom of the trench 60, a part of the mesa, and sidewalls connected to a part of the bottom, it should be noted that the first metal layer 80 may cover sidewalls of the trench 60 connected to a part of the bottom of the trench 60, i.e., sidewalls of the trench away from the gate 1, and the first metal layer 80 may also cover the cap layer 50 on a part of the bottom of the trench 60 and a part of the mesa. The gate dielectric layer 90 and the gate 1 are located in the trench 60, and the isolation dielectric 11 is spaced between the gate 1 and the first metal layer 80, it should be explained that, in the left-right direction shown in fig. 1, the gate 1 may be located in the trench 60 and the gate 1 may be disposed near the left side of the adjacent doped base region 40 and the cap layer 50, and the isolation dielectric 11 may be located between the gate 1 and the first metal layer 80; a gate dielectric layer 90 may be located within the trench 60 and a gate 1 may be disposed adjacent to the right side of the adjacent doped base region 40 and cap layer 50, and a portion of the gate dielectric layer 90 may be disposed between the gate 1 and the doped base region 40. The first electrode 2 is located on a side of the substrate 10 away from the buffer layer 20, the second electrode 3 is filled in the trench 60 and is in contact with the first metal layer 80, it should be noted that, in the up-down direction shown in fig. 1, the first electrode 2 may be located below the substrate 10, or it is understood that the substrate 10 may be located between the first electrode 2 and the buffer layer 20, the second electrode 3 may be disposed above the trench 60, a part of the second electrode 3 may be filled in the trench 60, and the second electrode 3 is in contact with the first metal layer 80. The MOSFET transistor 100 has a first cell region 110 and a second cell region 120, and a portion of the heavily doped region 70 in the second cell region 120 further extends to the sidewall of the trench 60 having the first metal layer 80, it should be explained that a portion of the heavily doped region 70 in the second cell region 120 may extend to the sidewall of the trench 60 having the first metal layer 80.
In the second cell region 120, a part of the heavily doped region 70 may extend to a sidewall of the trench 60, that is, a sidewall far away from the gate 1, and the doped base region 40 may be connected to the second electrode 3 through the heavily doped region 70 at the sidewall of the trench 60 in the second cell region 120, so that short circuit of the second electrode 3, the doped base region 40, and the cap layer 50 may be realized, and a bipolar junction transistor effect of the MOSFET transistor 100 may be suppressed. The active region of the MOSFET transistor 100 may be composed of two cell regions, the two cell regions may be a first cell region 110 and a second cell region 120, the first cell region 110 and the second cell region 120 may be asymmetrically disposed, a plurality of trenches 60 may be located in the first cell region 110 and/or the second cell region 120, specifically, in the left-right direction shown in fig. 1, the right side of the trench 60 may be a gate 1 and a gate dielectric layer 90, the left side of the trench 60 may be a second electrode 3 and a first metal layer 80, and the gate 1 and the second electrode 3 may be isolated by an isolation dielectric 11.
Therefore, by arranging the trench 60, the first cell region 110 and the second cell region 120, compared with the prior art, the electric field shielding of the trench gate by the heavily doped region is realized, and the reliability of the device gate is improved. The electric connection between the doped base region 40 and the second electrode 3 is realized, and the schottky diode 200 is connected in parallel in an anti-parallel mode, so that the preparation difficulty of the MOSFET transistor 100 can be reduced, the production cost of the MOSFET transistor 100 can be reduced, and the on-resistance of the MOSFET transistor 100 can be reduced on the basis of not influencing the cell size.
In some embodiments of the present invention, as shown in fig. 1-4, an ohmic contact 130 may be formed between the first metal layer 80 in the second cell region 120 and the heavily doped region 70 at the sidewall of the trench 60 and at the bottom of the trench 60, an ohmic contact 130 may be formed between the first metal layer 80 in the first cell region 110 and the drift region 30, an ohmic contact 130 may be formed between the first metal layer 80 and the cap layer 50 on a portion of the mesa, and a schottky contact 140 may be formed between the first metal layer 80 and the drift region 30. It should be noted that in the second cell region 120, an ohmic contact 130 may be formed between the first metal layer 80 and the heavily doped region 70 at the sidewall of the trench 60, and at the same time, a portion of the first metal layer 80 may cover a portion of the mesa, and the first metal layer 80 may form an ohmic contact 130 with the cap layer 50 on the portion of the mesa. In the first cell region 110, the first metal layer 80 in the trench 60 may form a schottky contact 140 with the n-type lightly doped drift region 30, and the first metal layer 80 in the trench 60 may also form a schottky contact 140 with the doped base region 40, meanwhile, a portion of the first metal layer 80 may cover a portion of the mesa, and the first metal layer 80 may form an ohmic contact 130 with the cap layer 50 on the portion of the mesa.
Further, the cells of the active region may be arranged in the same plane and alternately arranged, the arrangement period and the corresponding area ratio of the first cell region 110 and the second cell region 120 may be determined according to the magnitude of the follow current, for example, the arrangement of the cells of the active region may be the first cell region 110, the second cell region 120, the first cell region 110, and the second cell region 120, or the arrangement of the cells of the active region may be the first cell region 110, the second cell region 120, the first cell region 110, and the second cell region 120, but the present invention is not limited thereto, and the arrangement of the cells of the active region may be in other forms, and the higher the ratio of the first cell region 110 is, the stronger the follow current capability is.
As an example, as shown in fig. 1 to 4, the second electrode 3 may be electrically connected to the cap layer 50 on the mesa, the doped base region 40, the heavily doped region 70 in the trench 60, the heavily doped region 70 on the sidewall of the trench 60, and the schottky contact 140, and the first cell region 110 may be provided with the heavily doped region 70 on both sides of the schottky contact 140, respectively, so as to form a schottky diode 200(MPS) structure embedded in the pn diode, so as to shield the electric field at the schottky contact 140 and reduce the reverse bias leakage current of the schottky diode 200, and the parallel pn diode may also inject minority carriers to modulate the conductivity at a high current, so as to increase the surge current capability of the schottky diode 200.
In some embodiments of the present invention, the substrate 10, the buffer layer 20, the drift region 30 and the cap layer 50 may have a first doping type, and the doped base region 40 and the heavily doped region 70 may have a second doping type, it should be noted that the first doping type may be n-type doping, and the second doping type may be p-type doping, that is, the doping types of the substrate 10, the buffer layer 20, the drift region 30 and the cap layer 50 may be n-type doping, and the doping types of the doped base region 40 and the heavily doped region 70 may be p-type doping, but the present invention is not limited thereto, and the substrate 10, the buffer layer 20, the drift region 30 and the cap layer 50 may have the second doping type, and the doped base region 40 and the heavily doped region 70 may have the first doping type while the substrate 10, the buffer layer 20, the drift region 30 and the cap layer 50 have the second doping type, that is, the doping types of the substrate 10, the buffer layer 20, the drift region 30 and the cap layer 50 may be, the doping types of the doped base region 40 and the heavily doped region 70 can be n-type doping, so that the doping types of the substrate 10, the buffer layer 20, the drift region 30, the cap layer 50, the doped base region 40 and the heavily doped region 70 can be flexibly changed, the manufacturing difficulty of the MOSFET transistor 100 can be reduced, and the manufacturing efficiency of the MOSFET transistor 100 can be improved.
In some embodiments of the present invention, the substrate 10 and the cap layer 50 may be both heavily doped, the drift region 30 may be lightly doped, it should be explained that the concentration of the doped base region 40 depends on the designed threshold voltage, the substrate 10 and the cap layer 50 may be both p-type heavily doped, the substrate 10 and the cap layer 50 may also be both n-type heavily doped, the drift region 30 may be p-type lightly doped, the drift region 30 may also be n-type lightly doped, when the substrate 10 is p-type heavily doped, the drift region 30 is p-type lightly doped, the cap layer 50 is p-type heavily doped, the doped base region 40 is n-type doped, when the substrate 10 is heavily doped n-type, the drift region 30 is lightly doped n-type, the cap layer 50 is heavily doped n-type, the doped base region 40 is heavily doped p-type, this arrangement allows flexibility in changing the doping types of the substrate 10, the drift region 30 and the doped base region 40, so that the manufacture of the MOSFET transistor 100 can be facilitated.
In some embodiments of the present invention, the distance D between the orthographic projection of the heavily doped region 70 on the substrate 10 and the orthographic projection of the gate sidewall of the trench 60 on the substrate 10 may satisfy: d is more than or equal to 0 and less than or equal to Th, and Th is the sum of the widths of the grid 1 and the isolation medium 11. It is also understood that the orthographic projection of the heavily doped region 70 on the substrate 10 may coincide with the orthographic projection of the gate sidewall of the trench 60 on the substrate 10, the length of the orthographic projection of the gate sidewall of the trench 60 on the substrate 10 may also be greater than the length of the orthographic projection of the heavily doped region 70 on the substrate 10, but the length of the orthographic projection of the sidewall of the trench 60 on the substrate 10 is greater than the sum of the widths of the gate 1 and the isolation medium 11, and the distance between the orthographic projection of the heavily doped region 70 on the substrate 10 and the orthographic projection of the sidewall of the trench 60 on the substrate 10 may be designed according to the material structure and the performance of the MOSFET transistor 100, and thus the distance between the orthographic projection of the heavily doped region 70 and the orthographic projection of the sidewall of the trench 60 on the substrate 10 may be set to ensure.
In some embodiments of the present invention, the thickness of the doped base region 40 may be no less than 0.2 microns to avoid punch-through of the base region. It should be noted that the concentration and thickness of the doped base region 40 may be formed by an epitaxial growth method, or may be increased by an ion implantation method, according to the design of the threshold voltage and the breakdown voltage, the thickness of the doped base region 40 may be greater than 0.2 μm, if the thickness of the doped base region 40 is too thin, the doped base region is easy to punch through, if the thickness of the doped base region 40 is too thick, the length and resistance of the trench 60 may be increased, and meanwhile, the doping concentration of the doped base region 40 may be set to 1 × e15cm-3-5×e17cm-3This arrangement may provide better operation of the MOSFET transistor 100.
In some embodiments of the present invention, the thickness of the doped base region 40 may be 0.2 to 1 micrometer, and it should be explained that the thickness of the doped base region 40 may be set to be between 0.2 to 1 micrometer, and preferably, the thickness of the doped base region 40 may be set to be 0.5 micrometer, which may facilitate the production of the MOSFET transistor 100 and also ensure better operation performance of the MOSFET transistor 100.
As an embodiment, the doping concentration of the cap layer 50 located above the doped base region 40 may be greater than 1 × e19cm-3The thickness of the cap layer 50 above the doped base region 40 may be greater than 0.1 micrometer, and preferably, the thickness of the cap layer 50 is between 0.2 and 1 micrometer, so that the ohmic contact 130 may be prevented from being easily penetrated, the on-resistance may be prevented from being too large, and the difficulty in etching the trench 60 may also be reduced.
In some embodiments of the present invention, the doping concentration of heavily doped region 70 may be greater than 1 × e19cm-3It should be noted that the heavily doped region 70 at the bottom of the trench 60 and the doped base region 40 can be electrically connected by p-type heavily doped on the sidewall of the trench 60, the heavily doped region 70 at the bottom of the trench 60 and the heavily doped region 70 on the sidewall of the trench 60 can be formed by vertical ion implantation and oblique ion implantation, and thus the second electrode 3 can be electrically connected to the doped base region 40 at the same time, so as to suppress the bipolar junction transistor effect of the MOSFET transistor 100 and improve the reliability of the MOSFET transistor 100, and the doping concentrations of the heavily doped region 70 at the bottom of the trench 60 and the heavily doped region 70 on the sidewall of the trench 60 can be greater than 1 × e19cm-3This arrangement facilitates the formation of a good ohmic contact 130.
In some embodiments of the present invention, the depth of the trench 60 structure may be greater than the thickness of the doped base region 40, and it should be explained that when the depth of the trench 60 structure is greater than the thickness of the doped base region 40, the MOSFET transistor 100 may have better operating performance.
In some embodiments of the present invention, the depth of the portion of the trench 60 extending into the drift region 30 may be not less than 0.2 μm, it should be noted that the depth of the portion of the trench 60 extending into the drift region 30 may be 0.2 μm, the depth of the portion of the trench 60 extending into the drift region 30 may be greater than 0.2 μm, the portion of the trench 60 extending into the drift region 30 may become a portion of the schottky contact 140 region in the first cell region 110, the interval between the p-type heavily doped regions in the two trenches 60 is required to satisfy the requirement of electric field shielding of the trench gate and the schottky contact 140, and at the same time, a low resistance conductive channel needs to be provided, thereby enabling the MOSFET transistor 100 to have better operation performance.
In some embodiments of the present invention, the MOSFET transistor 100 may further comprise: a lightly doped conductive layer 300 (n-type conductive layer), the lightly doped conductive layer 300 may be located within the drift region 30 and may be located between two adjacent heavily doped regions 70, a doping type of the lightly doped conductive layer 300 may be the same as a doping type of the drift region 30, and a doping concentration may be greater than a doping concentration of the drift region 30. It should be explained that a JFET (Junction Field-Effect Transistor) region may be disposed between two adjacent heavily doped regions 70, the lightly doped conductive layer 300 may be located in the drift region 30, the lightly doped conductive layer 300 may be located between two adjacent heavily doped regions 70, if the doping type of the drift region 30 is n-type doping, the doping type of the lightly doped conductive layer 300 is n-type doping, and if the doping type of the drift region 30 is p-type doping, the doping type of the lightly doped conductive layer 300 is p-type doping, the doping concentration of the lightly doped conductive layer 300 may be greater than the doping concentration of the drift region 30, however, the doping concentration of the lightly doped conductive layer 300 needs to be designed in consideration of the electric field shielding effect, and if the doping concentration of the lightly doped conductive layer 300 is too high, the field shielding for the trench 60 and schottky contact 140 is weak and so arranged can further reduce the on-resistance of the JFET region.
As an embodiment, the width of the JFET region may be smaller than the width of the whole cell, and the smaller the width of the JFET region is, the better the shielding effect of the heavily doped region 70 on the gate dielectric electric field at the bottom of the trench 60 is, thereby reducing the width of the JFET region may increase the reliability of the MOSFET transistor 100, and improving the doping concentration of the JFET region may reduce the on-resistance of the JFET region, and the higher the doping concentration below the heavily doped region 70 is favorable for the carriers to better diffuse toward each direction of the drift layer 30 after passing through the trench 60, thereby reducing the diffusion of the carriers in each direction of the driftOn-resistance, and drift layer 30 under JFET region is used as voltage-resistant drift layer 30 of MOSFET transistor 100, the doping concentration and doping thickness of drift layer 30 can be determined according to the voltage-resistant capability of MOSFET transistor 100, for example, for MOSFET transistor 100 of 1200V, the concentration can be 5 × e15cm-3-20×e15cm-3The thickness may be between 7-15 microns.
In some embodiments of the present invention, the MOSFET transistor 100 may satisfy at least one of the following conditions: the material forming the substrate 10 includes SiC; the material forming the first metal layer 80 may include at least one of Ti, Mo, Ni, MoN, Pt, and the like. The material forming the second electrode 3 may include at least one of TiAl, TiNiAg, TiAu, and the like. The material forming the first electrode 2 may include TiNiAg, the thickness of the first electrode 2 may be greater than 1 μm, and the material forming the isolation medium 11 may include SiO2、Si3N4It should be noted that the material for forming the isolation medium 11 may include SiO2、Si3N4May also be SiO, the material forming the isolation dielectric 112And Si3N4. The gate 1 is a polysilicon gate, and it should be noted that the material forming the gate 1 may be polysilicon. The arrangement is convenient for the MOSFET transistor 100, and simultaneously, the MOSFET transistor 100 with different materials can be selected according to different conditions, so that the use performance of the MOSFET transistor 100 can be improved.
It should be noted that since the sidewalls of the trench 60 are on other crystal planes, the thermal oxidation rate is more than 2 times higher than that on the bottom surface of the trench 60, so that the gate dielectric on the bottom of the trench 60 is much smaller than that on the sidewalls of the trench 60 as a result of the conventional thermal oxidation method, which results in the gate dielectric on the bottom of the trench 60 having a large electric field at the gate voltage of the MOSFET transistor 100, and even breakdown, and reduces the reliability and lifetime of the MOSFET transistor 100. Therefore, in the gate dielectric preparation process, polysilicon can be deposited by LPCVD to make the polysilicon thickness at the bottom of the trench 60 greater than the sidewall thickness of the trench 60, then thermally oxidized, and then NO or N is used2O、POCl3Annealing in an equal atmosphere to improve interface traps. So that the total SiO2 thickness at the bottom of trench 60 is eventually equal to or greater than the sidewalls of trench 60. The gate dielectric thickness at the sidewalls of the trench 60 meets the design requirement of between 20-100 nanometers.
The gate source isolation dielectric 11 on top of the polysilicon may be SiO2、Si3N4. The second electrode 3 in the trench 60 and the isolation dielectric 11 of the polysilicon gate 1 are preferably SiO2Preferably greater than 0.5 microns. Formed by thermal oxidation of polysilicon, or by LPCVD deposition of SiO2And then etched, or a combination of the two, i.e. firstly thermally oxidizing the polysilicon and then depositing SiO by LPCVD2。
The first metal layer 80 may be a metal such as Ti, Ni, Mo, MoN, Pt, etc. and is annealed after deposition to improve the schottky contact 140. Meanwhile, since the surfaces of the p + region and the n + region are larger than 1E19cm-3Thus forming a good ohmic contact 130 with the heavily doped region 70 in the trench 60 and the cap layer 50 on the mesa. In addition, there is also a method in which polysilicon is used for the side wall of the trench 60, and since the fermi level of polysilicon is related to the doping concentration, the barrier height between SiC is related to the doping concentration of polysilicon, and the barrier height can be adjusted by adjusting the doping concentration of polysilicon here. While the heavily doped region 70 at the bottom of the trench 60 and the cap layer 50 on the mesa are formed of a metal, such as Ni, and RTA is performed to form ohmic contacts 130 to the heavily doped region 70 at the bottom of the trench 60 and the cap layer 50 on the mesa, maintaining schottky contacts 140 at the sidewalls of the trench 60.
The metal of the second electrode 3 can be TiAl, TiNiAg, TiAu or the like, and the thickness is more than 1 micron.
The first electrode 2 may comprise an ohmic contact to the first electrode 2 and a compact metal composition of the first electrode 2, which may be TiNiAg or the like, having a thickness greater than 1 micron.
The whole MOSFET transistor 100 consists of an active region, a junction terminal region and a scribing groove region, and metal extraction is respectively carried out on the grid 1 and the second electrode 3 of each cell on the active region, so that corresponding pressing block metal is made, and the subsequent packaging application of the MOSFET transistor 100 is facilitated.
It should be noted that, compared with the prior art, the MOSFET transistor 100 has a gate channel only on one side of the trench 60, so that the gate channel density is reduced by half, and the saturation current is reduced accordingly. The saturation current is determined by the channel resistance, and the short circuit endurance time of the MOSFET transistor 100 is determined by the saturation current:
tsC＝4ρCPΔTMAx/(EC×JD,sat)
where p semiconductor material density, CPIs the material characteristic heat capacity, Δ TMAXIs the maximum allowable temperature rise, ECCritical electric field strength. The saturation current is therefore directly related to the short circuit current tolerant capability of the MOSFET transistor 100. The short circuit current capability of the MOSFET transistor 100 is doubled.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the invention.
In the description of the present invention, "a plurality" means two or more.
In the description of the present invention, the first feature being "on" or "under" the second feature may include the first and second features being in direct contact, and may also include the first and second features being in contact with each other not directly but through another feature therebetween.
In the description of the invention, "above", "over" and "above" a first feature in a second feature includes the first feature being directly above and obliquely above the second feature, or simply means that the first feature is higher in level than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.
Claims (9)
1. A MOSFET transistor, comprising:
a substrate;
a buffer layer on one side of the substrate;
the drift region is positioned on one side of the buffer layer far away from the substrate;
the doped base region is positioned on one side of the drift region, which is far away from the buffer layer;
the cap layer is positioned on one side of the doped base region, which is far away from the drift region;
a plurality of trenches extending from one side of the cap layer to one side of the substrate and into the drift region;
a plurality of heavily doped regions located at least within the drift region and at the bottom of the trench,
the first metal layer covers part of the table top, part of the bottom and the side wall connected with the part of the bottom of the groove;
a gate dielectric layer and a gate electrode, the gate dielectric layer and the gate electrode are positioned in the trench and an isolation dielectric is arranged between the gate electrode and the first metal layer,
the first electrode is positioned on one side of the substrate far away from the buffer layer, the second electrode is filled in the groove and is in contact with the first metal layer,
the MOSFET transistor is provided with a first cell region and a second cell region, and a part of the heavily doped region in the second cell region further extends to the side wall of the groove at one side with the first metal layer.
2. The MOSFET transistor of claim 1, wherein the first metal layer in the second cell region forms an ohmic contact with the heavily doped region at the trench sidewalls and trench bottom, and with a cap layer on the portion of the mesa;
schottky contact is formed between the first metal layer in the first cell region and the drift region, and ohmic contact is formed between the Schottky contact and the cap layer on the part of the table-board.
3. The MOSFET transistor of claim 1, wherein the substrate, the buffer layer, the drift region, and the cap layer have a first doping type, and the doped base region and the heavily doped region have a second doping type.
4. The MOSFET transistor of claim 3, wherein the substrate and the cap layer are heavily doped and the drift region is lightly doped.
5. The MOSFET transistor of claim 1, wherein a distance D between an orthographic projection of the heavily doped region on the substrate and an orthographic projection of the gate sidewall of the trench on the substrate satisfies:
0≤D≤Th，
and Th is the sum of the widths of the grid electrode and the isolation medium.
6. The MOSFET transistor of claim 1, wherein the doped base region has a thickness of no less than 0.2 microns.
7. The MOSFET transistor of claim 1, wherein the depth of the trench is greater than the thickness of the doped base region.
8. The MOSFET transistor of claim 9, wherein the portion of the trench extending into the drift region has a depth of no less than 0.2 microns.
9. The MOSFET transistor of claim 1, further comprising:
the lightly doped conducting layer is positioned in the drift region and between two adjacent heavily doped regions, the doping type of the lightly doped conducting layer is the same as that of the drift region, and the doping concentration of the lightly doped conducting layer is greater than that of the drift region.
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| CN113097298A (en) * | 2021-03-30 | 2021-07-09 | 全球能源互联网研究院有限公司 | Insulated gate bipolar transistor and preparation method thereof |
| CN114843332A (en) * | 2022-04-27 | 2022-08-02 | 电子科技大学 | Low-power-consumption high-reliability half-packaged trench gate MOSFET device and preparation method thereof |
| CN114843332B (en) * | 2022-04-27 | 2023-04-25 | 电子科技大学 | Low-power-consumption high-reliability semi-package trench gate MOSFET device and preparation method thereof |
| CN116230774A (en) * | 2023-05-04 | 2023-06-06 | 南京第三代半导体技术创新中心有限公司 | Asymmetric silicon carbide trench gate MOSFET and manufacturing method thereof |
| CN116230774B (en) * | 2023-05-04 | 2023-07-25 | 南京第三代半导体技术创新中心有限公司 | Asymmetric silicon carbide trench gate MOSFET and manufacturing method thereof |
| CN118136672A (en) * | 2024-04-30 | 2024-06-04 | 河北博威集成电路有限公司 | Silicon carbide MOSFET device integrated with SBD and preparation method thereof |
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