CN111739934A - A Gallium Nitride High Electron Mobility Transistor with Junction Field Plate - Google Patents

Abstract

The invention provides a gallium nitride-based high electron mobility transistor with a junction field plate, which is characterized in that on the basis of a traditional gallium nitride HEMT device, a longitudinal PN junction is formed above a barrier layer of the transistor and is used as a surface electric field of a voltage-resistant structure modulation device, so that the transverse electric field distribution is optimized, and the purpose of improving the breakdown voltage is achieved. On one hand, when the grid is in a blocking state, the longitudinal PN junction diode can assist in depleting two-dimensional electron gas of a device channel, bear a part of drain voltage, reduce the voltage borne by the drain side at the edge of the grid, and reduce the peak electric field at the position. In a forward conduction state, the PN junction depletion region can prevent the grid from generating overlarge leakage current, and the forward conduction current capability of the device is ensured. Compared with the conventional metal field plate, the PN junction field plate does not introduce additional parasitic capacitance, ensures the working frequency and the switching speed of the device, and improves the reliability of the device while improving the breakdown voltage.

Description

A Gallium Nitride High Electron Mobility Transistor with Junction Field Plate

technical field

The invention belongs to the technical field of microelectronic devices, in particular to a gallium nitride-based high electron mobility transistor with a PN junction field plate, which can effectively improve the breakdown voltage of the device.

Background technique

GaN-based heterojunction field-effect transistors (GaN HEMTs) operate with high concentration and high electron mobility 2DEG formed in the AlGaN/GaN heterojunction channel. GaN material has excellent physical and chemical properties such as large band gap, high critical breakdown electric field (critical breakdown electric field is as high as 3.4MV/cm, 10 times that of Si material), thermal conductivity and radiation resistance. GaN-based heterojunction field effect transistors can maintain high reliability in high-voltage and high-power applications. At the same time, because of their fast electron saturation speed and high carrier mobility, high-speed switching fields also have a broad field. application space.

At present, the common GaN HEMT is a lateral device, and its schematic diagram is shown in FIG. 1, which mainly includes a substrate 210, a GaN buffer layer 201, a GaN channel layer 202, and an AlGaN barrier layer grown sequentially from bottom to top 203 and a source electrode 204, a gate electrode 205, and a drain electrode 206 respectively disposed on the upper surface of the AlGaN barrier layer, the source electrode 204 and the drain electrode 206 all form ohmic contact with the AlGaN barrier layer 203; the The gate 205 forms a Schottky contact with the AlGaN barrier layer 203 ; a passivation layer 209 is grown on the surface of the AlGaN barrier layer between the source electrode 204 and the drain electrode 206 .

For common GaN HEMTs, when a voltage is applied to the drain, the channel 2DEG between the gate and the drain cannot be fully depleted, so that there is an electric field concentration near the drain terminal at the gate edge. The electric field concentration will cause the device to break down prematurely and generate a leakage channel when a lower drain voltage is applied, resulting in leakage of the buffer layer, so that the advantages of the GaN material cannot be fully utilized, making the GaN-based heterojunction high electron The application of mobility transistors to high voltages is limited.

In order to give full play to the high critical breakdown electric field characteristics of GaN materials, researchers have proposed many technical measures to improve the voltage withstand capability of the device, among which the representative measures mainly include: field plate technology (such as gate field plate, source field plate , drain field plate), substrate transfer technology, ion implantation, buffer layer doping, superlattice buffer layer and back barrier technology, etc.

In 2001, Li J et al. in the literature (Li J, Cai S J, Pan G Z, et al. High breakdown voltage GaN HFET with field plate [J]. Electronics Letters, 2001, 37(3): 196-197.) for the first time It is disclosed that a field plate shorted to the gate is adopted. The introduction of the gate field plate can effectively reduce the electric field peak at the edge of the gate, expand the 2DEG depletion region of the channel between the gate and the drain, and make the gap between the gate and the drain. The electric field distribution is more uniform, thereby improving the withstand voltage. However, additional capacitance is formed between the field plate and the channel, which degrades the frequency and switching characteristics of the device.

The introduction of substrate transfer technology provides more possibilities to improve the breakdown voltage of GaN devices. Due to the narrow forbidden band width of the substrate, the conventional Si substrate device obviously cannot meet the growing demand for its withstand voltage, and the substrate transfer technology can effectively eliminate the premature breakdown caused by the insufficient withstand voltage of the Si substrate. In 2010, Bin Liu et al. in the literature (Bin Lu, Tomás Palacios. High Breakdown (>1500V) AlGaN/GaN HEMTs by Substrate-TransferTechnology [J]. IEEE Electron Device Letters, 2010, 31(9): 951-953) The report on the substrate transfer technology in China achieves a breakdown voltage greater than 1500V (gate-drain spacing is 20μm), while the on-resistance is only 5.3mΩ·cm ² . However, the process of substrate transfer technology is not yet fully mature, and its cost is greatly increased compared to Si substrates.

The buffer layer doping technology is also one of the methods to reduce the leakage current and increase the withstand voltage. Doping the buffer layer with impurities such as C and Fe constitutes a deep level trap, so that the electrons leaking into the buffer layer are trapped, causing the buffer layer to leak current. The value of is significantly reduced, thereby increasing the breakdown voltage of the device. However, doping C, Fe and other deep-level acceptor impurities in the buffer layer will cause current collapse and degrade the DC characteristics of the device.

The use of the AlGaN back-barrier buffer layer structure can increase the height of the barrier from the channel two-dimensional electron gas to the buffer layer, which limits the leakage of the channel two-dimensional electron gas to the buffer layer, reduces the leakage current, and increases the breakdown voltage. However, this method is limited in improving the breakdown voltage. On the one hand, the AlGaN back barrier will introduce traps between the buffer layer and the channel layer due to lattice mismatch; on the other hand, the AlGaN barrier layer and the AlGaN back barrier It has the opposite polarization effect, thereby reducing the two-dimensional electron gas concentration of the channel, which increases the on-resistance.

To sum up, these technical measures will introduce various problems while increasing the withstand voltage. How to improve the withstand voltage without affecting other performances of the device has become an urgent problem to be solved in GaN-based high electron mobility transistors.

SUMMARY OF THE INVENTION

The purpose of the present invention is to reduce the electric field peak at the gate edge by introducing the junction field plate structure, modulate the channel electric field to make its distribution more uniform, reduce the leakage current of the buffer layer, and improve the breakdown voltage. The invention provides a gallium nitride-based heterojunction field effect transistor with a junction field plate.

In order to solve its technical problem, the present invention adopts following technical scheme:

A GaN-based high electron mobility transistor with a junction field plate, the structure of which includes, from bottom to top, a substrate 210, a GaN buffer layer 201, a GaN channel layer 202, and an AlGaN barrier layer. 203, and the source electrode 204, the passivation layer 209, the gate electrode 205, the P-type doped gallium nitride semiconductor 207, the N-type doped gallium nitride semiconductor 208 and the drain electrode respectively disposed above the AlGaN barrier layer 203 206; the source electrode 204 and the drain electrode 206 both form ohmic contact with the AlGaN barrier layer 203; the gate electrode 205 forms a Schottky contact with the AlGaN barrier layer 203; the gate electrode 205 and the drain An N-type semiconductor layer 208 is grown on the surface of the AlGaN barrier layer 203 between the electrodes 206, and a P-type semiconductor layer 207 is grown on the surface of the N-type semiconductor layer 208. The P-type semiconductor 207 and the N-type semiconductor 208 form a PN junction Field plate; a passivation layer 209 is grown on the surface of the AlGaN barrier layer 203 between the source electrode 204 and the drain electrode 206 .

Preferably, the N-type doped semiconductor 208 is located above the AlGaN barrier layer 203 between the gate and the drain, and the P-type doped semiconductor 207 is located above the N-type doped semiconductor 208 between the gate and the drain ; The length of the N-type doped semiconductor 208 does not exceed the distance between the gate and the drain, and the length of the P-type doped semiconductor 207 does not exceed the length of the N-type doped semiconductor 208; the P-type doped semiconductor 207 and the The difference between the doping concentrations of the N-type doped semiconductor 208 is 10˜10 ⁴ .

As a preferred way, a PN junction field plate composed of a P-type doped semiconductor 207 and an N-type doped semiconductor 208 is repeatedly grown between the gate metal 205 and the drain metal 206, and the lengths of the multiple PN junction field plates are The sum does not exceed the spacing between gate and drain.

As a preferred way, the shape of the P-type doped semiconductor 207 is a slope, and the thickness of one end of the slope is greater than the thickness of the other end; the length of the P-type doped semiconductor 207 does not exceed the length of the N-type doped semiconductor 208, and both are A passivation layer 209 is grown over the P-type doped semiconductor 207 not exceeding the spacing between the gate and the drain.

As a preferred way, a protrusion is provided in the middle of the P-type doped semiconductor 207 , and the thickness and length of the protrusion are smaller than those of the N-type doped semiconductor 208 . layer 209.

As a preferred manner, the width of the P-type doped semiconductor 207 on the xoz plane decreases sequentially from the gate 205 to the drain 206 , and the width of the N-type doped semiconductor 208 on the xoz plane does not change.

As a preferred manner, the width of the P-type doped semiconductor 207 on the xoz plane increases sequentially from the gate 205 to the drain 206 , and the width of the N-type doped semiconductor 208 on the xoz plane does not change.

As a preferred manner, the material of the N-type doped semiconductor 208 is selected from any one or a combination of GaN, Si, GaAs, GaN, SiC, AlN, AlGaN and InGaN; the material of the P-type doped semiconductor 207 Any one or a combination of GaN, Si, GaAs, GaN, SiC, AlN, AlGaN and InGaN; the material of the passivation layer 209 is selected from SiO ₂ , HfO ₂ , Al ₂ O ₃ , Si ₃ A composite material formed by any one or more of N ₄ and La ₂ O ₃ ; the material of the substrate 210 is selected from any one of sapphire, Si and SiC.

The beneficial effects of the present invention are as follows: the purpose of the present invention is to overcome the problems that the gallium nitride-based high electron mobility transistor (GaNHEMT) has insufficient withstand voltage and cannot give full play to the high critical breakdown electric field and high electron saturation mobility of GaN materials. A gallium nitride-based high electron mobility transistor with a PN junction field plate, the technical solution of the present invention is to form a vertical PN junction above the aluminum gallium nitride barrier layer between the gate and the drain as a withstand voltage structure The surface electric field of the device is modulated, the lateral electric field distribution is optimized, and the purpose of increasing the breakdown voltage is achieved. On the one hand, when the gate is in the blocking state, the vertical PN junction diode will assist to deplete the two-dimensional electron gas of the device channel, bear part of the drain voltage, reduce the voltage on the drain side of the gate edge, reduce The peak electric field here. In the forward conduction state, the PN junction depletion region can prevent the gate from generating excessive leakage current and ensure the forward conduction current capability of the device. Meanwhile, compared with the conventional metal field plate, the field plate of the present invention does not introduce additional parasitic capacitance, which ensures the operating frequency and switching speed of the device, and improves the reliability of the device while increasing the breakdown voltage.

Description of drawings

FIG. 1 is a schematic structural diagram of a common gallium nitride high electron mobility transistor (GaN HEMT).

FIG. 2 is a schematic structural diagram of a GaN HEMT with a PN junction field plate provided by Embodiment 1 of the present invention.

FIG. 3 is a schematic structural diagram of a GaN HEMT with a PN junction field plate provided by Embodiment 2 of the present invention.

FIG. 4 is a schematic structural diagram of a GaN HEMT with a PN junction field plate provided by Embodiment 3 of the present invention.

FIG. 5 is a schematic structural diagram of a GaN HEMT with a PN junction field plate provided by Embodiment 4 of the present invention.

FIG. 6 is a schematic structural diagram of a GaN HEMT with a PN junction field plate provided by Embodiment 5 of the present invention.

FIG. 7 is a comparison of the breakdown characteristics of Example 1 of the present invention and a common GaN HEMT.

FIG. 8 is a comparison of the channel electric field of Example 1 of the present invention and a common GaN HEMT.

210 is the substrate, 201 is the GaN buffer layer, 202 is the GaN channel layer, 203 is the AlGaN barrier layer, 204 is the source, 205 is the gate, 206 is the drain, and 207 is the P-type semiconductor layer , 208 is an N-type semiconductor layer, and 209 is a passivation layer.

Detailed ways

The present invention will be described in further detail below with reference to specific examples, but the embodiments of the present invention are not limited to these examples.

FIG. 1 is a schematic structural diagram of a common gallium nitride high electron mobility transistor (GaN HEMT), which includes, from bottom to top, a substrate 210, a GaN buffer layer 201, a GaN channel layer 202, and an AlGaN barrier. The source electrode 204, the gate electrode 205, the drain electrode 206 and the passivation layer 209 formed above the layer 203 and the AlGaN barrier layer, wherein the source electrode 204 and the drain electrode 206 respectively form ohmic contact with the AlGaN barrier layer 203, The gate 205 forms a Schottky contact with the AlGaN barrier layer 203 .

Example 1

This embodiment provides a GaN-based high electron mobility transistor. As shown in FIG. 2 , the structure of the transistor includes, from bottom to top, a substrate 210 , a GaN buffer layer 201 , a GaN channel layer 202 , and an AlGa The nitrogen barrier layer 203, and the source electrode 204, the passivation layer 209, the gate electrode 205, the P-type doped gallium nitride semiconductor 207, and the N-type doped gallium nitride semiconductor respectively disposed above the aluminum gallium nitrogen barrier layer 203 208 and drain 206; both the source 204 and the drain 206 form ohmic contact with the AlGaN barrier layer 203; the gate 205 forms Schottky contact with the AlGaN barrier layer 203; An N-type semiconductor layer 208 is grown on the surface of the AlGaN barrier layer 203 between the electrode 205 and the drain 206, and a P-type semiconductor layer 207 is grown on the surface of the N-type semiconductor layer 208. The P-type semiconductor 207 and the N-type semiconductor 208 A PN junction field plate is formed; a passivation layer 209 is grown on the surface of the AlGaN barrier layer 203 between the source electrode 204 and the drain electrode 206 .

The N-type doped semiconductor 208 is located above the AlGaN barrier layer 203 between the gate and the drain, and the P-type doped semiconductor 207 is located above the N-type doped semiconductor 208 between the gate and the drain; The length of the doped semiconductor 208 does not exceed the distance between the gate and the drain, and the length of the P-type doped semiconductor 207 does not exceed the length of the N-type doped semiconductor 208; the P-type doped semiconductor 207 and the N-type doped semiconductor The difference between the doping concentrations of the semiconductors 208 is 10˜10 ⁴ .

Table 1 is the simulation structure parameters of common HEMT and embodiment 1 of the present invention:

Table 1 Comparison of device simulation parameters and results

Device parameters Ordinary HEMT PN junction field plate HEMT P-type semiconductor doping concentration -- 3×10¹⁸cm^-3 N-type semiconductor doping concentration -- 3×10¹⁶cm^-3 P-type semiconductor thickness -- 0.1μm N-type semiconductor thickness -- 0.1μm P-type semiconductor length -- 3μm N-type semiconductor length -- 3μm Source gate passivation layer thickness 0.2μm 0.2μm Source gate passivation layer length 1μm 1μm Passivation layer thickness at drain 0.2μm 0.2μm Length of passivation layer at drain 2μm 2μm Gate to source spacing 1μm 1μm Gate to drain pitch 5μm 5μm gate length 0.5μm 0.5μm AlGaN barrier layer thickness 20nm 20nm Al composition of AlGaN barrier layer 0.28 0.28 GaN channel layer thickness 30nm 30nm GaN buffer layer thickness 1μm 1μm Breakdown Voltage (@I_DS＝1μA/mm) 760V 425V

FIG. 7 and FIG. 8 compare the simulation results of Embodiment 1 and a common HEMT, and the results fully reflect the advantages of the present invention for increasing the breakdown voltage. It can be seen from the simulation results in Figure 7 that the breakdown voltage of the common HEMT device is 425V (the breakdown current criterion is 1 μA/mm), while the breakdown voltage of Example 1 of the present invention is 760V (the breakdown current criterion is 1 μA) /mm). FIG. 8 is a comparison diagram of the distribution of the electric field intensity of the channel. It can be clearly seen from FIG. 8 that Example 1 can significantly reduce the electric field peak value at the gate edge, make the electric field distribution of the channel more uniform, and thus improve the breakdown voltage of the device.

Example 2

As shown in FIG. 3 , the difference between this embodiment and Embodiment 1 is that there are three PN junctions composed of P-type doped semiconductors 207 and N-type doped semiconductors 208 between the gate metal 205 and the drain metal 206 . Field plates, there is a passivation layer 209 between the PN junction field plates. The sum of the lengths of the plurality of PN junction field plates does not exceed the distance between the gate and the drain.

Example 3

As shown in FIG. 4 , the difference between this embodiment and Embodiment 1 is that the shape of the P-type doped semiconductor 207 is a slope, and the thickness of one end of the slope is greater than the thickness of the other end; the length of the P-type doped semiconductor 207 does not exceed A passivation layer 209 is grown over the P-type doped semiconductor 207 for the length of the N-type doped semiconductor 208, and neither of them exceeds the distance between the gate and the drain.

Example 4

As shown in FIG. 5 , the difference between this embodiment and Embodiment 1 is that the P-type doped semiconductor 207 is provided with a protrusion in the middle, and the thickness and length of the protrusion are smaller than the thickness and length of the N-type doped semiconductor 208 . length, a passivation layer 209 is grown over the P-type doped semiconductor 207 .

Example 5

As shown in FIG. 6 , the difference between this embodiment and Embodiment 1 is that the width of the P-type doped semiconductor 207 on the xoz plane decreases sequentially from the gate 205 to the drain 206 , and the N-type doped semiconductor 208 is on the xoz plane. The width does not change.

Example 6

The difference between this embodiment and Embodiment 1 is that the width of the P-type doped semiconductor 207 on the xoz plane increases sequentially from the gate 205 to the drain 206, and the width of the N-type doped semiconductor 208 on the xoz plane is unchanged.

The above are only preferred embodiments of the present invention, and do not limit the present invention in any form. Any simple modifications and equivalent changes made to the above embodiments according to the technical essence of the present invention all fall into the present invention. within the scope of protection.

Claims (8)

1. A GaN-based high electron mobility transistor with a junction field plate, characterized in that: its structure sequentially comprises from bottom to top: a substrate (210), a GaN buffer layer (201), a GaN channel A channel layer (202), an AlGaN barrier layer (203), and a source electrode (204), a passivation layer (209), a gate electrode (205), a source electrode (204), a passivation layer (209), a gate electrode (205), P-type doped gallium nitride semiconductor (207), N-type doped gallium nitride semiconductor (208) and drain electrode (206); the source electrode (204) and the drain electrode (206) are both connected with AlGaN The barrier layer (203) forms an ohmic contact; the gate (205) forms a Schottky contact with the AlGaN barrier layer (203); the AlGaN between the gate (205) and the drain (206) An N-type semiconductor layer (208) is grown on the surface of the barrier layer (203), a P-type semiconductor layer (207) is grown on the surface of the N-type semiconductor layer (208), and the P-type semiconductor (207) and the N-type semiconductor (208) A PN junction field plate is formed; a passivation layer (209) is grown on the surface of the AlGaN barrier layer (203) between the source electrode (204) and the drain electrode (206). 2. A GaN-based high electron mobility transistor with a junction field plate according to claim 1, characterized in that: the N-type doped semiconductor (208) is located between the gate and the drain of aluminum gallium Above the nitrogen barrier layer (203), the P-type doped semiconductor (207) is located above the N-type doped semiconductor (208) between the gate and the drain; the length of the N-type doped semiconductor (208) does not exceed the gate The distance between the P-type doped semiconductor (207) and the drain does not exceed the length of the N-type doped semiconductor (208); the P-type doped semiconductor (207) and the N-type doped semiconductor (208) ) in the doping concentration difference is 10 to 10 ⁴ . 3. A GaN-based high electron mobility transistor with a junction field plate according to claim 1, characterized in that: a P-type doped semiconductor (207) and an N-type doped semiconductor (208) are composed of A plurality of PN junction field plates are repeatedly grown between the gate metal (205) and the drain metal (206), and the sum of the lengths of the plurality of PN junction field plates does not exceed the distance between the gate and the drain. 4. The GaN-based high electron mobility transistor with a junction field plate according to claim 1, wherein the shape of the P-type doped semiconductor (207) is a slope, and the thickness of one end of the slope is greater than the thickness of the other end; the length of the P-type doped semiconductor (207) does not exceed the length of the N-type doped semiconductor (208), and neither exceeds the distance between the gate and drain A passivation layer (209) is grown over the semiconductor (207). 5 . The GaN-based high electron mobility transistor with a junction field plate according to claim 1 , wherein the P-type doped semiconductor ( 207 ) is provided with a protrusion in the middle, and the protrusion The thickness and length of the rising portion are smaller than those of the N-type doped semiconductor (208), and a passivation layer (209) is grown on the P-type doped semiconductor (207). 6. A GaN-based high electron mobility transistor with a junction field plate according to claim 1, characterized in that: the width of the P-type doped semiconductor (207) on the xoz plane is from the gate (205) ) to the drain (206) decreases sequentially, and the width of the N-type doped semiconductor (208) on the xoz plane does not change. 7. The GaN-based high electron mobility transistor with a junction field plate according to claim 1, wherein the width of the P-type doped semiconductor (207) on the xoz plane is from the gate (205) ) to the drain (206) increase sequentially, and the width of the N-type doped semiconductor (208) on the xoz plane is unchanged. 8. The GaN-based high electron mobility transistor with a junction field plate according to any one of claims 1 to 7, wherein the N-type doped semiconductor (208) material is selected from GaN , Si, GaAs, GaN, SiC, AlN, AlGaN and InGaN any one or a combination of several; the material of the P-type doped semiconductor (207) is selected from GaN, Si, GaAs, GaN, SiC, AlN, Any one or a combination of AlGaN and InGaN; the material of the passivation layer (209) is selected from any one of SiO ₂ , HfO ₂ , Al ₂ O ₃ , Si ₃ N ₄ and La ₂ O ₃ or Several composite materials are formed; the material of the substrate (210) is selected from any one of sapphire, Si and SiC.

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