CN110309090B - A kind of interface unit - Google Patents
A kind of interface unit Download PDFInfo
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- CN110309090B CN110309090B CN201910563815.3A CN201910563815A CN110309090B CN 110309090 B CN110309090 B CN 110309090B CN 201910563815 A CN201910563815 A CN 201910563815A CN 110309090 B CN110309090 B CN 110309090B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
- H01R13/648—Protective earth or shield arrangements on coupling devices, e.g. anti-static shielding
- H01R13/652—Protective earth or shield arrangements on coupling devices, e.g. anti-static shielding with earth pin, blade or socket
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R27/00—Coupling parts adapted for co-operation with two or more dissimilar counterparts
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Details Of Connecting Devices For Male And Female Coupling (AREA)
Abstract
The present application provides a connector, comprising: one side of the connector comprises a plurality of groups of signal pins and a group of first grounding pins, each group of signal pins comprises two first signal pins, and any group of signal pins shares the first grounding pins; the other side of the connector comprises a plurality of groups of signal pins and a group of second grounding pins, each group of signal pins comprises two second signal pins, and any group of signal pins shares the second grounding pins; connecting any group of signal pins included at one side of the connector with corresponding target equipment signal pins to be connected, wherein the target equipment to be connected is connected with a UART interface of a processor; and any group of signal pins included on the other side of the connector are connected with the corresponding target serial port signal pins to be connected, and the second grounding pin included on the other side of the connector is connected with the corresponding target serial port grounding pins to be connected.
Description
Technical Field
The present application relates to the field of electronic technology, and more particularly, to a connector.
Background
At present, in order to debug a processor conveniently, a UART (Universal Asynchronous Receiver/Transmitter) interface is generally integrated on the processor, and the UART interface is connected to a serial port of a computer host to output debugging information of the processor, so that a designer can conveniently perform related debugging design.
Since the serial port of the computer host is RS-232 (asynchronous transfer standard interface established by the american electronic industry association, RS-232 interface is generally an interface standard for serial data communication with 9 pins (DB-9)) level, and the UART interface of the processor is TTL (Time To Live) level. In order to smoothly output debugging information of the processor to the computer host, the TTL level of the UART interface of the processor is converted into the RS-232 level through the level conversion chip, three signals TXD, RXD and GND of the RS-232 level are connected to the RJ45 socket, and a cable with one side provided with an RJ45 plug and the other side provided with a DB-9 plug is used for connecting the computer host.
With the increasing number of hardware devices designed by multiple processors, a solution is urgently needed for outputting the debugging information of the multiple processors, and multiple serial ports can be designed for the multiple processors so as to output the debugging information of the multiple processors.
Disclosure of Invention
In view of the above, the present application provides a connector.
Specifically, the method is realized through the following technical scheme:
a connector, comprising:
one side of the connector comprises a plurality of groups of signal pins and a group of first grounding pins, each group of signal pins comprises two first signal pins, and any group of signal pins shares the first grounding pins;
the other side of the connector comprises a plurality of groups of signal pins and a group of second grounding pins, each group of signal pins comprises two second signal pins, and any group of signal pins shares the second grounding pins;
the connector comprises a connector body, a plurality of groups of signal pins and a group of first grounding pins, wherein the plurality of groups of signal pins and the group of first grounding pins which are arranged on one side of the connector body are correspondingly connected with the plurality of groups of signal pins and the group of second grounding pins which are arranged on the other side of the connector body in a one-to-one correspondence mode in a preset mode;
connecting any group of signal pins included at one side of the connector with corresponding target equipment signal pins to be connected, wherein the target equipment to be connected is connected with a UART interface of a processor;
and any group of signal pins included on the other side of the connector are connected with the corresponding target serial port signal pins to be connected, and the second grounding pin included on the other side of the connector is connected with the corresponding target serial port grounding pins to be connected.
The connector that this application embodiment provided, through connector one side multiunit signal pin, be connected with a plurality of target device signal pins of treating to connect that correspond, multiunit signal pin through the connector opposite side is connected with the target serial ports signal pin of treating to connect that corresponds, second ground pin to the connector opposite side includes, be connected with a plurality of target serial ports ground pin of treating to connect that correspond, wherein, treat target device and treater UART interface connection of connecting, multiunit signal pin and a set of first ground pin that connector one side includes, multiunit signal pin and a set of second ground pin that include with the connector opposite side are connected through presetting mode one-to-one. Therefore, the embodiment of the application can realize that the multi-channel serial port outputs the debugging information of a plurality of processors.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required in the description of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art according to the drawings.
FIG. 1 is a schematic diagram of an application scenario illustrated in an exemplary embodiment of the present application;
FIG. 2 is a schematic diagram of a left side pin of a connector according to an exemplary embodiment of the present application;
FIG. 3 is a diagram illustrating a right side pin of a connector according to an exemplary embodiment of the present application;
fig. 4 is a schematic diagram illustrating internal connections between a left pin and a right pin of a connector according to an exemplary embodiment of the present application.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
As shown in fig. 1, for an application scenario schematic diagram shown in the embodiment of the present application, a UART interface of a processor is connected to a corresponding level shift chip (MAX3232), the level shift chip is connected to a connector, the connector is connected to an RJ45 socket, and the RJ45 socket is connected to a computer through a special cable, so that multi-channel serial ports can output debugging information of multiple processors, and output is simultaneously implemented without switching control, which brings great convenience to debugging and configuration of a multiprocessor device.
For the connector in the embodiment of the present application, one side of the connector includes a plurality of groups of signal pins and a group of first ground pins, each group of signal pins includes two first signal pins, and any group of signal pins shares the first ground pin.
The connector comprises a first receiving signal pin and a first sending signal pin, wherein any group of signal pins included on one side of the connector comprises the first receiving signal pin and the first sending signal pin.
For example, as shown in fig. 2, on the left side of the connector, three signal pins and a set of first ground pins are included, for the first set of signal pins, including TXD1 pin and RXD1 pin, for the second set of signal pins, including TXD2 pin and RXD2 pin, and for the third set of signal pins, including TXD3 pin and RXD3 pin.
And the other side of the connector comprises a plurality of groups of signal pins and a group of second grounding pins, each group of signal pins comprises two second signal pins, and any group of signal pins shares the second grounding pins.
And any group of signal pins on the other side of the connector comprises a second receiving signal pin and a second sending signal pin.
For example, as shown in fig. 3, on the right side of the connector, three sets of signal pins including TXD1 pin and RXD1 pin are included, for the first set of signal pins, TXD2 pin and RXD2 pin are included, and for the third set of signal pins, TXD3 pin and RXD3 pin are included.
As for the multiple groups of signal pins and the group of first ground pins included on one side of the connector, the multiple groups of signal pins and the group of second ground pins included on the other side of the connector are connected in a one-to-one correspondence manner in a preset manner, as shown in fig. 4. The preset mode may be a dial switch, a jumper cap, a jumper wire, or an internal conductor, which is not limited in the embodiment of the present application.
For any group of signal pins included on one side of the connector, the signal pins are connected with corresponding target equipment to be connected, wherein the target equipment to be connected is connected with a UART interface of the processor, and the method specifically comprises the following steps:
the signal pins of any group included on one side of the connector comprise a first receiving signal pin and a first sending signal pin, the first receiving signal pin is connected with the corresponding receiving signal pin of the target device to be connected, and the first sending signal pin is connected with the corresponding sending signal pin of the target device to be connected. Wherein the target device to be connected is a level shift chip (e.g., MAX 3232).
For example, the left side of the connector includes three sets of quotation marks, for the first set of signal pins, the TXD1 pin is connected to the TXD1 pin of MAX3232A as shown in fig. 1, the RXD1 pin is connected to the RXD1 pin of MAX3232A as shown in fig. 1, for the second set of signal pins, the TXD2 pin is connected to the TXD2 pin of MAX3232A as shown in fig. 1, the RXD2 pin is connected to the RXD2 pin of MAX3232A as shown in fig. 1, for the third set of signal pins, the TXD3 pin is connected to the TXD3 pin of MAX3232B as shown in fig. 1, and the RXD3 pin is connected to the RXD3 pin of MAX32 3232A as shown in fig. 1.
To arbitrary a set of signal pin that the connector opposite side includes, be connected with the target serial ports signal pin of waiting to connect that corresponds, to the second ground pin that the connector opposite side includes, be connected with a plurality of target serial ports ground pin of waiting to connect that correspond, specifically be:
any group of signal pins on the other side of the connector comprises a second signal receiving pin and a second signal sending pin, the second signal receiving pin is connected with the corresponding target serial port signal receiving pin to be connected, and the second signal sending pin is connected with the corresponding target serial port signal sending pin to be connected. The target serial port to be connected is an RJ45 socket, and the RJ45 socket has 3 pins.
For example, on the right side of the connector, three sets of signal pins and a set of second ground pin are included, for the first set of signal pins, the TXD1 pin is connected to the TXD1 pin of the RJ45 socket 1 shown in fig. 1, the RXD1 pin is connected to the RXD1 pin of the RJ45 socket 1 shown in fig. 1, for the second set of signal pins, the TXD2 pin is connected to the TXD2 pin of the RJ45 socket 2 shown in fig. 1, the RXD2 pin is connected to the RXD2 pin of the RJ45 socket 2 shown in fig. 1, for the third set of signal pins, the TXD3 pin is connected to the TXD3 pin of the RJ45 socket 3 shown in fig. 1, the RXD3 pin is connected to the RXD3 pin of the RJ45 socket 3 shown in fig. 1, and the second ground pin is connected to the ground pin of the RJ45 socket 1, the RJ45 socket 2 and.
For the RJ45 socket, a cable with one end being an RJ45 plug and the other end being a DB-9 plug can be designed, and the cable can be used to connect a computer with the RJ45 socket and output debugging information of a multiprocessor.
For the connector provided by the embodiment of the application, the increased cost is lower, and the abnormal situation is easy to position.
Through the above description to the connector that this application embodiment provided, through connector one side multiunit signal pin, with a plurality of target device signal pins that wait to connect that correspond connect, multiunit signal pin through the connector opposite side is connected with the target serial ports signal pin that waits to connect that corresponds, to the second ground pin that the connector opposite side includes, with a plurality of target serial ports ground pin that wait to connect that correspond connect and connect, wherein, wait to connect target device and treater UART interface connection, multiunit signal pin and a set of first ground pin that connector one side includes, multiunit signal pin and a set of second ground pin that include with the connector opposite side are connected through presetting mode one-to-one. Therefore, the embodiment of the application can realize that the multi-channel serial port outputs the debugging information of a plurality of processors.
The implementation process of the functions of each unit in the device is specifically described in the implementation process of the corresponding step in the method, and is not described herein again.
For the device embodiments, since they substantially correspond to the method embodiments, reference may be made to the partial description of the method embodiments for relevant points. The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of the application. One of ordinary skill in the art can understand and implement it without inventive effort.
The invention may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The invention may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.
The foregoing is directed to embodiments of the present invention, and it is understood that various modifications and improvements can be made by those skilled in the art without departing from the spirit of the invention.
Claims (6)
1. A connector, comprising:
one side of the connector comprises a plurality of groups of signal pins and a group of first grounding pins, each group of signal pins comprises two first signal pins, and any group of signal pins shares the first grounding pins;
the other side of the connector comprises a plurality of groups of signal pins and a group of second grounding pins, each group of signal pins comprises two second signal pins, and any group of signal pins shares the second grounding pins;
the connector comprises a connector body, a plurality of groups of signal pins and a group of first grounding pins, wherein the plurality of groups of signal pins and the group of first grounding pins which are arranged on one side of the connector body are correspondingly connected with the plurality of groups of signal pins and the group of second grounding pins which are arranged on the other side of the connector body in a one-to-one correspondence mode in a preset mode;
connecting any group of signal pins included at one side of the connector with corresponding target equipment signal pins to be connected, wherein the target equipment to be connected is connected with a UART interface of a processor;
and any group of signal pins included on the other side of the connector are connected with the corresponding target serial port signal pins to be connected, and the second grounding pin included on the other side of the connector is connected with the corresponding target serial port grounding pins to be connected.
2. The connector according to claim 1, wherein the signal pins included in the connector include a first reception signal pin and a first transmission signal pin.
3. The connector according to claim 2, wherein the connecting any group of signal pins included in one side of the connector with corresponding target device signal pins to be connected comprises:
for a first receiving signal pin in any group included at one side of the connector, connecting with a corresponding receiving signal pin of target equipment to be connected;
and connecting the first signal transmission pins in any group included at one side of the connector with the corresponding signal transmission pins of the target equipment to be connected.
4. The connector of claim 1, wherein the signal pins included on the other side of the connector include a second receive signal pin and a second transmit signal pin.
5. The connector according to claim 4, wherein the connecting any one group of signal pins included on the other side of the connector with the corresponding target serial port signal pin to be connected comprises:
connecting a second receiving signal pin in any group included at the other side of the connector with a corresponding receiving signal pin of a target serial port to be connected;
and connecting the second signal sending pins in any group included at the other side of the connector with the corresponding target serial port signal sending pins to be connected.
6. The connector according to any one of claims 1 to 5, wherein the target serial port to be connected is an RJ45 socket, and the target device to be connected is a level conversion chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910563815.3A CN110309090B (en) | 2019-06-26 | 2019-06-26 | A kind of interface unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910563815.3A CN110309090B (en) | 2019-06-26 | 2019-06-26 | A kind of interface unit |
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| Publication Number | Publication Date |
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| CN110309090A CN110309090A (en) | 2019-10-08 |
| CN110309090B true CN110309090B (en) | 2021-06-29 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201910563815.3A Active CN110309090B (en) | 2019-06-26 | 2019-06-26 | A kind of interface unit |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN203658990U (en) * | 2013-11-29 | 2014-06-18 | 深圳中电长城信息安全系统有限公司 | Debugging device for central processing unit |
| CN105470675A (en) * | 2014-09-03 | 2016-04-06 | 联想(北京)有限公司 | Electric connector |
| CN105786742A (en) * | 2014-12-24 | 2016-07-20 | 中兴通讯股份有限公司 | Server serial port switching apparatus and method, and server |
| CN206226832U (en) * | 2016-09-21 | 2017-06-06 | 重庆零度智控智能科技有限公司 | A kind of flexible PCB |
| CN109582620A (en) * | 2018-12-21 | 2019-04-05 | 郑州云海信息技术有限公司 | A kind of UART interface conversion equipment and interface conversion method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5772453A (en) * | 1996-10-01 | 1998-06-30 | Hon Hai Precision Ind. Co., Ltd. | Side-by-side dual port USB connector |
| US8984184B2 (en) * | 2013-04-05 | 2015-03-17 | William Marsh Rice University | System and method for managing input/output data of peripheral devices |
| CN203350870U (en) * | 2013-06-05 | 2013-12-18 | 福建星网锐捷通讯股份有限公司 | Switching circuit based on multiplexing of multiple processor serial ports on veneer |
-
2019
- 2019-06-26 CN CN201910563815.3A patent/CN110309090B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN203658990U (en) * | 2013-11-29 | 2014-06-18 | 深圳中电长城信息安全系统有限公司 | Debugging device for central processing unit |
| CN105470675A (en) * | 2014-09-03 | 2016-04-06 | 联想(北京)有限公司 | Electric connector |
| CN105786742A (en) * | 2014-12-24 | 2016-07-20 | 中兴通讯股份有限公司 | Server serial port switching apparatus and method, and server |
| CN206226832U (en) * | 2016-09-21 | 2017-06-06 | 重庆零度智控智能科技有限公司 | A kind of flexible PCB |
| CN109582620A (en) * | 2018-12-21 | 2019-04-05 | 郑州云海信息技术有限公司 | A kind of UART interface conversion equipment and interface conversion method |
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| Publication number | Publication date |
|---|---|
| CN110309090A (en) | 2019-10-08 |
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