CN118339647A

CN118339647A - Three-dimensional phase change memory and manufacturing method thereof

Info

Publication number: CN118339647A
Application number: CN202280005288.4A
Authority: CN
Inventors: 刘峻
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2022-11-11
Filing date: 2022-11-11
Publication date: 2024-07-12
Also published as: WO2024098391A1

Abstract

Disclosed herein is a 3D PCM architecture having a 3D PCM array with word lines and bit lines on a first die, a word line decoder on a second die, and the first die and the second die being hybrid bonded to each other in a face-to-face arrangement. By removing the word line decoder from the first die and implementing the word line decoder on the second die, the layout of the 3D PCM array may be rearranged in order to increase the bit density of the 3DPCM array. By making available the die area that would otherwise be occupied by the word line decoder and the contacts between the decoder and the word lines in the array, the 3D PCM array can be moved closer to each other while still providing an electrical path between the word lines in the array on the first die and the output terminals of the word line decoder circuitry on the second die.

Description

Three-dimensional phase change memory and manufacturing method thereof

Background

The present disclosure relates to three-dimensional (3D) Phase Change Memory (PCM) devices and methods of manufacturing the same.

Planar memory cells are scaled to smaller dimensions by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of the memory cell approaches the lower limit, planar processing and fabrication techniques become challenging and costly. As a result, the storage density of the planar memory cell approaches the upper limit.

The 3D memory architecture can address density limitations in planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. For example, phase Change Memories (PCMs) may utilize differences between the resistivity of amorphous and crystalline phases in phase change materials based on electrothermal heating and quenching of the phase change materials. PCM array cells may be vertically stacked in 3D to form a 3D PCM.

Disclosure of Invention

Disclosed herein is a 3D PCM architecture having a 3D PCM array with word lines and bit lines on a first die, a word line decoder on a second die, and the first die and the second die are hybrid bonded to each other in a face-to-face arrangement. By removing the word line decoder circuitry from the first die and implementing the word line decoder circuitry on the second die, the layout of the 3D PCM array may be rearranged to increase the bit density of the array while still providing an electrical path between the word lines in the array on the first die and the output terminals of the word line decoder circuitry on the second die.

In one example, a 3D PCM includes a first die having at least one bit line decoder, at least one PCM cell array including a plurality of bit lines coupled to the first bit line decoder in the at least one bit line decoder, a plurality of word lines coupled to the at least one PCM cell array, and a first bonding layer configured for hybrid bonding, the first bonding layer disposed on a top side of the first die. And further comprising a second die having at least one word line decoder circuit and a second bonding layer configured for hybrid bonding, the second bonding layer disposed on a top side of the second die. The first bonding layer has a plurality of first bonding contacts disposed therein and the second bonding layer has a plurality of second bonding contacts disposed therein. In this example, the first die and the second die are hybrid bonded to each other in a face-to-face arrangement such that at least a portion of the first bonding contact and at least a portion of the second bonding contact are electrically connected to each other.

In another example, a 3D memory includes a first die having a first substrate, a bit line decoder circuit disposed on the first substrate, an array of PCM cells disposed over the bit line decoder circuit, a first bonding layer configured for hybrid bonding, the first bonding layer disposed on a top side of the first die. In this example, the PCM cell array includes a plurality of bit lines and a plurality of word lines. The 3D memory of this example also includes a second die having a second substrate, word line decoder circuitry disposed on the second substrate, and a second bonding layer configured for hybrid bonding, wherein the second bonding layer is disposed on a top side of the second die. In this embodiment, the first bonding layer has a plurality of first bonding contacts disposed therein and the second bonding layer has a plurality of second bonding contacts disposed therein, and the plurality of first bonding contacts and the plurality of second bonding contacts are electrically conductive. And, in this example, the top side of the first die and the top side of the second die are hybrid bonded to each other in a face-to-face orientation such that at least a portion of the plurality of first bonding contacts and at least a portion of the plurality of second bonding contacts are electrically connected to each other.

In another example according to the present disclosure, a 3D PCM device includes a bit line decoder circuit disposed on a first die, a first hybrid bond layer disposed on a first surface of the first die, and a 3D PCM cell array disposed over the bit line decoder circuit. The 3D PCM cell array has a plurality of bit lines and a plurality of word lines, which are configured together with the 3D PCM cell array as a 3D PCM cross-point memory. Such a 3D PCM device according to the present disclosure further includes a word line decoder circuit disposed on the second die, a second hybrid bonding interface disposed on the first surface of the second die, and a pad extraction dielectric layer disposed on the second surface of the second die; wherein the first die and the second die are bonded to each other such that the first hybrid bonding layer and the second hybrid bonding layer are in direct contact with each other, the plurality of bit lines are electrically coupled to bit line decoder circuitry disposed on the first die, and the plurality of word lines are electrically coupled to word line decoder circuitry disposed on the second die.

Drawings

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable a person skilled in the pertinent art to make and use the disclosure.

Fig. 1 is a perspective view of an exemplary 3D PCM device having a cross-point arrangement.

Fig. 2A is a block diagram of an exemplary 3D PCM device having a cross-point arrangement.

Fig. 2B is a plan view of the exemplary 3D PCM device of fig. 2A having a cross-point arrangement.

Fig. 2C is a perspective view of the exemplary 3D PCM device of fig. 2A having a cross-point arrangement.

Fig. 3A is a block diagram of an exemplary 3D PCM storage device according to the present disclosure.

Fig. 3B is a plan view of the exemplary 3D PCM storage device of fig. 3A according to some embodiments of the present disclosure.

Fig. 3C is a perspective view of the exemplary 3D PCM storage device of fig. 3A according to the present disclosure.

Fig. 4A is a perspective view of another exemplary 3D PCM storage device according to the present disclosure.

Fig. 4B is a perspective view of yet another exemplary 3D PCM storage device according to the present disclosure.

Fig. 5A-5L illustrate an exemplary fabrication process for forming a 3D PCM storage device according to the present disclosure.

Fig. 6 is a flowchart of an exemplary method for forming a 3D PCM storage device according to the present disclosure.

Fig. 7 is a schematic stick diagram illustration of a previous 3D PCM array architecture with bit line decoder circuitry and word line decoder circuitry on the same die as the 3D PCM array, and thus occupying area that could otherwise be used for memory cells.

Fig. 8A is a block diagram illustrating a first die with bit line decoder circuitry, PCM cell array, and hybrid bonding layer, a second die with word line decoder circuitry and another hybrid bonding layer oriented in a face-to-face arrangement prior to hybrid bonding.

Fig. 8B is a block diagram illustrating the first die and the second die of fig. 8A after hybrid bonding to each other.

Fig. 9 is a cross-sectional view of an exemplary first die including bit line decoder circuitry, a 3D PCM cell array disposed over the bit line decoder circuitry, and a first hybrid bonding layer disposed on a top side thereof.

Fig. 10A is a cross-sectional view of an example in a partially fabricated state to a second die that includes word line decoder circuitry and array circuitry.

Fig. 10B is a cross-sectional view of an exemplary second die including word line decoder circuitry, array circuitry, a second bonding layer, and a second bonding contact.

FIG. 11 is a cross-sectional view of an exemplary multi-die 3D PCM memory product having a PCM array on one die and a word line decoder associated with the PCM array on a different die.

The present disclosure will be described with reference to the accompanying drawings.

Detailed Description

Disclosed herein is a 3D PCM architecture having at least one 3D PCM array with word lines and bit lines on a first die and a word line decoder on a second die, the first die and the second die being hybrid bonded to each other in a face-to-face arrangement. By removing the word line decoder circuitry from the first die and implementing the word line decoder circuitry on the second die, the layout of the 3D PCM array may be rearranged so as to increase the bit density of the array while still providing an electrical connection path between the word lines in the array (on the first die) and the output terminals of the word line decoder circuitry (on the second die). Thus, embodiments in accordance with the present disclosure may use die area made available by eliminating word line decoder circuitry to increase the number of memory cells per unit area in the 3D PCM of the first die, as compared to previous 3D PCM arrays implemented on a single die. According to the present disclosure, the bit density of the 3D PCM of the first die may thereby be increased.

Various illustrative examples and embodiments are presented herein to facilitate an understanding of the structure of a 3D PCM and a method for generating a 3DPCM according to the present disclosure.

This detailed description includes, in part, background information regarding the structure and fabrication of an exemplary 3D phase change memory and an exemplary hybrid bond layer structure. The detailed description section also includes a description and drawings of the structure of the illustrative embodiment including stacked 3DPCM, bond layer arrangements, face-to-face hybrid bonding (wafer-to-wafer or die-to-die) methods, and arrangements of bit line and word line contacts for improved area efficiency and memory cell density. In various embodiments, the word line decoder circuitry is implemented on a different die than the memory array, and structures are provided on each die to interconnect the output terminals of the word line decoder circuitry on one die to the word lines in the memory array on a different die.

In this way, the layout of a PCM based memory array according to the present disclosure may be changed compared to PCM based memory arrays where both the bit line decoder and the word line decoder are present on the same die. By eliminating the need for die area dedicated to implementing word line decoders, memory array efficiency may be improved. Also, in some embodiments, interconnect routing congestion may be reduced because address lines that are typically input to a word line decoder do not need to be routed in the memory array portion of the die. Therefore, the interconnect wiring can be simplified.

Although specific constructions and arrangements are discussed, it should be understood that this is done for illustrative purposes only. One skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in a variety of other applications.

It is worthy to note that any reference in the specification to "one embodiment," "an example embodiment," and "some embodiments," etc., means that a particular feature, structure, or characteristic may be included in the described embodiments, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the relevant art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

Generally, terms may be understood, at least in part, from the use of context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, depending at least in part on the context. Similarly, terms such as "a" or "an" may be equally understood as conveying a singular usage or a plural usage, depending at least in part on the context. In addition, also depending at least in part on the context, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors that are not necessarily explicitly described.

It should be readily understood that the meanings of "on", "over" and "over" in this disclosure should be interpreted in the broadest sense so that "on" means not only directly on "something but also includes the meaning of having an intermediate feature or layer therebetween, and" over "or" over "means not only the meaning of" over "or" over "something, but also the meaning of" over "or" over "something and no intermediate feature or layer therebetween (i.e., directly on something).

Further, spatially relative terms, such as "below," "lower," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. In addition to the orientations depicted in the drawings, spatially relative terms are intended to encompass different orientations of the device in use or process steps. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the term "substrate" refers to a material upon which subsequent layers of material are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a wide variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

As used herein, the term "layer" refers to a portion of material that includes regions having a thickness. The layer may extend over the entire underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. Furthermore, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure, or between any pair of horizontal planes at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along tapered surfaces. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, above and/or below. The layers may comprise multiple layers. For example, the interconnect layer may include one or more conductors and contact layers (in which interconnect lines and/or via contacts are formed) and one or more dielectric layers.

As used herein, the term "nominal" refers to desired or target values for a characteristic or parameter of a component or process step, as well as a series of values above and/or below the desired value, set during a design phase of a product or process. The range of values may be due to small variations in manufacturing processes or tolerances. As used herein, the term "about" indicates a given amount of value that may vary based on the particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" may indicate a given amount of a value that varies, for example, within 10-30% of the value (e.g., ±10%, ±20% or ±30% of the value).

As used herein, the term "3D memory device" refers to a semiconductor device having memory cells that may be vertically arranged on a laterally oriented substrate such that the number of memory cells may be amplified in a vertical direction relative to the substrate. As used herein, the term "vertically" refers to a lateral surface that is nominally perpendicular to the substrate.

Description of stacked 3D phase change memory arrays

PCM may use the difference between the resistivity of the amorphous and crystalline phases of a phase change material (e.g., chalcogenide alloy) based at least in part on electrothermal heating and quenching of the phase change material. The phase change material in a PCM cell may be located between two electrodes and a current may be applied to repeatedly switch the material (or at least a portion of the material's blocking current path) between the two phases to store data. PCM cells may be vertically stacked in a 3D fashion to form a 3D PCM.

The 3D PCM may include a 3D cross-point memory array that stores data based on resistance changes in bulk material characteristics (e.g., in a high resistance state or a low resistance state), in combination with a stackable cross-point data access array that will be bit-addressable. For example, fig. 1 shows a perspective view of an exemplary 3D cross-point memory device 100. The 3D PCM cross-point memory device 100 has a transistor-less, cross-point architecture that positions memory cells at the intersection of vertical conductors. The 3D PCM cross-point memory device 100 includes a plurality of parallel lower bit lines 102 in a first common plane and a plurality of parallel upper bit lines 104 in a second common plane above the lower bit lines 102. The 3D PCM cross-point memory device 100 also includes a plurality of parallel word lines 106 in a third common plane that are located vertically between the lower bit lines 102 and the upper bit lines 104. As shown in fig. 1, each lower bit line 102 and each upper bit line 104 extend laterally in a bit line direction (parallel to the wafer plane) in plan view, and each word line 106 extends laterally in a word line direction in plan view. Each word line 106 is perpendicular to each lower bit line 102 and each upper bit line 104.

Note that x, y, and z axes are shown in fig. 1. The x and y axes show two orthogonal directions in the wafer plane. The x-direction is the word line direction and the y-direction is the bit line direction. It should also be noted that the z-axis is also included in fig. 1 and further illustrates the spatial relationship of the components in the 3D PCM cross-point memory device 100. The substrate (not shown) of the 3D PCM intersection memory device 100 comprises two lateral surfaces extending laterally in the x-y plane: a top surface on the front side of the wafer, and a bottom surface on the back side opposite the front side of the wafer. The z-axis is perpendicular to the x-axis and the y-axis. As used herein, when a substrate is located in the lowest plane of a semiconductor device (e.g., 3D PCM cross-point memory device 100) in the z-direction (perpendicular to the x-y plane), whether one component of the semiconductor device (e.g., a layer or device) is "above," "above," or "below" another component (e.g., a layer or device) in the z-direction is determined relative to the substrate of the semiconductor device. The same concepts used to describe spatial relationships are applied throughout this disclosure.

As shown in fig. 1, the 3D PCM cross-point memory device 100 includes a plurality of memory cells 108, each memory cell 108 being disposed at an intersection of a lower or upper bit line 102 or 104 and a corresponding word line 106. Each memory cell 108 includes at least a PCM element 110 and a selector 112 stacked vertically. Each memory cell 108 stores a single bit of data and can be written to or read from by varying the voltage applied to the corresponding selector 112, replacing the need for transistors. Each memory cell 108 is individually accessed by a current applied through the top and bottom conductors (e.g., the corresponding word line 106 and the lower or upper bit line 102 or 104) that are in contact with each memory cell 108. The memory cells 108 in the 3D PCM cross-point memory device 100 are arranged in a memory array.

In the existing 3D PCM cross-point memory, bit line contacts for upper and lower bit lines are arranged at both sides outside the memory array in plan view. Since the 3D PCM cross-point memory consists of a plurality of memory arrays surrounded by bit line contacts, the bit line contact area occupies a large part of the device area, which reduces array efficiency. For example, fig. 2A is a block diagram of an exemplary 3D PCM intersection point storage device 200, fig. 2B is a plan view of the exemplary 3D PCM intersection point storage device 200 in fig. 2A, and fig. 2C shows a perspective view of the exemplary 3D PCM intersection point storage device 200 of fig. 2A.

As shown in fig. 2A, the 3D PCM cross-point memory device 200 includes two memory arrays a and B202, each of which includes an array of 3D PCM cross-point memory cells. For each memory array 202, bit line contacts are provided in two bit line contact areas (BL CT) 204 surrounding the memory array 202 and outside the memory array 202. That is, the two bit line contact regions 204 are arranged on both sides of the corresponding memory array 202 in the bit line direction (y-direction), but do not overlap the memory array 202 in a plan view. As a result, dedicated bit line contact regions 204 occupy a significant portion of the device area in the bit line direction, thereby reducing array efficiency and complicating the interconnect routing scheme. The 3D PCM cross-point memory device 200 also includes word line contacts located in a word line contact region (WL CT) 206 in the middle of the respective memory array 202 in the word line direction (x-direction).

Referring to FIG. 2B, each bit line 208 (either a lower bit line or an upper bit line) extends beyond the memory array 202 in the bit line direction and out of the memory array 202. At one or both ends of each bit line 208 outside of the memory array 202, a bit line extension 210 having a critical dimension greater than the critical dimension of the bit line 208 is formed to place a bit line contact 212 having a relaxed critical dimension compared to the bit line 208. That is, the critical dimension of bit line contact 212 is greater than the critical dimension of bit line 208, which further increases the size of bit line contact region 204 and reduces array efficiency. For example, as shown in FIG. 2C, as each bit line 208 extends laterally beyond the memory array 202 in either bit line direction, its critical dimension increases to form a corresponding bit line extension 210. A bit line contact 212 having a relaxed critical dimension (e.g., greater than the critical dimension of bit line 208) is disposed below and in contact with each bit line extension 210, i.e., extending downward in the same vertical direction.

Various embodiments in accordance with the present disclosure provide improved interconnection schemes for 3D PCM storage devices (e.g., 3D PCM cross-point storage devices) and methods of manufacturing the same. Bit line contacts may be formed within the memory array region, which eliminates the need for dedicated bit line contact regions outside of the memory array region, thereby improving memory array efficiency and simplifying interconnect routing. In some embodiments, the bit line contacts are inclusively disposed between the memory cells in plan view, i.e., overlapping the memory array. In some embodiments, the critical dimension of the bit line contact is not greater than the critical dimension of the corresponding bit line. That is, the critical dimension of the bit line contacts is no longer relaxed compared to the critical dimension of the bit lines, and the size of the bit line contacts can be reduced, further saving contact area. In order to form bit line contacts with non-relaxed critical dimensions, in situ polymer deposition and etching schemes may be used.

Fig. 3A shows a block diagram of an exemplary 3D PCM storage device 300. The 3D PCM storage device 300, such as a 3D PCM cross point storage device, may include a plurality of storage arrays a and B302, each array of storage arrays 3D PCM cells being disposed in a storage array area. The 3d PCM storage device 300 may also include, for each storage array 302, bit line contacts disposed in two bit line contact regions (BL CTs) 304, the two bit line contact regions (BL CTs) 304 being located at both ends of the storage array region in the bit line direction (i.e., the y-direction). Unlike the 3D PCM cross-point memory device 200 of fig. 2A, in which the bit line contacts are located outside of the memory array region, at least some of the bit line contacts in the 3D PCM memory device 300 are disposed within the memory array region. As shown in fig. 3A, each bit line contact region 304 completely overlaps a corresponding memory array 302. That is, each bit line contact in bit line contact region 304 is disposed within the memory array region. For each memory array 302, the 3d PCM storage device 300 may also include a word line contact region (WL CT) 306 located in the middle of the memory array region in the word line direction (i.e., x-direction). Word line contacts of the 3D PCM storage device 300 may be provided in the word line contact region 306. In some embodiments, each word line contact is disposed within a memory array region. By disposing both the word line contact region 306 and the bit line contact region 304 within the memory array region of the corresponding memory array 302, the contact area can be reduced and the memory array efficiency can be improved.

Fig. 3B is a plan view of the exemplary 3D PCM storage device 300 of fig. 3A. As shown in fig. 3B, the 3D PCM storage device 300 may also include a plurality of bit lines 308. Each bit line 308 extends across the memory array area of the memory array 302 in the bit line direction (y-direction). Unlike bit lines 208 in 3D PCM cross-point memory device 200 that extend beyond memory array 302 and beyond memory array 302, bit lines 308 in 3D PCM memory device 300 are disposed within the memory array area of memory array 302. Unlike 3D PCM cross-point memory device 200, which includes bit line extensions 210 having relaxed critical dimensions on which bit line contacts 212 are formed, 3D PCM memory device 300 includes bit line contacts 310 that are in direct contact with corresponding bit lines 308. Each bit line contact 310 may be disposed in a bit line contact region 304 within a memory array region of the memory array 302. In some embodiments, the critical dimension of each bit line contact 310 is no greater than the critical dimension of each bit line 308. That is, the critical dimensions of bit line contact 310 are no longer relaxed compared to bit line 308 in accordance with the present disclosure. Accordingly, the bit line contact size may be reduced to further save contact area. It will be appreciated that while each bit line 308 is in contact with two bit line contacts 310 in two bit line contact regions 304, respectively, as shown in fig. 3B, in some other embodiments one or more bit lines 308 may be in contact with only one bit line contact 310 in either of the two bit line contact regions 304.

Fig. 3C is a perspective view of the exemplary 3D PCM storage device 300 of fig. 3A. As shown in fig. 3C, the 3D PCM storage device 300 may also include a plurality of word lines 312. Each word line 312 extends across the memory array area of the memory array 302 in the word line direction (x-direction). That is, the word lines 312 and bit lines 308 of the 3D PCM storage device 300, such as a 3D PCM cross-point storage device, may be vertically arranged conductors in a cross-point structure.

In some embodiments, 3D PCM storage device 300 includes a lower bit line 308A and an upper bit line 308B that are parallel to each other. For example, each of the lower bit lines 308A and the upper bit lines 308B may extend laterally across the memory array 302 in the bit line direction (y-direction). The lower bit line 308A and the upper bit line 308B have the same critical dimension, e.g., the same width in the x-direction. In one example, the critical dimensions of the lower bit lines 308A and the upper bit lines 308B may be about 20nm, and the spacing of the lower bit lines 308A and the upper bit lines 308B may be about 40nm. The 3D PCM storage device 300 also includes parallel word lines 312 that lie in the same plane between the lower bit lines 308A and the upper bit lines 308B in the z-direction. Each word line 312 is perpendicular to the lower bit line 308A and the upper bit line 308B. In one example, the critical dimension (e.g., width in the y-direction) of the word lines 312 may be about 20nm, and the pitch of the word lines 312 is about 40nm. The lower bit line 308A, the upper bit line 308B, and the word line 312 may comprise a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each of the lower bit line 308A, the upper bit line 308B, and the word line 312 comprises a metal, such as tungsten.

The 3D PCM memory device 300 includes a plurality of lower memory cells 314A, each disposed at an intersection of a corresponding one of the lower bit lines 308A and the word lines 312, and a plurality of upper memory cells 314B, each disposed at an intersection of a corresponding one of the upper bit lines 308B and the word lines 312. Each memory cell 314A or 314B may be individually accessed by a current applied through the respective word line 312 and bit line 308A or 308B in contact with the memory cell 314A or 314B. Each of the lower memory cell 314A and the upper memory cell 314B may include a stacked PCM element 322, a selector 318, and a plurality of electrodes 316, 320, and 324.PCM element 322 may take advantage of the difference between the resistivity of the amorphous and crystalline phases in the phase change material based on electrothermal heating and quenching of the phase change material. A current may be applied to repeatedly switch the phase change material (or at least a portion of the phase change material that blocks the current path) of the PCM element 322 between the two phases to store data. A single bit of data may be stored in each memory cell 314A or 314B and may be written to or read by varying the voltage applied to the corresponding selector 318, eliminating the need for transistors. In some embodiments, three electrodes 316, 320, and 324 are disposed below selector 318, between selector 318 and PCM element 322, and above PCM element 322, respectively. It should be appreciated that the relative positions of the selector 318 and the PCM element 322 may be switched in other embodiments.

The selector 318 and PCM element 322 may be a dual stack memory/selector structure. The material of PCM element 322 includes a chalcogenide-based alloy (chalcogenide glass), such as a GST (Ge-Sb-Te) alloy, or any other suitable phase change material. The material of the selector 318 may include any suitable Ovonic Threshold Switch (OTS) material, such as Zn_xTe_y、Ge_xTe_y、Nb_xO_y、Si_xAs_yTe_z or the like. It is to be understood that the structure, construction, and materials of the memory array 302 are not limited to the example in fig. 3C, and may include any suitable structure, construction, and materials. Electrodes 316, 320, and 324 may comprise a conductive material including, but not limited to W, co, cu, al, carbon, polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each of the electrodes 316, 320, and 324 includes carbon, such as amorphous carbon.

As shown in fig. 3C, 3D PCM storage 300 may also include a lower bitline contact 310A below lower bitline 308A and in contact with lower bitline 308A, and an upper bitline contact 310B above upper bitline 308B and in contact with upper bitline 308B. The lower bit line contact 310A extends downward and the upper bit line contact 310B extends upward. That is, the lower bit line contact 310A and the upper bit line contact 310B may extend vertically in opposite directions. The lower bit line contact 310A and the upper bit line contact 310B may comprise a conductive material including, but not limited to W, co, cu, al, polysilicon, doped silicon, silicide, or any combination thereof. Each of the lower bit line contact 310A and the upper bit line contact 310B comprises a metal, such as tungsten. Thus, lower bit line contact 310A and upper bit line contact 310B are electrically connected to lower bit line 308A and upper bit line 308B, respectively, for individually addressing a corresponding lower memory cell 314A or upper memory cell 314B.

As described above, the bit line contacts 310A and 310B may have non-relaxed critical dimensions, i.e., reduced contact dimensions, to further efficiently use chip space. In some embodiments, a critical dimension (e.g., diameter) of at least one of the lower bit line contact 310A and the upper bit line contact 310B is not greater than a critical dimension (e.g., width in the x-direction) of the corresponding lower bit line 308A or upper bit line 308B. In one example, the critical dimension of at least one of the lower bit line contact 310A and the upper bit line contact 310B may be the same as the critical dimension of the corresponding lower bit line 308A or upper bit line 308B. In another example, the critical dimension of at least one of the lower bit line contact 310A and the upper bit line contact 310B may be less than the critical dimension of the corresponding lower bit line 308A or upper bit line 308B. In some embodiments, the critical dimension of at least one of the lower bit line contact 310A and the upper bit line contact 310B is no greater than about 60nm, such as no greater than 60nm. In some embodiments, the critical dimension of at least one of the lower bit line contact 310A and the upper bit line contact 310B is between about 10nm and about 30nm, such as between 10nm and 30nm (e.g., ,10nm、11nm、12nm、13nm、14nm、15nm、16nm、17nm、18nm、19nm、20nm、21nm、22nm、23nm、24nm、25nm、26nm、27nm、28nm、29nm、30nm, is any range defined by any of these values as the lower end, or is any range defined by any two of these values). In some embodiments, the critical dimension of each of the lower bit line contact 310A and the upper bit line contact 310B is not greater than the critical dimension of each of the lower bit line 308A and the upper bit line contact 308B. In some embodiments, the critical dimensions of bit lines 308A and 308B and bit line contacts 310A and 310B are about 20nm, for example 20nm.

In some embodiments, at least one of the lower bit line contacts 310A and the upper bit line contacts 310B has the same pitch as the corresponding lower bit line 308A or upper bit line 308B. In some embodiments, the pitch is no greater than about 80nm, such as no greater than 80nm. In some embodiments, the pitch is between about 20nm and about 60nm, such as between 20nm and 60nm (e.g., ,20nm、22nm、24nm、26nm、28nm、30nm、32nm、34nm、36nm、38nm、40nm、42nm、44nm、46nm、48nm、50nm、52nm、54nm、56nm、58nm、60nm, any range defined by any one of these values as the lower end, or any range defined by any two of these values). In some embodiments, the pitch of each of the lower bit line contacts 310A and the upper bit line contacts 310B is no greater than the pitch of each of the lower bit line 308A and the upper bit line 308B. In some embodiments, the pitch of bit lines 308A and 308B and the pitch of bit line contacts 310A and 310B is approximately 40nm, such as 40nm. By having bit line contacts 310A and 310B with non-relaxed critical dimensions and spacing, bit line contacts 310A and 310B may be in direct contact with bit lines 308A and 308B, rather than in contact with bit line extensions (e.g., 210 as shown in fig. 2C).

In plan view (parallel to the wafer plane), at least one of the lower bit line contact 310A and the upper bit line contact 310B is inclusively disposed between the lower and upper memory cells 314A and 314B of the memory array 302. As used herein, a bit line contact 310A or 310B is "inclusively" disposed between memory cells 314A and 314B of memory array 302 (i) when the bit line contact 310A or 310B overlaps at least one of the memory cells 314A and 314B in plan view, or (ii) when the bit line contact 310A or 310B is disposed between the memory cells 314A and 314B in plan view. As shown in fig. 3C, since memory cells 314A and 314B are disposed at intersections of word lines 312 and bit lines 308A and 308B and each bit line contact 310A or 310B is in contact with a respective bit line 308A or 308B, the outermost memory cells 314A and 314B of memory array 302 define a range (between boundaries "a" and "B") in the bit line direction (y-direction) in which lower bit line contact 310A and/or upper bit line contact 310B may be disposed. In the example of fig. 3C, both the lower bit line contact 310A and the upper bit line contact 310B overlap the outermost memory cells 314A and 314B, respectively. That is, each bit line contact 310A or 310B is disposed within a memory array region of the memory array 302. It should be appreciated that lower bit line contact 310A and/or upper bit line contact 310B may be disposed in any position (e.g., anywhere between boundaries "a" and "B" in FIG. 3C) that is located between memory cells 314A and 314B, inclusive, in plan view. In some embodiments, at least one of the lower bit line contact 310A and the upper bit line contact 310B is disposed between the lower memory cell 314A and the upper memory cell 314B of the memory array 302 in plan view, i.e., does not overlap with the memory cell 314A or 314B in plan view.

Although in fig. 3C, each of the lower and upper bit line contacts 310A, 310B are inclusively disposed between the lower and upper memory cells 314A, 314B of the memory array 302 in plan view, it should be appreciated that in some other embodiments one of the lower and upper bit line contacts may be disposed outside of the memory array in plan view. In other words, the lower bit line contact or the upper bit line contact is disposed between the lower memory cell and the upper memory cell in a plan view in an inclusive manner. For example, fig. 4A shows a perspective view of another exemplary 3D PCM storage device 400, and fig. 4B shows a perspective view of yet another exemplary 3D PCM storage device 401. The 3D PCM memory device 400 is similar to the 3DPCM memory device 300 in fig. 3C except for the upper bit line and upper bit line contacts.

As shown in fig. 4A, according to some embodiments, an upper bit line 402B extends laterally beyond the memory array 302 in the bit line direction (y-direction), and an upper bit line contact 404B in contact with the upper bit line 402B is disposed between the lower memory cell 314A and the upper memory cell 314B of the memory array 302 in plan view, without inclusion. That is, according to some embodiments, lower bitline contact 310A is disposed within a memory array region of memory array 302, while upper bitline contact 404B is disposed outside the memory array region of memory array 302. In some embodiments, lower bit line contact 310A and upper bit line contact 404B extend in the same direction, e.g., downward as shown in fig. 4A, such that bit line contacts 310A and 404B may be pad led out from the same side of 3D PCM storage device 400. While in fig. 4A the upper bit line 402B extends beyond the memory array 302, it is to be understood that the critical dimension of the upper bit line 402B may not increase, i.e., no upper bit line extension is formed, and the critical dimension (e.g., diameter) of the upper bit line contact 404B may not be greater than the critical dimension (e.g., width in the x-direction) of the upper bit line 402B, as described in detail above.

Referring to fig. 4b,3D PCM storage device 401 is similar to 3D PCM storage device 300 except for lower bit lines and lower bit line contacts. The structure, function, and materials of the same components described above with respect to the 3D PCM storage device 300 are not repeated for convenience of description. As shown in fig. 4B, the lower bit line 406A extends laterally beyond the memory array 302 in the bit line direction (y-direction), and a lower bit line contact 408A in contact with the lower bit line 406A is disposed between the lower memory cell 314A and the upper memory cell 314B of the memory array 302 in plan view, not inclusive. That is, according to some embodiments, upper bitline contact 310B is disposed within a memory array region of memory array 302, while lower bitline contact 408A is disposed outside the memory array region of memory array 302. In some embodiments, the lower bit line contact 408A and the upper bit line contact 310B extend in the same direction, e.g., upward as shown in fig. 4B, such that the bit line contacts 408A and 310B may be pad led out from the same side of the 3D PCM storage device 400. Although in fig. 4B the lower bit line 406A extends beyond the memory array 302, it is to be understood that the critical dimension of the lower bit line 406A may not increase, i.e., no lower bit line extension is formed, and the critical dimension (e.g., diameter) of the lower bit line contact 408A may not be greater than the critical dimension (e.g., width in the x-direction) of the lower bit line 406A, as described in detail above.

Fig. 5A-5L illustrate an exemplary manufacturing process for forming a 3D PCM storage device according to the present disclosure. Fig. 6 is a flowchart of an exemplary method 600 for forming a 3D PCM storage device according to the present disclosure. Examples of the 3D PCM storage device depicted in fig. 5A-5L and fig. 6 include a 3D PCM storage device 400 (see fig. 4A). Fig. 5A to 5L and fig. 6 will be described together. The operations of method 600 are not exhaustive and other operations may be performed before, after, or between any of the illustrated operations. Further, some operations may be performed simultaneously or in a different order than shown in fig. 6.

Referring to fig. 6, method 600 begins with operation 602 in which a lower bit line contact and a lower bit line in contact with the lower bit line contact are formed. Forming the lower bitline contact may include in situ polymer deposition and etching such that the critical dimension of the lower bitline contact is not greater than the critical dimension of the lower bitline. In some embodiments, to form the lower bit line, a conductor layer is deposited, the conductor layer is double patterned, and the double patterned conductor layer is etched. The conductor layer may comprise tungsten. In some embodiments, the critical dimension of the lower bitline contact is no greater than the critical dimension of the lower bitline. For example, the critical dimension is not greater than about 60nm, such as between about 10nm and about 30 nm. The lower bit line contacts may have the same pitch as the lower bit lines. For example, the pitch is no greater than about 80nm.

Referring to fig. 5A, a plurality of lower bit line contacts 504 are formed through a dielectric layer 502. To form the lower bitline contacts 504, the dielectric layer 502 with a dielectric material such as silicon oxide may first be formed by one or more thin film deposition processes including, but not limited to, chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof. Contact holes (not shown) with non-relaxed critical dimensions and spacing for the lower bitline contacts 504 as described in detail above may be etched through the dielectric layer 502, which may be deposited and etched using in situ polymers to control the size of the contact holes. For example, the plasma etch process may be modified such that polymer deposition (e.g., accumulation of a fluorocarbon polymer layer) occurs during the plasma etch to control the etch rate (also referred to as "polymerization"). A plasma etch may then be performed in the same plasma etcher to etch back and eventually remove the polymer layer. The in-situ polymer deposition and etching may further reduce the critical dimensions of the lower bit line contacts 504 after patterning in order to achieve reduced contact dimensions that may not be readily achievable by photolithography. For example, the critical dimension of the contact hole of the lower bitline contact 504 may be between about 50nm and about 60nm after photolithography and may be further reduced to about 20nm and about 30nm after in situ polymer deposition and etching. After forming the contact holes, the lower bit line contacts 504 may be formed by depositing one or more conductive materials (e.g., tungsten) to fill the contact holes using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD or any combination thereof. The lower bit line contacts 504 may be further planarized by Chemical Mechanical Polishing (CMP) and/or etching such that the upper ends (top surfaces) of the lower bit line contacts 504 are flush with the top surface of the dielectric layer 502.

Referring to fig. 5A, a conductor layer 508 is formed on the dielectric layer 502 and in contact with the lower bit line contact 504. A metal layer such as a tungsten layer may be deposited using one or more thin film deposition processes including, but not limited to CVD, PVD, ALD or any combination thereof. As described in detail below with respect to fig. 5B, the conductor layer 508 is then double patterned, and the double patterned conductor layer 508 is etched to form lower bit lines 536 over the lower bit line contacts 504, respectively, in contact with the lower bit line contacts 504.

The method 600 proceeds to operation 604, as shown in fig. 6, where a plurality of lower memory cells are formed over and in contact with the lower bit line. Each lower memory cell may include a stacked PCM element, a selector, and a plurality of electrodes. In some embodiments, the lower bit line contacts are inclusively disposed between the lower memory cells in plan view. To form the plurality of lower memory cells, layers of the first conductor, OTS material, the second conductor, chalcogenide-based alloy, and the third conductor are then deposited to form a memory stack, and the memory stack is then etched in two perpendicular directions. Each of the first, second and third conductors may include amorphous carbon. In some embodiments, to subsequently etch the storage stack, the storage stack is double patterned in a first of two perpendicular directions, the double patterned storage stack is etched in the first direction to form a first gap, the first gap is filled with a dielectric material, the etched storage stack is double patterned in a second of the two perpendicular directions, the double patterned, etched storage stack is etched in the second direction to form a second gap, and the second gap is filled with a dielectric material.

Still referring to fig. 5A, a lower storage stack 506 is formed on conductor layer 508. In some embodiments, to form the lower storage stack 506, the first conductor layer 510, the OTS material layer 512, the second conductor layer 514, the chalcogenide-based alloy layer 516, and the third conductor layer 518 are then deposited using one or more thin film deposition processes including, but not limited to CVD, PVD, ALD, electroplating, electroless plating, any other suitable deposition process, or any combination thereof. For example, each of the first, second, and third conductor layers 510, 514, and 518 may include amorphous carbon, the OTS material layer 512 may include Zn_xTe_y、Ge_xTe_y、Nb_xO_y、Si_xAs_yTe_z, etc., and the chalcogenide-based alloy layer 516 may include a GST alloy. It should be appreciated that in some embodiments, the order in which the OTS material layer 512 and chalcogenide-based alloy layer 516 are deposited may be switched. In some embodiments, dielectric layer 520 is formed on lower storage stack 506 by depositing a dielectric material such as silicon nitride using one or more thin film deposition processes including, but not limited to CVD, PVD, ALD or any combination thereof.

Referring to fig. 5B, the lower memory stack 506 and the conductor layer 508 thereunder and the dielectric layer 520 thereabove are etched in the bit line direction (y-direction) (see fig. 5A). The lower storage stack 506, the conductor layer 508, and the dielectric layer 520 may be double-patterned first in the bit line direction. An etch mask (not shown) is patterned on dielectric layer 520, for example, by photolithography, development, and etching. The etch mask may be a photoresist mask or a hard mask patterned based on a photolithographic mask. The double patterning may include, but is not limited to, photo-etch-photo-etch (le) pitch splitting or self-aligned double patterning (SADP) to control the critical dimensions of the lower bit lines 536 and lower memory cells 538 to be formed (see fig. 5G). In some embodiments, the double-patterned lower storage stack 506, conductor layer 508, and dielectric layer 520 are etched in the bit line direction to form parallel first gaps 522 in the bit line direction. The etch mask, which may be double patterned, may be used to etch through the lower storage stack 506, the conductor layer 508, and the dielectric layer 520 by one or more wet and/or dry etching processes, such as Deep Reactive Ion Etching (DRIE), to simultaneously form parallel first gaps 522. Thereby forming parallel lower bit lines 536 extending in the bit line direction that are above the lower bit line contacts 504 and in contact with the lower bit line contacts 504. Thereby also forming etched memory stacks 524 separated by first gaps 522.

Referring to fig. 5C, the first gap 522 is filled with a dielectric material 526, such as, but not limited to, silicon oxide. In some embodiments, dielectric material 526 is deposited into first gap 522 using one or more thin film deposition processes including, but not limited to CVD, PVD, ALD, electroplating, electroless plating, any other suitable deposition process, or any combination thereof, followed by a planarization process, such as CMP and/or etching. For example, ALD may be used to deposit silicon oxide into the first gap 522, followed by CMP to fill the first gap 522.

Referring to fig. 5D, a plurality of word line contacts 528 are formed on dielectric layer 502. The word line contacts 528 may be formed by first patterning, followed by in situ polymer deposition and etching, and one or more thin film deposition processes such as CVD, PVD, or ALD. The upper ends (top surfaces) of the word line contacts 528 may be planarized using CMP to be flush with the top surfaces of the etched memory stacks 524. During the planarization process, a top portion of dielectric material 526 and dielectric layer 520 (see fig. 5C) are removed to expose a top surface of third conductor layer 518 of etched memory stack 524.

The method 600 proceeds to operation 606, where a plurality of parallel word lines in a same plane are formed over and in contact with a lower memory cell. Each word line may be perpendicular to the lower bit line. To form a word line, a conductor layer is deposited, double patterned, and etched.

Referring to fig. 5E, a conductor layer 530 is formed over the etched memory stack 524 and dielectric material 526 and in contact with the upper ends of the word line contacts 528. A metal layer such as a tungsten layer may be deposited using one or more thin film deposition processes including, but not limited to CVD, PVD, ALD or any combination thereof.

Referring to fig. 5F, the conductor layer 530 is then double patterned in the word line direction (x-direction) to form an etch mask 532 extending in the word line direction. The etch mask 532 may be patterned on the conductor layer 530 by photolithography, development, and etching. The etch mask 532 may be a photoresist mask or a hard mask patterned based on a photolithographic mask. The double patterning may include, but is not limited to, le pitch splitting or SADP to control the critical dimensions of the lower word line 534 and lower memory cell 538 (see fig. 5G) to be formed. The double patterning process in fig. 5F is performed in a word line direction perpendicular to the bit line direction in which the double patterning process in fig. 5B is performed.

Referring to fig. 5G, the conductor layer 530 (see fig. 5F) and the etched memory stack 524 thereunder are etched in the word line direction (x-direction) to form a second gap 537 in the word line direction. Etching stops at the lower bit line 536 such that the lower bit line 536 remains intact. The parallel second gaps 537 may be formed simultaneously by one or more wet and/or dry etching processes (e.g., DRIE) using an etch mask 532 to etch through the conductor layer 530 and the etched memory stack 524. According to some embodiments, parallel lower word lines 534 extending in the word line direction are thereby formed to overlie word line contacts 528 and contact word line contacts 528. Lower memory cell 538 is thus also formed at the intersection of lower bit line 536 and lower word line 534, respectively. Each lower memory cell 538 may include a first conductor layer 510 (as a first electrode), an OTS material layer 512 (as a selector), a second conductor layer 514 (as a second electrode), a chalcogenide-based alloy layer 516 (as a PCM element), and a third conductor layer 518 (as a third electrode). Lower memory cell 538 is above and in contact with lower bitline 536. The lower memory cells 538 may be patterned (e.g., by the double patterning process in fig. 5F) such that each lower bitline contact 504 is inclusively disposed between the lower memory cells 538 in plan view.

Although not shown, the second gap 537 may be filled with a dielectric material, such as silicon oxide. In some embodiments, dielectric material is deposited into second gap 537 using one or more thin film deposition processes including, but not limited to CVD, PVD, ALD, electroplating, electroless plating, any other suitable deposition process, or any combination thereof, followed by a planarization process, such as CMP and/or etching. For example, silicon oxide may be deposited into the second gap 537 using ALD, followed by CMP to fill the second gap 537.

The method 600 proceeds to operation 608, where a plurality of upper memory cells are formed over and in contact with the word line. Each upper memory cell may include a stacked PCM element, a selector, and a plurality of electrodes. Each upper memory cell may be in contact with a corresponding one of the word lines. To form the plurality of upper memory cells, layers of the first conductor, OTS material, the second conductor, chalcogenide-based alloy, and the third conductor are then deposited to form a memory stack, and the memory stack is then etched in two perpendicular directions. Each of the first, second and third conductors may include amorphous carbon. In some embodiments, to subsequently etch the storage stack, the storage stack is double patterned in a first of two perpendicular directions, the double patterned storage stack is etched in the first direction to form a first gap, the first gap is filled with a dielectric material, the etched storage stack is double patterned in a second of the two perpendicular directions, the double patterned, etched storage stack is etched in the second direction to form a second gap, and the second gap is filled with a dielectric material.

Referring to fig. 5H, a conductor layer 542 is formed on the lower word line 534, and an upper memory stack 540 is formed on the conductor layer 542. In some embodiments, to form upper storage stack 540, first conductor layer 544, OTS material layer 546, second conductor layer 548, chalcogenide-based alloy layer 550, and third conductor layer 552 are then deposited using one or more thin film deposition processes including, but not limited to CVD, PVD, ALD, electroplating, electroless plating, any other suitable deposition process, or any combination thereof. For example, each of the first, second, and third conductor layers 544, 548, and 552 may include amorphous carbon, the OTS material layer 546 may include Zn_xTe_y、Ge_xTe_y、Nb_xO_y、Si_xAs_yTe_z, etc., and the chalcogenide-based alloy layer 550 may include a GST alloy. It should be appreciated that in some embodiments, the order in which the OTS material layer 546 and the chalcogenide-based alloy layer 550 are deposited may be switched. Dielectric layer 554 is formed on upper storage stack 540 by depositing a dielectric material, such as silicon nitride, using one or more thin film deposition processes including, but not limited to CVD, PVD, ALD or any combination thereof.

Referring to fig. 5I, the upper storage stack 540 and the conductor layer 542 below it (see fig. 5H) and the dielectric layer 554 above it are etched in the word line direction (x-direction). The upper storage stack 540, conductor layer 542, and dielectric layer 554 may be double patterned first in the word line direction. An etch mask (not shown) is patterned on dielectric layer 554, for example, by photolithography, development, and etching. The etch mask may be a photoresist mask or a hard mask patterned based on a photolithographic mask. The double patterning may include, but is not limited to, le pitch splitting or SADP to control the critical dimensions of the upper word line 534 and the upper memory cell 562 (see fig. 5L) to be formed. In some embodiments, the double-patterned upper storage stack 540, conductor layer 542, and dielectric layer 554 are etched in the word line direction to form parallel first gaps 556 in the word line direction. The upper storage stack 540, conductor layer 542 and dielectric layer 554 may be etched through using a double patterned etch mask by one or more wet and/or dry etching processes (e.g., DRIE) to simultaneously form parallel first gaps 556. According to some embodiments, parallel upper word lines 543 extending along the word line direction are thereby formed above lower word lines 534 and in contact with lower word lines 534. Etched memory stacks 541 separated by first gaps 556 are also thereby formed. It will be appreciated that in some embodiments, the conductor layer 542 and resulting upper word line 543 may be omitted such that the word line includes only the lower word line 534 and not the upper word line 543.

Although not shown, the first gap 556 may be filled with a dielectric material, such as silicon oxide. In some embodiments, dielectric material is deposited into first gap 556 using one or more thin film deposition processes including, but not limited to CVD, PVD, ALD, electroplating, electroless plating, any other suitable deposition process, or any combination thereof, followed by a planarization process, such as CMP and/or etching. For example, ALD may be used to deposit silicon oxide into first gap 556 followed by CMP to fill first gap 556.

In some embodiments, the upper bit line contacts are formed prior to forming the upper memory cells. Forming the upper bitline contact may include in situ polymer deposition and etching such that the critical dimension of the upper bitline contact is no greater than the critical dimension of the upper bitline. For example, the critical dimension is not greater than about 60nm, such as between about 10nm and about 30 nm. In some embodiments, the upper bit line contacts have the same pitch as the upper bit lines. For example, the pitch is no greater than about 80nm.

Referring to fig. 5J, a plurality of upper bitline contacts 558 are formed. In some embodiments, the upper bit line contacts 558 are first formed by patterning, followed by in situ polymer deposition and etching. Contact holes (not shown) with non-relaxed critical dimensions and spacing of upper bit line contacts 558 as described in detail above may be etched using in situ polymer deposition and etching to control the size of the contact holes. For example, the plasma etch process may be modified such that polymer deposition (e.g., accumulation of fluorocarbon polymer layers) occurs during plasma etching to control the etch rate (also referred to as "polymerization"). A plasma etch may then be performed in the same plasma etcher to etch back and eventually remove the polymer layer. The in situ polymer deposition and etching may further reduce the critical dimension of the upper bit line contacts 558 after patterning in order to achieve a reduced contact size that may not be readily achievable by photolithography. After contact hole formation, upper bit line contacts 558 may be formed by depositing one or more conductive materials (e.g., tungsten) to fill the contact holes using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The upper ends (top surfaces) of the upper bit line contacts 558 may be planarized using CMP to be flush with the top surface of the etched memory stack 541. During the planarization process, top portions of dielectric layer 554 (shown in fig. 5I) and dielectric material (not shown) filling first gap 556 are removed to expose a top surface of third conductor layer 552.

The method 600 proceeds to operation 610, as shown in fig. 6, where an upper bit line is formed over and in contact with an upper memory cell. The upper bit line may be perpendicular to each word line. In some embodiments, to form the upper bit line, a conductor layer is deposited, the conductor layer is double patterned, and the double patterned conductor layer is etched.

Referring to fig. 5K, a conductor layer 564 is formed over the etched memory stack 541 and a dielectric material (not shown) filling the first gap 556 (see fig. 5J). According to some embodiments, conductor layer 564 is over and in contact with upper bit line contact 558 and etched memory stack 541 (see fig. 5J). In some embodiments, a metal layer, such as a tungsten layer, is deposited using one or more thin film deposition processes including, but not limited to CVD, PVD, ALD or any combination thereof.

The conductor layer 564 is then double patterned in the bit line direction (y-direction) to form an etch mask 568 extending along the bit line direction. Etch mask 568 may be patterned over conductor layer 564 by photolithography, development, and etching. The etch mask 568 may be a photoresist mask or a hard mask patterned based on a photolithographic mask. The double patterning may include, but is not limited to, le pitch splitting or SADP to control the critical dimensions of the upper bit lines 560 and upper memory cells 562 (see fig. 5L) to be formed. The double patterning process in fig. 5K is performed in the bit line direction.

Referring to fig. 5L, the conductor layer 564 (see fig. 5K) and the etched memory stack 541 thereunder are etched in the bit line direction (y-direction) to form a second gap 570 in the bit line direction. According to some embodiments, etching stops at upper word line 543 such that upper word line 543 remains intact. The conductor layer 564 and the etched memory stack 541 may be etched by one or more wet and/or dry etching processes (e.g., DRIE) using an etch mask 568 (see fig. 5K) to simultaneously form parallel second gaps 570. According to some embodiments, parallel upper bit lines 560 extending in the bit line direction are thereby formed over and in contact with upper bit line contacts 558. Thereby also forming upper memory cells 562 at the intersections of upper bit lines 560 and upper word lines 543, respectively. Each upper memory cell 562 can include a first conductor layer 544 (as a first electrode), an OTS material layer 546 (as a selector), a second conductor layer 548 (as a second electrode), a chalcogenide-based alloy layer 550 (as a PCM element), and a third conductor layer 552 (as a third electrode). According to some embodiments, upper bit line 560 is also over and in contact with upper memory cell 562. The top surface of each upper memory cell 562 is flush with the top surface (upper end) of the upper bit line contact 558.

Although not shown, the second gap 570 may be filled with a dielectric material, such as silicon oxide. Dielectric material may be deposited into second gap 570 using one or more thin film deposition processes including, but not limited to CVD, PVD, ALD, electroplating, electroless plating, any other suitable deposition process, or any combination thereof, followed by a planarization process, such as CMP and/or etching. For example, silicon oxide may be deposited into the second gap 570 using ALD followed by CMP.

As described above, the upper bit line contacts 558 are formed prior to forming the upper memory cells 562. Accordingly, the upper bit line contacts 558 (see shown in fig. 5L) extending downward are not formed between the upper memory cells 562 in plan view. In some embodiments, the upper bit line contacts may be formed after the upper memory cells 562 are formed such that the upper bit line contacts may be formed between the upper memory cells 562 in plan view. For example, the method 600 may optionally proceed to operation 612, wherein an upper bitline contact is formed above the upper bitline in contact with the upper bitline. In some embodiments, the upper bit line contacts are inclusively disposed between the upper memory cells in plan view. In some embodiments, forming the upper bitline contact includes in situ polymer deposition and etching such that the critical dimension of the upper bitline contact is no greater than the critical dimension of the upper bitline. For example, the critical dimension is not greater than about 60nm, such as between about 10nm and about 30 nm. In some embodiments, the upper bit line contacts have the same pitch as the upper bit lines. For example, the pitch is no greater than about 80nm. The details of forming the upper bitline contacts are substantially similar to those of forming the lower bitline contacts 504 described above with respect to fig. 5A. Once formed, the upper bitline contacts are above and in contact with upper bitline 560 and are also contained in plan view between upper memory cells 562.

Description of Multi-die 3D PCM architecture

Various embodiments of 3D PCM architecture according to the disclosure provide improved bit density through higher array efficiency compared to previous architectures for 3D phase change memories. By fabricating the 3D PCM array on the first die and by fabricating its associated word line decoder circuit on the second die, the area to be occupied by the word line decoder circuit in the case that the word line decoder circuit is fabricated on the first die with the 3D PCM array becomes available to provide additional PCM cells on the first die. In this way, the overall bit density of the first die may be increased. In some implementations, the 3D PCM cell arrays may be moved closer together, i.e., packed more closely, because the word line decoder circuitry has been relocated to another die. In addition to the word line circuitry itself, word line contacts on the first die that begin below the word line are eliminated in accordance with the present disclosure.

A 3D PCM device having an array of PCM cells may be provided on a first die without word line decoder circuitry according to various embodiments of the present disclosure. In other words, the word lines in the 3D array of PCM cells on the first die are configured to receive word line signals from the word line decoder on the second die.

In previous 3D PCM architectures, the word line decoder circuitry is fabricated on the same die as the bit line decoder circuitry and the 3D PCM cell array. Thus, in previous architectures, the die area that may be dedicated to memory cells was occupied by word line decoder circuitry and/or contacts needed to connect word line circuitry disposed on a substrate with word lines in a 3D PCM array.

Fig. 7 is a schematic bar graph illustration of a prior 3D PCM array architecture having bit line decoder circuitry and word line decoder circuitry on the same die as the 3D PCM array and thus occupying area that would otherwise be available for memory cells. Referring to fig. 7, word line 702 is shown as extending horizontally and bit line 704 is shown as extending vertically. PCM cells are provided at each location where a word line 702 crosses a bit line 704. The locations of the various bit line contacts are indicated by black dots on the bit lines. Still referring to the previous 3D PCM array architecture of fig. 7, a word line contact region 706 is shown (within the dashed box). Note that no bit lines are placed in the word line contact region 706, so there is no word line/bit line overlap that can form PCM cells. Therefore, layout efficiency of such previous 3D PCM array architectures is limited.

Fig. 8A is a block diagram illustrating a first die with bit line decoder circuitry, PCM cell array, and hybrid bonding layer, and a second die with word line decoder circuitry and another hybrid bonding layer oriented in a face-to-face arrangement prior to hybrid bonding. Fig. 8A illustrates an intermediate stage of manufacturing an embodiment of a 3D PCM architecture according to the present disclosure.

Still referring to fig. 8A, a first die 802 is provided. The first die 802 includes at least bit line decoder circuitry 806 and a 3D PCM array 808 disposed over the at least bit line decoder circuitry 806. Further, a first hybrid bonding layer 810 is disposed over the 3D PCM array 808, and the first hybrid bonding layer 810 is a top side layer of the first die 802 prior to performing the hybrid bonding operation. The first hybrid bonding layer 810 is a dielectric layer in which a plurality of conductive bonding contacts are disposed. In some embodiments, the bond contact includes at least copper.

Still referring to fig. 8A, a second die 804 is provided and the second die 804 is shown in an inverted orientation such that its top side surface faces the top side surface of the first die 802. The second die 804 includes at least word line decoder circuitry 814 and a second hybrid bond layer 812. The second hybrid bonding layer 812 is a dielectric layer in which a plurality of conductive bonding contacts are disposed. In some embodiments, the bond contact includes at least copper.

Fig. 8B is a block diagram illustrating the first die and the second die of fig. 8A after hybrid bonding to each other. Referring to fig. 8A-8B, a first die 802 and a second die 804 are hybrid bonded to each other to form a multi-die device 816. Hybrid bonding of the first die 802 and the second die 804 brings the first hybrid bonding layer 810 and the second hybrid bonding layer 812 into contact with each other to attach the first die 802 and the second die 804 to each other and form the hybrid bonding layer 820. It should be appreciated that in some embodiments, such hybrid bonding may be achieved by die-to-die hybrid bonding. In other embodiments, such hybrid bonding may be achieved by wafer-to-wafer hybrid bonding. Typically, after wafer-to-wafer hybrid bonding, a separation operation may be performed to separate the hybrid bonded die from the wafer (but not from each other). Such a separation operation may be referred to as singulation.

Still referring to fig. 8B, the hybrid bond not only mechanically attaches the first die 802 and the second die 804 to each other, it also creates a plurality of electrical paths between the first die 802 and the second die 804. These electrical vias are formed because, as a result of the hybrid bonding operation, the electrically conductive first hybrid bonding contact disposed in the first hybrid bonding layer is in physical contact with the electrically conductive second hybrid bonding contact disposed in the second hybrid bonding layer. In this way, electrical signals may pass in either direction between the first die 802 and the second die 804 of the multi-die device 816.

Fig. 9 is a cross-sectional view of an exemplary first die 902 including bit line decoder circuitry, a 3D PCM cell array disposed over the bit line decoder circuitry, and a first hybrid bonding layer disposed on a top side thereof. Essentially, the cross-sectional view is a more detailed version of the first die 802 shown in block diagram form in fig. 8A. In fig. 9, three main portions of the first die 802 are shown, namely the bit line decoder circuitry 806, the 3D PCM array 808 disposed over at least the bit line decoder circuitry 806, and the first hybrid bond layer 810 disposed over the 3D PCM array 808, but they are represented by component illustrations rather than blocks. However, fig. 9 also shows a detail not shown in fig. 8A, namely the first hybrid bond contact. As described above, after hybrid bonding, the first hybrid bond contact is in physical contact with the second hybrid bond contact and thus allows electrical continuity throughout the multi-die device 816.

Fig. 10A-10B illustrate a cross-sectional view of an exemplary second die 1002 in a partially fabricated state and a cross-sectional view of an exemplary second die 1004 in a completed state, respectively, the exemplary second die 1002 in a partially fabricated state including word line decoder circuitry and array circuitry. That is, the second die 1004 of fig. 10B is the second die 1002 after back-end-of-line (BEOL) processing.

Essentially, the cross-sectional view of fig. 10B is a more detailed version of the exemplary second die 804 shown in block diagram form in fig. 8A. An example second die 1004 that is fully fabricated shows a word line decoder 816 and a hybrid bond layer 812, which are represented by component illustrations rather than in block diagram form. However, fig. 10B also shows details not shown in fig. 8A, namely a second hybrid bonding contact. As described above, after hybrid bonding, the first hybrid bond contact is in physical contact with the second hybrid bond contact and thus allows electrical continuity throughout the multi-die device 816.

Fig. 11 is a cross-sectional view of an exemplary multi-die 3D PCM device 1100, the multi-die 3D PCM device 1100 having a PCM array on one die and word line decoders associated with the PCM array on a different die. Fig. 11 illustrates the example first die 902 of fig. 9 hybrid bonded to an example second die 1004. By placing the word line decoder circuitry on a different die than the die in which the 3D PCM array and its associated bit line decoder are disposed, multiple 3D PCM arrays may be more closely packed together compared to previous 3DPCM architectures in accordance with embodiments of the present disclosure. Thus, embodiments of 3D PCM architecture according to the present disclosure provide improved array efficiency and greater bit density.

Some embodiments

According to one aspect of the present disclosure, a multi-die 3D PCM product is disclosed. According to the present disclosure, a 3D PCM made of at least two dies includes a first die having at least one bit line decoder, at least one PCM cell array including a plurality of bit lines coupled to the first bit line decoder of the at least one bit line decoder, a plurality of word lines coupled to the at least one PCM cell array, and a first hybrid bonding layer configured for hybrid bonding, the first hybrid bonding layer disposed on a top side of the first die. The 3D PCM made of at least two dies may further include a second die having at least one word line decoder circuit and a second hybrid bonding layer configured for hybrid bonding, the second hybrid bonding layer being disposed on a top side of the second die. In some embodiments, the first hybrid bond layer has a plurality of first hybrid bond contacts disposed therein and the second hybrid bond layer has a plurality of second bond contacts disposed therein. The first die and the second die are hybrid bonded to each other in a face-to-face arrangement such that at least a portion of the first bonding contact and at least a portion of the second bonding contact are electrically connected to each other.

In some implementations, the at least one word line decoder circuit has a plurality of word line decoder output terminals, and each of the plurality of word line decoder output terminals is coupled to the at least one second bonding contact.

In some implementations, each of the plurality of word lines is coupled to at least one first bonding contact.

In some implementations, the at least one word line decoder circuit has a plurality of word line decoder output terminals, and each of the plurality of word line decoder output terminals is electrically coupled to at least one second bonding contact in the second bonding layer. Each of the plurality of word lines is electrically connected to at least one of the first bond contacts; and wherein each of the plurality of word lines in the first die is electrically coupled to at least one of the plurality of word line decoder output terminals in the second die.

In some implementations, the second die has a pad extraction dielectric layer disposed on a back side thereof, and the pad extraction dielectric layer has a plurality of recesses therein. In this example, the term "backside" is used if reference is made to a second die prior to hybrid bonding with a first die. After hybrid bonding, the first die may be considered the "bottom" die and the second die may be considered the "top" die, and in this frame of reference, i.e., after hybrid bonding, the "back side" of the second die corresponds to the "top side" of the hybrid bonded memory device.

In some embodiments, each of the plurality of conductive pads is disposed within a respective recess of the plurality of recesses in the pad extraction dielectric layer. In this example, the plurality of conductive pads may be formed by subtractive metallization processes, such as, but not limited to, copper metallization processes. In alternative embodiments, instead of forming recesses in the pad extraction dielectric layer, a blanket deposition of one or more layers of metal onto the pad extraction dielectric layer may be performed. The deposited metal(s) may then be patterned, followed by dielectric deposition operations and planarization operations.

In some implementations, at least one of the plurality of conductive pads is electrically coupled to circuitry on the second die through a Through Silicon Via (TSV). In this example, the TSVs provide a conductive path through the substrate of the second die that is electrically isolated from the substrate itself.

In some implementations, at least one of the plurality of conductive pads is electrically coupled to circuitry on the first die through a through silicon via.

In some implementations, the second die further includes a first circuit having one or more output terminals, and at least one of the first circuit output terminals is electrically coupled to at least one of the plurality of conductive pads.

In some implementations, the first circuit on the first die and the second circuit on the second die are electrically coupled to each other through a first one of the plurality of first bonding contacts and a first one of the plurality of second bonding contacts.

In some embodiments, the first circuit and the second circuit may be electrically coupled to at least one of the plurality of conductive pads.

In some implementations, the second die further includes a first circuit that is different from the word line decoder circuit and has one or more output terminals. In this example, at least one first circuit output terminal is electrically coupled to at least one of the plurality of second bonding contacts. By electrically coupling the first circuit output terminal on the second die to the second bonding contact, a signal path between the first die and the second die is provided.

According to another aspect of the present disclosure, a 3D memory is disclosed. For example, a 3D memory may use phase change material instead of transistors as separate storage bits, and these storage bits together with word lines and bit lines in a cross-point arrangement create a 3D memory. A 3D memory according to the present disclosure may include a first die having a first substrate, a bit line decoder circuit disposed on the first substrate, an array of PCM cells disposed over the bit line decoder circuit, a first bonding layer configured for hybrid bonding, the first bonding layer disposed on a top side of the first die. The 3D memory may further include a second die having a second substrate, word line decoder circuitry disposed on the second substrate, a second bonding layer configured for hybrid bonding, the second bonding layer disposed on a top side of the second die. In this exemplary embodiment, the first bonding layer has a plurality of first bonding contacts disposed therein, and the second bonding layer has a plurality of second bonding contacts disposed therein. And the plurality of first bonding contacts and the plurality of second bonding contacts are electrically conductive, the top side of the first die and the top side of the second die are hybrid bonded to each other in a face-to-face orientation such that at least a portion of the plurality of first bonding contacts and at least a portion of the plurality of second bonding contacts are electrically connected to each other, and the PCM cell array includes a plurality of bit lines and a plurality of word lines.

In some implementations, the bit lines of the PCM cell array are electrically coupled to the bit line decoder circuit of the first die, and the word lines of the PCM cell array are electrically coupled to the word line decoder circuit of the second die.

In some implementations, the bit lines are perpendicular to the word lines and are arranged in a cross-point memory architecture with PCM cells.

In some embodiments, a pad extraction dielectric layer having a thickness and having a plurality of recesses therein is disposed on a backside of the second die. In this example, the depth of each of the plurality of recesses is less than the thickness of the pad extraction dielectric layer.

In some embodiments, a plurality of conductive pads, each of the plurality of conductive pads may be disposed in a corresponding one of the plurality of recesses; and a Through Silicon Via (TSV) disposed through the second substrate. In this example, the TSV is electrically coupled to at least one of the plurality of conductive pads.

In some embodiments, the plurality of first bonding contacts comprises copper and the plurality of second bonding contacts comprises copper.

In some implementations, the word line decoder circuit includes a plurality of output terminals electrically coupled to the plurality of word lines through a corresponding plurality of second bonding contacts and a corresponding plurality of first bonding contacts, respectively.

According to another aspect of the present disclosure, a 3D PCM device includes a bit line decoder circuit disposed on a first die, a first hybrid bonding layer disposed on a first surface of the first die, a 3D PCM cell array disposed over the bit line decoder circuit, the 3D PCM cell array having a plurality of bit lines and a plurality of word lines. In addition, the word line decoder circuit may be disposed on the second die, the second hybrid bonding layer may be disposed on the first surface of the second die, and the pad extraction dielectric layer may be disposed on the second surface of the second die. In this example, the plurality of bit lines, the plurality of word lines, and the 3D PCM cell array are arranged in a cross point configuration. The first die and the second die are bonded to each other such that the first hybrid bonding layer and the second hybrid bonding layer are in contact with each other. Also, in accordance with the present disclosure, the plurality of bit lines are electrically coupled to bit line decoder circuitry disposed on a first die of the 3D PCM device, and the plurality of word lines are electrically coupled to word line decoder circuitry disposed on a second die of the 3D PCM device.

The foregoing description of the specific embodiments will so reveal the general nature of the disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments without undue experimentation, and without departing from the generic concept of the present disclosure. Accordingly, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specific functions and their relationships. For ease of description, the boundaries of these functional building blocks are arbitrarily defined herein. Alternate boundaries may be defined so long as the specified functions and relationships thereof are appropriately performed.

The summary and abstract sections may set forth one or more, but not necessarily all, exemplary embodiments of the present disclosure as contemplated by the inventors, and are, therefore, not intended to limit the disclosure and appended claims in any way.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A three-dimensional (3D) Phase Change Memory (PCM) comprising:

A first die having at least one bit line decoder, at least one PCM cell array comprising a plurality of bit lines coupled to a first bit line decoder of the at least one bit line decoder, a plurality of word lines coupled to the at least one PCM cell array, and a first bonding layer configured for hybrid bonding, the first bonding layer disposed on a top side of the first die; and

A second die having at least one word line decoder circuit, and a second bonding layer configured for hybrid bonding, the second bonding layer disposed on a top side of the second die;

Wherein the first bonding layer has a plurality of first bonding contacts disposed therein and the second bonding layer has a plurality of second bonding contacts disposed therein; and

Wherein the first die and the second die are hybrid bonded to each other in a face-to-face arrangement such that at least a portion of the first bonding contact and at least a portion of the second bonding contact are electrically connected to each other.

2. The 3D PCM of claim 1 wherein the at least one word line decoder circuit has a plurality of word line decoder output terminals, and each of the plurality of word line decoder output terminals is coupled to at least one second bonding contact.

3. The 3D PCM of claim 1, wherein each of the plurality of word lines is coupled to at least one first bonding contact.

4. The 3D PCM of claim 1 wherein the at least one word line decoder circuit has a plurality of word line decoder output terminals and each of the plurality of word line decoder output terminals is electrically coupled to at least one second bonding contact;

Wherein each word line of the plurality of word lines is electrically coupled to at least one of the first bonding contacts; and

Wherein each of the plurality of word lines in the first die is electrically coupled to at least one of the plurality of word line decoder output terminals of the second die.

5. The 3D PCM of claim 1 wherein the second die has a pad extraction dielectric layer disposed on a back side thereof and the pad extraction dielectric layer has a plurality of recesses therein.

6. The 3D PCM of claim 5, wherein each of a plurality of conductive pads is disposed within a corresponding recess of the plurality of recesses in the pad extraction dielectric layer.

7. The 3D PCM of claim 6 wherein at least one of the plurality of conductive pads is electrically coupled to circuitry on the second die through a through silicon via.

8. The 3D PCM of claim 6 wherein at least one of the plurality of conductive pads is electrically coupled to circuitry on the first die through a through silicon via.

9. The 3D PCM of claim 6 wherein the second die further comprises:

A first circuit having one or more output terminals;

wherein at least one first circuit output terminal is electrically coupled to at least one of the plurality of conductive pads.

10. The 3D PCM of claim 6, wherein the first circuit on the first die and the second circuit on the second die are electrically coupled to each other through a first one of the plurality of first bonding contacts and a first one of the plurality of second bonding contacts.

11. The 3D PCM of claim 10, wherein the first circuit and the second circuit are further electrically coupled to at least one of the plurality of conductive pads.

12. The 3D PCM of claim 1 wherein the second die further comprises:

A first circuit different from the word line decoder circuit, the first circuit having one or more output terminals;

Wherein at least one first circuit output terminal is electrically coupled to at least one of the plurality of second bonding contacts.

13. A three-dimensional (3D) memory, comprising:

a first die having a first substrate, a bit line decoder circuit disposed on the first substrate, an array of Phase Change Memory (PCM) cells disposed over the bit line decoder circuit, a first bonding layer configured for hybrid bonding, the first bonding layer disposed on a top side of the first die; and

A second die having a second substrate, word line decoder circuitry disposed on the second substrate, a second bonding layer configured for hybrid bonding, the second bonding layer disposed on a top side of the second die;

wherein the first bonding layer has a plurality of first bonding contacts disposed therein and the second bonding layer has a plurality of second bonding contacts disposed therein;

Wherein the first plurality of bonding contacts and the second plurality of bonding contacts are electrically conductive;

wherein the top side of the first die and the top side of the second die are hybrid bonded to each other in a face-to-face orientation such that at least a portion of the plurality of first bonding contacts and at least a portion of the plurality of second bonding contacts are electrically connected to each other; and

Wherein the PCM cell array includes a plurality of bit lines and a plurality of word lines.

14. The 3D memory of claim 13, wherein the bit lines of the PCM cell array are electrically coupled to the bit line decoder circuit of the first die and the word lines of the PCM cell array are electrically coupled to the word line decoder circuit of the second die.

15. The 3D memory of claim 14, wherein the bit line is perpendicular to the word line and is arranged in a cross-point memory architecture with the PCM cell.

16. The 3D memory of claim 15, wherein a pad extraction dielectric layer having a thickness and having a plurality of recesses therein is disposed on a backside of the second die;

wherein a depth of each recess of the plurality of recesses is less than the thickness of the pad extraction dielectric layer.

17. The 3D memory of claim 16, further comprising:

a plurality of conductive pads, each of the plurality of conductive pads disposed in a corresponding recess of the plurality of recesses; and

A Through Silicon Via (TSV) disposed through the second substrate;

wherein the TSV is electrically coupled to at least one of the plurality of conductive pads.

18. The 3D memory of claim 13, wherein the first plurality of bonding contacts comprises copper and the second plurality of bonding contacts comprises copper.

19. The 3D memory of claim 13, wherein the word line decoder circuit comprises a plurality of output terminals electrically coupled to the plurality of word lines through a corresponding plurality of second bonding contacts and a corresponding plurality of first bonding contacts, respectively.

20. A three-dimensional (3D) Phase Change Memory (PCM) device comprising:

Bit line decoder circuitry disposed on the first die;

A first hybrid bonding layer disposed on a first surface of the first die;

A 3D PCM cell array disposed over the bit line decoder circuit, the 3D PCM cell array having a plurality of bit lines and a plurality of word lines;

a word line decoder circuit disposed on the second die;

a second hybrid bonding layer disposed on the first surface of the second die; and

A pad extraction dielectric layer disposed on a second surface of the second die;

Wherein the plurality of bit lines, the plurality of word lines, and the 3D PCM cell array are arranged in a cross-point configuration;

Wherein the first die and the second die are bonded to each other such that the first hybrid bonding layer and the second hybrid bonding layer are in contact with each other; and

Wherein the plurality of bit lines are electrically coupled to the bit line decoder circuit disposed on the first die and the plurality of word lines are electrically coupled to the word line decoder circuit disposed on the second die.