CN118156251A - Through silicon via interconnection structure and forming method - Google Patents
Through silicon via interconnection structure and forming method Download PDFInfo
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- CN118156251A CN118156251A CN202410267603.1A CN202410267603A CN118156251A CN 118156251 A CN118156251 A CN 118156251A CN 202410267603 A CN202410267603 A CN 202410267603A CN 118156251 A CN118156251 A CN 118156251A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
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- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The embodiment of the invention discloses a through silicon via interconnection structure and a forming method thereof, wherein the structure comprises a first substrate with a first surface and a second surface, and a plurality of through holes are arranged on the first substrate; the first conductive piece is partially filled in the through hole, the top of the first conductive piece is in a groove shape and is lower than the second surface, and the bottom of the first conductive piece is flush with the first surface; a second substrate having a third surface provided with a plurality of through holes of the second conductive member partially filled; a bonding pad formed at the bottom of the first conductive member; the bottom surface of the connecting piece is welded with the bonding pad, the top point of the connecting piece is connected with the top of the second conductive piece, and a filling area is formed between the first substrate and the second substrate; conductive material coating the bonding pads and the connectors; and an adhesive member filled in the filling region to adhere the first substrate and the second substrate. Through the mode, the method can save time cost and economic cost caused by multiple electroplating, can realize bonding with high adhesive strength at low temperature, and further reduces the economic cost.
Description
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a through silicon via interconnection structure and a forming method.
Background
Through silicon via (Through Silicon Via, TSV) technology is a core technology that enables three-dimensional integrated circuit (INTEGRATED CIRCUIT, IC) integration. It provides the ability for shortest chip-to-chip interconnects and interconnects of minimum pad size and pitch. TSV technology has a number of advantages over conventional interconnect technology, including lower power consumption, better electrical performance, higher density, wider data width and bandwidth, and lighter weight. The TSV technology can be applied to various electronic components such as a micro processing unit (Microprocessor Unit, MPU), a programmable logic device (Programmable Logic Device, PLD), a dynamic random access memory (Dynamic Random Access Memory, DRAM), a graphic electronic chip, a CMOS image sensor, and the like.
The process flow of the TSV comprises the formation of a through hole, the manufacture of a related special wafer, the metallization of the through hole and the bonding of the TSV. Typically in chip fabrication, the metal conductor layer is typically prepared using physical vapor deposition (Physical Vapor Deposition, PVD). If the TSV via is also prepared using PVD, this takes a lot of time and costs compared to a few tens of nanometers of wires. Thus, the via metallization of TSVs is typically performed by electroplating. But because the conductivity of the substrate of the silicon substrate is poor, the electro-precipitation cannot be directly carried out; therefore, the metallization will first be performed by PVD to deposit an electronic layer having a thickness of a few nanometers, and then electroplating (similar to damascene electroplating) after the silicon substrate is rendered conductive. This will result in different locations of the vias on the wafer and different plating levels, since the current near the edge of the wafer is higher, the vias near the edge of the wafer are plated to a higher level than the center vias.
Interconnections between wafers that complete via metallization and connection terminals are commonly referred to as TSV bonding techniques. The technology adopts metal-metal bonding technology, macromolecule adhesive bonding technology and the like, and the metal-metal bonding technology is used as a main mode at present. Copper-copper diffusion welding is carried out at 350-4000 ℃ under a certain pressure and for a period of time, then TSV bonding is completed by annealing in a nitrogen annealing furnace for a certain time, and the welding strength is high but the heat load is large and the economic cost is high by applying the technology; the solder ball welding forms stable mechanical and electrical connection between the 3D chip layers by means of BGA solder ball reflow; the conductive adhesive bonding technique uses a conductive adhesive to bond the bonding pads, and the technique can greatly reduce the heat load, but has low bonding strength and poor reliability.
Disclosure of Invention
The technical problem mainly solved by the embodiment of the invention is to provide the through silicon via interconnection structure and the forming method, so that the time cost and the economic cost caused by multi-stage electroplating can be saved, and meanwhile, the bonding with high bonding strength can be realized under the low-temperature condition, so that the economic cost is further reduced.
In order to solve the technical problems, one technical scheme adopted by the embodiment of the invention is as follows: provided is a through silicon via interconnect structure, including: the first substrate is provided with a first surface and a second surface, and a plurality of through holes penetrating through the first surface and the second surface are formed in the first substrate; the top of the first conductive piece is in a groove shape and is lower than the second surface, and the bottom of the first conductive piece is flush with the first surface; a second substrate with a third surface, provided with a plurality of through holes filled with second conductive elements; a bonding pad formed at the bottom of the first conductive member; the bottom surface of the connecting piece is welded with the bonding pad, the top point of the connecting piece is connected with the top of the second conductive piece, and a filling area is formed between the first substrate and the second substrate; the conductive material covers the bonding pad and the connecting piece, and covers the top of the second conductive piece and the unconnected area of the connecting piece; and an adhesive member filled in the filling region to adhere the first substrate and the second substrate.
In some embodiments, the first substrate and the second substrate are both wafers.
In some embodiments, the conductive material comprises a conductive gel.
In some embodiments, the material of the adhesive comprises an adhesive.
In some embodiments, the material of the first and second conductive members comprises copper and the material of the connector comprises gold.
In order to solve the technical problems, another technical scheme adopted by the embodiment of the invention is as follows: the method for forming the through silicon via interconnection structure comprises the following steps: drilling holes on a first substrate with a first surface and a second substrate with a third surface, and correspondingly forming a plurality of through holes; partially filling a conductive medium in the through hole to form a first conductive member and a second conductive member with groove-shaped tops in the through hole respectively; grinding by a wafer so that the bottom of the first conductive element is exposed to the first surface and the bottom is flush with the first surface; forming a bonding pad at the bottom of the first conductive member; generating a connection on the bonding pad; depositing a conductive material on top of the second conductive member; stacking the first and second substrates by connecting the vertex of the connection member with the top of the second conductive member, the first and third surfaces being parallel; curing the conductive material.
In some embodiments, a method of forming a through silicon via interconnect structure further comprises: filling an underfill material in a fill region between the first substrate and the second substrate; the underfill material is cured to form a bond to bond the first substrate and the second substrate.
In some embodiments, the stacking the first substrate and the second substrate by connecting the vertex of the connection member with the top of the second conductive member includes: aligning the apexes of the connection members with the tops of the second conductive members so that the apexes of any one connection member are in contact with the tops of the corresponding second conductive members through the conductive material; pressure is applied to bring the apex of each connector into contact with the top of a corresponding second conductor through the conductive material to stack the first and second substrates with the first surface parallel to the third surface.
In some embodiments, the process of filling the via with a conductive medium includes an electroplating process.
In some embodiments, the process of creating the connector includes a wire bonding process.
The beneficial effects of the embodiment of the invention are as follows: unlike the prior art, the embodiment of the invention firstly only needs partial metallization, thereby reducing the time cost and the economic cost caused by complete electroplating; secondly, in the structure, the connection between the conical connecting piece and the top of the second conductive piece in a groove shape achieves the effect of 'nailing', so that the connection strength of the first substrate and the second substrate is increased; furthermore, the electrical path mainly flows from the gold connecting piece to the copper conducting piece, and even the copper conducting piece is filled with conducting materials to prevent incomplete contact between the connecting piece and the conducting piece, so that the electrical performance is enough to meet the requirements of most application scenes; finally, on the premise that the electrical performance meets the requirement, the bonding piece is filled between the first substrate and the second substrate, namely, the bonding is performed in a high polymer bonding mode, so that the heat load can be greatly reduced on the premise of ensuring high bonding strength, and the time cost and the economic cost are reduced.
Drawings
FIG. 1 is a cross-sectional view of a through silicon via metallization process plated for 6 hours;
FIG. 2 is a cross-sectional view of a through silicon via metallization process plated for 8 hours;
FIG. 3 is a cross-sectional view of a through silicon via metallization process plated for 12 hours;
FIG. 4 is a schematic illustration of a through-silicon via interconnect structure according to an embodiment of the present invention;
FIG. 5 is a cross-sectional view of through silicon via metallization at different locations in a wafer;
FIG. 6 is a schematic illustration of another through-silicon via interconnect structure provided in accordance with an embodiment of the present invention;
FIG. 7 is a cross-sectional view of a chip stack implemented using the through-silicon via interconnect structure provided by the present invention;
fig. 8 is a flowchart illustrating a method for forming a through-silicon via interconnect structure according to an embodiment of the present invention.
Detailed Description
In order that the application may be readily understood, a more particular description thereof will be rendered by reference to specific embodiments that are illustrated in the appended drawings. It will be understood that when an element is referred to as being "fixed" to another element, it can be directly on the other element or one or more intervening elements may be present therebetween. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or one or more intervening elements may be present therebetween. The terms "upper," "lower," "inner," "outer," "bottom," and the like as used in this specification are used in an orientation or positional relationship based on that shown in the drawings, merely to facilitate the description of the application and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the application. Furthermore, the terms "first," "second," "third," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and/or" as used in this specification includes any and all combinations of one or more of the associated listed items.
In addition, the technical features mentioned in the different embodiments of the application described below can be combined with one another as long as they do not conflict with one another.
The through silicon via process includes the processes of forming a via, fabricating a related special wafer, metallizing the via, and bonding the TSV, wherein the metallization of the via generally adopts a physical weather precipitation method to fill the via, however, due to the large volume of the TSV, a lot of time and economic costs are consumed if the physical weather precipitation method is also used. Thus, in the TSV via, the electroplating process is usually performed in a manner of electroplating, in which metal ions are reduced from an electrolyte to metal atoms, and then gradually precipitate on defects or active points on the surface of the TSV via, to form a continuous metal plating layer.
However, at the beginning of electroplating, it is generally true that higher efficiency is exhibited. This is because, at the very beginning, defects and active sites on the substrate surface are not sufficiently filled with metal atoms, and metal ions are more easily adsorbed and reduced to metal atoms, and the process of forming the metal plating layer is relatively rapid. As the plating time increases, the metal plating layer gradually thickens, active sites on the substrate surface are also gradually filled, and the reduction and deposition rates of metal ions may gradually decrease, thereby affecting the efficiency of the entire plating process. Therefore, as the plating time increases and the metal plating layer increases, the plating efficiency gradually decreases, inevitably increasing the time cost and economic cost of the via metallization. Meanwhile, in order to achieve the effect of complete filling, the industry also generally reduces the electroplating current artificially, thereby reducing the electroplating efficiency, and increasing the time cost of through hole metallization.
Fig. 1,2 and 3 are cross-sectional views of a first stage plating, a second stage plating and a third stage plating, respectively, of a TSV through-hole, a multi-stage plating is performed in the through-hole of the first substrate 100 to form the conductive member 110, wherein the first stage plating has a completion time of about 6 hours, the second stage plating has a completion time of about 8 hours, and the third stage plating has a completion time of about 12 hours. As can be seen from fig. 1, after the first stage of electroplating, the conductive member formed by electroplating metal is in a groove shape, and the conventional TSV bonding technology is combined, for example, the metal-metal bonding technology includes diffusion welding and solder ball welding, wherein the diffusion welding is to make the conductive member and the conductive member apply a certain pressure at a temperature of 350-4000 ℃ and keep for a period of time, and then anneal in a nitrogen annealing furnace for a certain time to complete TSV bonding, however, when the top of the conductive member is in a groove shape, the top of the conductive member cannot fully contact with the bottom of another conductive member, and effective electrical interconnection cannot be formed between the two conductive members, so that the metal-metal bonding technology cannot be implemented when the top of the conductive member is in a groove shape; the solder ball solder is formed between 3D chip layers by means of BGA solder reflow to form stable mechanical and electrical connection, and similarly, when the top of the conductive member is in a groove shape, the BGA solder soldered at the bottom of the conductive member cannot fully contact with the top of the other conductive member, and no effective electrical interconnection can be formed between the two conductive members, so that the solder ball soldering technique cannot be implemented when the top of the conductive member is in a groove shape.
If the bonding is performed by using a polymer bonding method, a conductive adhesive bonding technology is generally adopted, that is, a conductive adhesive is used to bond the bonding pads, however, the technology is implemented on the premise that the bonding pads are required for the top and the bottom of the conductive member, and the bottom of the conductive member can be ground and flattened through a wafer, so that the electrical performance and the bonding strength of the bonding pads at the bottom are qualified, however, the bonding pads cannot be well bonded due to the groove shape of the top of the conductive member, and therefore, the bonding pads are not bonded by the conductive adhesive. As with the TSV via shown in fig. 2, the conductive member of fig. 2 is filled more fully than the conductive member shown in fig. 1, but still has a recess, and direct bonding likewise has fatal defects. Electroplating is thus continued until the conductive member is formed into the shape shown in fig. 3, so as to avoid the fatal defects of the metal-metal bonding technique, the solder ball bonding technique, or the polymer adhesive bonding method.
In order to reduce the electroplating time of the via metallization, reduce the thermal load and the economic cost, the embodiment of the present invention provides a through-silicon via interconnection structure, which is schematically shown in fig. 1, and includes a first substrate 100, a first conductive member 110, a second substrate 200, a second conductive member 210, a bonding pad 300, a connection member 400, a conductive material 500 and an adhesive member 600.
The first substrate 100 has a first surface and a second surface opposite to each other, and a plurality of through holes penetrating the first surface and the second surface are provided, and fig. 1 shows only one through hole structure of the first substrate; the first conductive element 110 is partially filled in the through hole of the first substrate 100, and the bottom of the first conductive element 110 is flush with the first surface, and the top of the first conductive element 110 is in a groove shape and lower than the second surface because the filling mode is a bottom-up electroplating process and is not completely filled.
By way of example and not limitation, the conductive member according to the embodiments of the present application is a conductive member formed by electroplating for 6 hours as shown in fig. 1.
The second substrate 200 has a third surface and is provided with a plurality of through holes filled with the second conductive elements 210, and in fact, the second substrate 200 may have the same structure as the first substrate 100, i.e. the second conductive elements 210 may be filled in the same manner as the first conductive elements 110, but the present embodiment mainly describes the connection structure of the first substrate 100 and the second substrate 200, so that the second substrate 200 only needs to show the top of the second conductive elements 210. The pad 300 is disposed at the bottom of the first conductive member 110.
In some embodiments of the present application, the first substrate 100 and the second substrate 200 are both wafers.
In an embodiment of the present application, the material of the first conductive member 110 and the second conductive member 210 includes copper.
The connection member 400 is disposed on the bonding pad 300, and in the embodiment of the present application, the connection member 400 is tapered and has a bottom surface and an apex, the bottom surface of the connection member 400 is welded to the bonding pad 300, the apex of the connection member 400 is connected to the top of the second conductive member 210, and a filling area is formed between the first substrate 100 and the second substrate 200.
The connection member 400 is tapered, so that the connection between the tapered connection member 400 and the top of the second conductive member 210 having the groove shape achieves the effect of "nailing", thereby increasing the connection strength between the first substrate 100 and the second substrate 200, and increasing the contact area between the connection member 400 and the second conductive member 210, thereby improving the electrical performance. The principle is that the connection member 400 is deformed by applying pressure after the connection member 400 is in contact with the second conductive member 210, thereby increasing the contact area between the two. In other embodiments, the connector 400 may be made cylindrical.
By way of example and not limitation, the material of the connector 400 includes gold.
The conductive material 500 encapsulates the bonding pad 300 and the connection member 400, and the connection member 400 is insufficient to achieve complete contact between the connection member 400 and the second conductive member 210 after being connected to the top of the second conductive member 210, so that there is a portion of the unconnected area on top of the second conductive member 210, and the conductive material 500 also covers the unconnected area.
By way of example and not limitation, the conductive material 500 includes a conductive gel.
The adhesive member 600 is filled in the filling region to adhere the first substrate 100 and the second substrate 200.
By way of example and not limitation, the material of the adhesive 600 includes an adhesive.
As shown in fig. 5, which is a cross-sectional view of through-silicon via metallization at different positions in a wafer, the through-silicon via interconnection structure provided by the embodiment of the invention is applied to an incompletely electroplated through-silicon via, and it can be seen that the through-silicon via metallization at different positions on the wafer has different electroplating degrees, and the through-silicon via metallization degree near the edge of the wafer is higher than that of the central through-silicon via due to larger current near the edge of the wafer.
Since the first substrate is to be kept flush with the second substrate, the connection element is deformed to different extents in connection with the second conductive element at different positions. The cross-sectional view of the connecting piece with the second conductive piece at the center is shown in fig. 4, the cross-sectional view of the connecting piece with the second conductive piece at the edge is shown in fig. 6, and the vertex of the conical connecting piece is deformed as seen in fig. 6, so that the contact area between the connecting piece and the second conductive piece is increased, and the invention can be applied to the practical situation of different electroplating degrees of the same wafer through hole.
The chip stacking structure realized by applying the through silicon via interconnection structure provided by the invention is shown in fig. 7.
Firstly, because the hardness of the gold connecting piece is lower, extrusion deformation exists in the through hole at the edge of the wafer, and the conical connecting piece deformation does not influence the matching quality, so that all the connecting pieces and the through holes can be matched at the same height. Secondly, the bonding strength of the invention is evaluated through a shear test and a peeling test, the maximum internal stress of the bonded through-silicon via interconnection structure is 0.65MPa, and the maximum internal stress of the through-silicon via interconnection structure provided by the invention is 0.35MPa, and the bonding strength is high by comparing and finding that the internal stress of the invention can be reduced by 47%. Finally, the electrical path of the through silicon via interconnection structure provided by the invention is mainly a gold connecting piece-copper second conductive piece, so that the current carrying capacity is stronger than that of conductive adhesive, and even if poor contact exists between the connecting piece and the second conductive piece, conductive materials are deposited, so that the requirements of most application scenes are still met in the electrical performance. In other cases, only a slight compressive force is applied to bring the connector into contact with the second conductive member, and the conductive material is present to ensure that the open circuit ratio between the connector and the second conductive member is 0.
Unlike the prior art, the embodiment of the invention firstly only needs partial metallization, thereby reducing the time cost and the economic cost caused by complete electroplating; secondly, in this structure, the connection between the tapered connector 400 and the top of the second conductive member 210 having a groove shape achieves the effect of "nailing", thereby increasing the connection strength of the first substrate 100 and the second substrate 200, and furthermore, the electrical path mainly flows from the gold connector to the copper conductive member, and even further fills the conductive material to prevent incomplete contact between the connector and the conductive member, so that the electrical performance is sufficient to satisfy the requirements of most application scenarios; finally, on the premise that the electrical performance meets the requirement, the bonding piece is filled between the first substrate and the second substrate, namely, the bonding is performed in a high polymer bonding mode, so that the heat load can be greatly reduced on the premise of ensuring high bonding strength, and the time cost and the economic cost are reduced.
In order to realize the through-silicon via interconnection structure provided in the above embodiment, the embodiment of the present invention further provides a method for forming the through-silicon via interconnection structure, where a flow chart of the method is shown in fig. 8, and the method specifically includes the following steps:
step S100: drilling holes on a first substrate with a first surface and a second substrate with a third surface, and correspondingly forming a plurality of through holes.
The first substrate and the second substrate are both wafers, and specifically, the wafer drilling is generally implemented by the following methods:
laser drilling: laser drilling is a common method of instantaneously heating a silicon wafer by a high-energy laser beam, melting and evaporating silicon material, thereby forming a through hole. Laser drilling has the advantages of high precision, high speed and non-contact, is suitable for micro holes and generates less damage.
Dry etching: dry etching is a technique that utilizes chemical vapor deposition (Chemical Vapor Doping, CVD) or physical vapor deposition to deposit photoresist on a silicon wafer and pattern it using a photolithographic process, and then removes the silicon material in the non-protected areas by dry etching to form holes.
Wet etching: wet etching is to coat photoresist on a silicon wafer, then pattern the photoresist by using a photolithography technique, and then immerse the silicon in a wet etching solution to dissolve or corrode the silicon material in the unprotected area to form a through hole.
Electrochemical corrosion: and (3) preparing a metal layer on the silicon wafer by using an electric corrosion technology, and performing a photoetching process, and then dissolving a certain part of the silicon wafer by adopting an electrochemical corrosion mode to form a through hole structure.
Through any one of the above modes, a plurality of through holes are formed in the first substrate and the second substrate respectively.
Step S200: the through hole is partially filled with a conductive medium to form a first conductive member and a second conductive member having a groove-like top, respectively, in the through hole.
Specifically, through a bottom-up electroplating process, metal ions are reduced into metal atoms from an electrolyte, then gradually separated out on defects or active points on the surface of the TSV through hole, continuous metal plating layers are formed in a plurality of through holes of the first substrate and the second substrate, and corresponding first conductive members and second conductive members with groove-shaped tops are formed. Of course, if necessary, only multi-stage plating may be required.
Step S300: the bottom of the first conductive member is exposed to the first surface by wafer polishing, and the bottom is flush with the first surface.
Wafer polishing is one of the common process steps in semiconductor manufacturing processes for achieving flatness and thickness uniformity requirements on the wafer and exposing the bottom of the first conductive member to the first surface.
The wafer polishing step comprises: surface cleaning: before grinding, the surface of the wafer needs to be cleaned to remove impurities and dirt attached to the surface, so that no extra pollution is introduced in the grinding process; grinding: grinding refers to grinding the wafer surface using a grinder or grinding equipment to remove a portion of the wafer thickness to achieve the desired flatness and surface quality requirements. During grinding, a grinding disc and grinding liquid are used for processing; and (3) detection: after finishing grinding, the wafer is usually detected to ensure that the thickness and the flatness after grinding meet the process requirements; cleaning: after polishing, the wafer needs to be cleaned again to ensure that no residual polishing liquid or particles remain on the surface.
The wafer polishing method comprises the following steps:
Mechanical grinding: grinding by using grinding mechanical equipment, and grinding the surface of the wafer by using a grinding disc and grinding liquid to realize the control of flatness and thickness; chemical mechanical polishing (CHEMICAL MECHANICAL Polish, CMP): CMP is a method of combining chemical etching and mechanical polishing, and is a method of adding a chemical solution to a grinding fluid to grind and planarize a wafer surface.
Step S400: a bonding pad is formed at the bottom of the first conductive member.
In the embodiment of the application, the bonding pad is formed on the bottom of the first conductive member exposed on the first surface, the shape of the bonding pad is not limited, and the bonding pad can be rectangular or circular, the area of the bonding pad is larger than the area of the bottom of the first conductive member, and the center point of the bonding pad is in the same straight line with the center point of the bottom of the first conductive member in the vertical direction.
Bonding pads are important structures for connecting the internal metal layers of the chip with external package pins or substrates, and the generation of the bonding pads generally comprises the following steps:
Trimming the orifice: after forming the through holes on the silicon wafer by etching or laser drilling, the through hole openings usually need to be trimmed to ensure that the shapes and sizes of the through hole openings meet the requirements.
Filling metal: the metal is filled into the via by electrochemical filling or other hole filling process to form the metal portion of the pad. The choice of filler metal will generally depend on the particular requirements, and common metals include copper, cobalt, nickel, and the like.
Forming a pad shape: after filling with metal, the desired shape and surface flatness of the bond pad is formed by subsequent processing steps (e.g., chemical mechanical polishing CMP) for subsequent soldering, packaging, etc.
Forming a protective layer: in order to protect the bonding pad and its surrounding structures from oxidation or contamination, a protective layer, such as tungsten, tungsten-copper alloy, etc., is usually formed on the surface of the bonding pad.
Step S500: a tapered connector is created on the pad.
In an embodiment of the present application, the connecting member is tapered, and a center point of a bottom surface of the connecting member coincides with a center point of a bottom portion of the first conductive member. The generation of the connecting piece adopts a wire bonding process, and the specific implementation steps are as follows:
Preparation: first, the substrate or device to be spotted is prepared, the appropriate gold wire material (typically gold or copper) is selected, and the readiness of the other process equipment and materials is ensured.
Preparing a substrate: the surface of the substrate on which the gold stud bumps are required to be dotted is cleaned, and the surface is ensured to be free of impurities or oxides and other substances which affect the spot welding quality.
Gold wire cutting: the gold wire material is cut to an appropriate length for the subsequent spot welding operation.
Spot welding operation: and fixing the gold wire on the wire bonding equipment, and precisely controlling parameters such as spot welding temperature, pressure, time and the like through a control system of the equipment, so that the gold wire is adhered to the surface of the substrate and a raised conical gold stud bump structure is formed.
And (3) quality inspection: after the gold stud bumps are spotted, quality inspection is carried out, the quality of spot welding is ensured to meet the requirements, and the gold stud and the substrate are firmly connected and have good electrical property.
Cleaning and packaging: and cleaning the spot welding area, removing welding residues, performing subsequent processing steps such as packaging and the like, protecting the gold stud bump and ensuring the integrity of the device.
Step S600: a conductive material is deposited on top of the second conductive member.
In the embodiment of the application, the conductive material is conductive adhesive, and conductive adhesive deposition is a key step in the TSV process, and is used for filling the cavity in the TSV structure and realizing electrical connection. The following are general steps and principles for conductive paste deposition in the TSV process:
Pretreatment: prior to conducting paste deposition, the TSV structure needs to be pre-treated, including cleaning and surface treatments, to ensure good adhesion and conductivity.
Filling conductive adhesive: the conductive paste is generally a conductive material and may be filled in the TSV structure. And injecting conductive adhesive into the groove-shaped TSV structure through a specific process, filling the cavity and connecting with other parts of the chip.
Step S700: the first surface and the third surface are opposite by connecting the apex of the connecting member with the top of the second conductive member to stack the first substrate and the second substrate.
In the embodiment of the present application, step S700 includes the following steps:
Aligning the apexes of the connecting pieces with the tops of the second conductive pieces, so that the apexes of any connecting piece are contacted with the tops of the corresponding second conductive pieces through conductive materials; the vertex of each connecting piece is contacted with the top of the corresponding second conductive piece through the conductive material by applying pressure so as to stack the first substrate and the second substrate, and the first surface is parallel to the third surface.
Step S800: the conductive material is cured.
The deposition of the conductive paste in step S600 further includes the steps of:
curing: after filling the conductive paste, a curing process is required, i.e., the conductive paste is heated or chemically cured to form stable connections and structures.
Flattening: after the conductive paste is cured, a surface planarization process is also typically required to ensure the flatness and structural integrity of the overall chip.
Step S900: an underfill material is filled in a fill region between the first substrate and the second substrate.
In the embodiment of the application, the purpose of filling the underfill material between the first substrate and the second substrate is to fix interlayer connection, and the underfill material is an adhesive, and specifically comprises the following steps:
Preparation: prior to filling the adhesive, the TSV structures need to be cleaned and surface treated to ensure that the adhesive adheres uniformly and fills the voids.
Filling an adhesive: a suitable adhesive, typically a flowable and adhesive material, is selected to fill the TSV structure, fill the voids and form the connection.
Step S1000: the underfill material is cured to form a bond to bond the first substrate and the second substrate.
Step S1000 is a complementary step to step S900, i.e. filling the underfill material further comprises the steps of:
Curing: after the adhesive is filled, it is necessary to perform a curing process, and the adhesive is heated or chemically cured to form a stable connection, thereby fixing the interlayer structure inside the chip.
Flattening: after filling the adhesive, a surface planarization process is sometimes required to ensure the flatness and surface quality of the overall chip.
Unlike the prior art, the embodiment of the invention firstly only needs partial metallization, thereby reducing the time cost and the economic cost caused by complete electroplating; secondly, in this structure, the connection between the tapered connector 400 and the top of the second conductive member 210 having a groove shape achieves the effect of "nailing", thereby increasing the connection strength of the first substrate 100 and the second substrate 200, and furthermore, the electrical path mainly flows from the gold connector to the copper conductive member, and even further fills the conductive material to prevent incomplete contact between the connector and the conductive member, so that the electrical performance is sufficient to satisfy the requirements of most application scenarios; finally, on the premise that the electrical performance meets the requirement, the bonding piece is filled between the first substrate and the second substrate, namely, the bonding is performed in a high polymer bonding mode, so that the heat load can be greatly reduced on the premise of ensuring high bonding strength, and the time cost and the economic cost are reduced.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting; the technical features of the above embodiments or in the different embodiments may also be combined within the idea of the application, the steps may be implemented in any order, and there are many other variations of the different aspects of the application as above, which are not provided in details for the sake of brevity; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.
Claims (10)
1. A through silicon via interconnect structure, comprising:
the first substrate is provided with a first surface and a second surface, and a plurality of through holes penetrating through the first surface and the second surface are formed in the first substrate;
the top of the first conductive piece is in a groove shape and is lower than the second surface, and the bottom of the first conductive piece is flush with the first surface;
a second substrate with a third surface, provided with a plurality of through holes filled with second conductive elements;
A bonding pad formed at the bottom of the first conductive member;
the bottom surface of the connecting piece is welded with the bonding pad, the top point of the connecting piece is connected with the top of the second conductive piece, and a filling area is formed between the first substrate and the second substrate;
the conductive material covers the bonding pad and the connecting piece, and covers the top of the second conductive piece and the unconnected area of the connecting piece;
and an adhesive member filled in the filling region to adhere the first substrate and the second substrate.
2. The structure of claim 1, wherein the first substrate and the second substrate are both wafers.
3. The structure of claim 1, wherein the conductive material comprises a conductive gel.
4. The structure of claim 1, wherein the material of the adhesive comprises an adhesive.
5. The structure of any of claims 1-4, wherein the material of the first conductive member and the second conductive member comprises copper and the material of the connector comprises gold.
6. A method for forming a through silicon via interconnect structure, comprising:
Drilling holes on a first substrate with a first surface and a second substrate with a third surface, and correspondingly forming a plurality of through holes;
partially filling a conductive medium in the through hole to form a first conductive member and a second conductive member with groove-shaped tops in the through hole respectively;
Grinding by a wafer so that the bottom of the first conductive element is exposed to the first surface and the bottom is flush with the first surface;
forming a bonding pad at the bottom of the first conductive member;
Generating a tapered connector on the bonding pad;
depositing a conductive material on top of the second conductive member;
Stacking the first and second substrates by connecting the vertex of the connection member with the top of the second conductive member, the first and third surfaces being parallel;
Curing the conductive material.
7. The method as recited in claim 6, further comprising:
Filling an underfill material in a fill region between the first substrate and the second substrate;
the underfill material is cured to form a bond to bond the first substrate and the second substrate.
8. The method of claim 6, wherein stacking the first substrate and the second substrate by connecting the apex of the connector with the top of the second conductive element comprises:
aligning the apexes of the connection members with the tops of the second conductive members so that the apexes of any one connection member are in contact with the tops of the corresponding second conductive members through the conductive material;
Pressure is applied to bring the apex of each connector into contact with the top of a corresponding second conductor through the conductive material to stack the first and second substrates with the first surface parallel to the third surface.
9. The method of claim 6, wherein the process of filling the via with a conductive medium comprises an electroplating process.
10. The method of any of claims 6-9, wherein the process of creating the connection comprises a wire bonding process.
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