CN118041349B - External clock synchronization and internal clock bidirectional soft switching circuit and method - Google Patents
External clock synchronization and internal clock bidirectional soft switching circuit and method Download PDFInfo
- Publication number
- CN118041349B CN118041349B CN202410167729.1A CN202410167729A CN118041349B CN 118041349 B CN118041349 B CN 118041349B CN 202410167729 A CN202410167729 A CN 202410167729A CN 118041349 B CN118041349 B CN 118041349B
- Authority
- CN
- China
- Prior art keywords
- switch
- voltage
- input
- lpf
- output end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000002457 bidirectional effect Effects 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title claims abstract description 21
- 230000008859 change Effects 0.000 claims abstract description 14
- 238000001514 detection method Methods 0.000 claims description 24
- 238000013459 approach Methods 0.000 claims description 14
- 230000008569 process Effects 0.000 claims description 10
- 239000003990 capacitor Substances 0.000 claims description 5
- 230000007306 turnover Effects 0.000 claims description 3
- 230000007704 transition Effects 0.000 abstract description 9
- 230000001360 synchronised effect Effects 0.000 abstract description 7
- 230000002035 prolonged effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 8
- 230000001105 regulatory effect Effects 0.000 description 4
- 230000002411 adverse Effects 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000009897 systematic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention discloses a bidirectional soft switching circuit and a method for external clock synchronization and internal clock, wherein the bidirectional soft switching circuit is arranged on a PLL ∬ _clk module and comprises the following components: the output end of the voltage comparator is connected with the input end of the counting latch and the switch control logic circuit respectively, the output end of the counting latch is connected with the enabling end of the voltage comparator, the output end of the switch control logic circuit is connected with the fourth switch S4 and the fifth switch S5 respectively, the fourth switch S4 is also connected with the upper current source I4, and the fifth switch S5 is also connected with the lower current mirror I5. The bidirectional soft switching circuit and the method eliminate hard switching between the external synchronous frequency and the internal fixed working frequency, and the duration of the transition zone is adjustable, so that the DC-DC constant voltage or constant current output change is relaxed, the reliability of the whole switching power supply chip is improved, and the service life of the whole switching power supply chip is prolonged.
Description
Technical Field
The invention relates to the technical field of semiconductor phase-locked loops, in particular to an external clock synchronization and internal clock bidirectional soft switching circuit and method.
Background
The power management chip is widely applied to the fields of portable electronics, automobiles, lighting LEDs, household appliances and the like, wherein a switching power supply DC-DC occupies a main share due to high efficiency. Modern switching power supplies are more integrated and systematic, and often need to work cooperatively with external system control, such as MCU and the like; high power is also sought and multi-chip parallel connection is required. These complex control requirements typically require the integration of a phase-locked loop PLL within the switching power supply that can synchronize the external clock.
Fig. 1 is a schematic diagram of a switching power supply chip with a built-in PLL. The built-in PLL & Interclk module of the switching power supply is responsible for receiving and synchronizing clock signals generated by an external system MCU or a master parallel chip; if no external clock signal exists, the internal clock signal is generated by itself and sent to the PWM generator, and then the power MOS tube is driven by the driver to be continuously turned on and off, so that constant voltage or constant current is output for the load.
As shown in fig. 2, the CLKIN pin is used for receiving an external clock input, and the Clk detection module detects whether an external clock signal exists, and generates a clk_det signal, for example: a high level indicates that there is an external clock input at this time, and a low level indicates that there is no external clock input at this time. The phase frequency detector PFD, the charge pump CP, the capacitive low pass filter LPF and the voltage controlled oscillator VCO form a classical charge pump phase locked loop CPPLL. The voltage-controlled oscillator VCO is often formed by a voltage-controlled current module Gm and a current-type relaxation oscillator.
When a system or a main parallel chip sends out a clock signal with a specific frequency, the clock signal is sent to a CLKIN pin and a Clk detection module to generate Clk_det=1, an external clock signal is further sent to a phase frequency detector PFD, a switch S3 is closed, the phase frequency detector PFD compares the frequency and the phase difference between the external clock signal and the original internal working frequency of a voltage controlled oscillator VCO, the on-off time of the switch S1 and the switch S2 is adjusted, the V_lpf voltage is changed, a positive voltage and a negative voltage difference is generated between the voltage and Vref, so that the current flowing out or extracted by a voltage control current module Gm is changed, and finally the frequency of a current type relaxation oscillator is changed, so that the output frequency of the VCO is rapidly synchronized with the phase-locked external clock signal; when the system or the main parallel chip stops sending out the clock signal with the specific frequency, the Clk detection module can not detect the clock signal, the clk_det=0 is generated, the switch S3 is immediately disconnected, the slave chip slave stops the synchronization function, the current originally flowing out or flowing in the voltage control current module Gm is rapidly cut off, and the internal fixed bias current Ib is converted to generate the internal clock signal.
However, the original internal clock frequency and the external frequency often differ by several hundred KHz to up MHz, and the hard switching can cause the PLL & inter_clk module to generate frequency abrupt change, as shown in fig. 3, the PWM frequency, constant voltage or constant current output of the driving power MOS transistor also can be changed drastically, which adversely affects the load. For example, during constant voltage output, voltage overshoot may occur, and the system control is hard switched for a long time beyond the load withstand voltage, so that reliability problems are easily caused to the load, and even the load is damaged; when the LED is driven by constant current, obvious brightness change and even flashing frequency can occur, and the service life of the LED or the use experience of a customer is influenced.
Disclosure of Invention
Aiming at the problems existing in the prior art, the invention provides an external clock synchronization and internal clock bidirectional soft switching circuit and method, which are used for eliminating hard switching between the external synchronization frequency and the internal fixed working frequency, and the duration of a transition zone is adjustable, so that the DC-DC constant voltage or constant current output change is relaxed, the reliability of the whole switching power supply chip is improved, and the service life of the whole switching power supply chip is prolonged.
In order to achieve the technical purpose, the invention adopts the following technical scheme: an external clock synchronization and internal clock bidirectional soft switching circuit, provided on a PLL & inter_clk module, comprising: the output end of the voltage comparator is connected with the input end of the counting latch and the switch control logic circuit respectively, the output end of the counting latch is connected with the enabling end of the voltage comparator, the output end of the switch control logic circuit is connected with the fourth switch S4 and the fifth switch S5 respectively, the fourth switch S4 is also connected with the upper current source I4, and the fifth switch S5 is also connected with the lower current mirror I5;
after the external clock signal is removed, the voltage comparator continuously detects an input voltage signal V_lpf, compares the input voltage signal V_lpf with Vref, and controls the fourth switch S4 to be conducted through the switch control logic circuit if the input voltage signal V_lpf is smaller than Vref, so that the upper current source I4 charges the input voltage signal V_lpf; if the input voltage signal V_lpf is more than Vref, the switch control logic circuit controls the fifth switch to be turned on, so that the lower circuit source I5 discharges the input voltage signal V_lpf, and a soft switching process is realized;
the counting latch is used for recording the adjustment times of the voltage-controlled oscillator VCO input voltage signal V_lpf approaching Vref.
Further, the PLL & inter_clk module includes: the device comprises a Clk detection module, a phase frequency detector PFD, a first switch S1, a second switch S2, a first bias current I A, a second bias current I B, a capacitive low-pass filter LPF and a voltage-controlled oscillator VCO, wherein the CLKIN pin of the Clk detection module is used for receiving external clock input, the output end of the Clk detection module is connected with the first input end of the phase frequency detector PFD, the first output end of the phase frequency detector PFD is connected with one end of the first switch S1 and the output end of the first bias current I A in series, the input end of the first bias current I A is connected with an operating voltage VDD, the second output end of the phase frequency detector PFD is connected with one end of the second switch S2, one end of the second switch S2 is also connected with the other end of the first switch S1, the capacitive low-pass filter LPF and the input end of the voltage-controlled oscillator VCO, the other end of the second switch S2 is connected with the input end of the second bias current I B, and the output end of the second bias current I B is grounded; the output end of the voltage controlled oscillator VCO is respectively connected with a driver in the switching power supply DC-DC and the first input end of the phase frequency detector PFD.
Further, the voltage controlled oscillator VCO comprises: the voltage control current module Gm, the third switch S3 and the current type relaxation oscillator, wherein the output end of the voltage control current module Gm is connected with one end of the third switch S3, the other end of the third switch S3 is connected with the input end of the current type relaxation oscillator, and the output end of the current type relaxation oscillator is respectively connected with a driver in the DC-DC of the switching power supply and the first input end of the phase frequency detector PFD.
Further, a sixth switch S6 is further provided, the first input end of the voltage comparator is connected with the other end of the first switch S1, one end of the second switch S2, the input end of the capacitive low-pass filter LPF, one end of the sixth switch S6, the first input end of the voltage control current module Gm, the input end of the fourth switch S4, and the output end of the fifth switch S5, and the second input end of the voltage comparator is connected with the other end of the sixth switch S6; the Clk_det signal end of the voltage comparator is connected with the Clk_det signal end of the Clk detection module.
Further, the output end of the counting latch is also connected with a third switch S3 and a sixth switch S6 respectively.
Further, the switch control logic circuit includes: the input end of the first inverter Inv1 is connected with the Clk_det signal end of the Clk detection module, the output end of the first inverter Inv1 is respectively connected with the input end of the second inverter Inv2 And the first input end of the AND gate And2, the output end of the second inverter Inv2 is connected with the first input end of the OR gate Or2, the second input end of the OR gate Or2 And the second input end of the AND gate And2 are connected with the output end of the voltage comparator, the output end of the OR gate Or2 is connected with the fourth switch S4, and the output end of the AND gate And2 is connected with the fifth switch S5.
Further, the fourth switch S4 is a PMOS transistor, a gate of the PMOS transistor is connected to an output terminal of the Or gate Or2, a source of the PMOS transistor is connected to an output terminal of the upper current source I4, and an input terminal of the upper current source I4 is connected to the operating voltage VDD; the drain of the PMOS transistor is connected to the first input of the voltage comparator.
Further, the fifth switch S5 is an NMOS transistor, a gate of the NMOS transistor is connected to an output end of the And gate nd2, a source of the NMOS transistor is connected to an input end of the lower current source I5, and an output end of the lower current source I5 is grounded; the drain of the NMOS transistor is connected with the first input end of the voltage comparator.
Further, the invention also provides a bidirectional soft switching method of the external clock synchronization and internal clock bidirectional soft switching circuit, which comprises the following specific processes:
when the external clock signal is evacuated, the Clk detection module generates a clk_det=0 signal, the external clock synchronization And internal clock bidirectional soft switching circuit is enabled, and the voltage signal v_lpf input to the voltage comparator starts to be continuously detected And adjusted, specifically, when the voltage signal v_lpf is smaller than Vref, the output result of the voltage comparator controls the conduction of the fourth switch S4 through an Or gate Or2 in the switch control logic circuit, controls the disconnection of the fifth switch S5 through an And gate And2, and the upper current source I4 continuously charges a capacitor low-pass filter LPF hung on the voltage signal v_lpf, so that the voltage signal v_lpf gradually increases And approaches Vref; when the voltage signal V_lpf is larger than Vref, the output result of the voltage comparator controls the disconnection of the fourth switch S4 and the conduction of the fifth switch S5 through the switch control logic circuit, the lower current source I5 continuously discharges the capacitive low-pass filter LPF hung on the voltage signal V_lpf, so that the V_lpf is continuously reduced and approaches Vref;
The final voltage signal V_lpf is regulated back and forth near Vref, the voltage comparator outputs high and low turnover, the voltage comparator is counted by the counting latch, the result is latched after the counting is full, the third switch S3, the fourth switch S4 and the fifth switch S5 are disconnected, the voltage comparator is closed, the sixth switch S6 is conducted, at the moment, the two ends of the voltage control current module Gm are equal, and the frequency of a circuit generated by the PLL & inter_clk module is not changed suddenly;
When the external clock signal is loaded, the Clk detection module generates a clk_det=1 signal, keeps turning off the sixth switch S6, the fourth switch S4, the fifth switch S5, turns off the voltage comparator, clears the latch of the count latch, turns on the third switch S3, and enters the phase-locked loop PLL process of synchronizing the external clock.
Compared with the prior art, the invention has the following beneficial effects: when an external clock signal is switched into an internal clock, the external clock synchronous and internal clock bidirectional soft switching circuit continuously detects and adjusts the input voltage signal V_lpf of the voltage-controlled oscillator VCO to approach the target voltage, realizes stable transition switching between external clock synchronous phase locking and internal clk, adjusts the sizes of the upper current mirror I4 and the lower current mirror I5 through the capacitance of the capacitance low-pass filter LPF, realizes adjustable switching speed and transition area duration of soft switching, can greatly improve abrupt change of the working frequency of a switching power supply chip caused by hard switching, realizes stable change of DC-DC constant voltage or constant current output, and improves the reliability of the switching power supply chip.
Drawings
FIG. 1 is a schematic diagram of a switching power supply chip with a built-in PLL;
FIG. 2 is a schematic diagram of a conventional PLL & Interclk module;
FIG. 3 is a schematic diagram showing abrupt frequency changes caused by external clock synchronization and internal clock hard switching under a conventional PLL & Interclk module;
FIG. 4 is a schematic diagram of a PLL & Interclk module incorporating external clock synchronization and internal clock bi-directional soft switching circuitry according to the present invention;
FIG. 5 is a schematic diagram of an external clock synchronization and internal clock bi-directional soft switching circuit according to the present invention;
FIG. 6 is a schematic diagram of the scheme of the present invention for implementing genlock and internal clk soft handoff;
Fig. 7 is a graph of cadence simulation results for a scheme of the present invention for implementing genlock and internal clk soft handoff.
Detailed Description
The technical scheme of the invention is further explained below with reference to the accompanying drawings.
As shown in fig. 4, the present invention provides an external clock synchronization and internal clock bidirectional soft switching circuit, which is disposed on a PLL & inter_clk module, and includes: the output end of the voltage comparator is connected with the input end of the counting latch and the switch control logic circuit respectively, the output end of the counting latch is connected with the enabling end of the voltage comparator, the output end of the switch control logic circuit is connected with the fourth switch S4 and the fifth switch S5 respectively, the fourth switch S4 is also connected with the upper current source I4, and the fifth switch S5 is also connected with the lower current mirror I5; after the external clock signal is removed, the voltage comparator continuously detects an input voltage signal V_lpf, compares the input voltage signal V_lpf with Vref, and controls the fourth switch S4 to be conducted through the switch control logic circuit if the input voltage signal V_lpf is smaller than Vref, so that the upper current source I4 charges the input voltage signal V_lpf; if the input voltage signal V_lpf is greater than Vref, the switch control logic circuit controls the fifth switch to be turned on, so that the lower circuit source I5 discharges the input voltage signal V_lpf, the soft switching process is realized, and the counting latch is used for recording the times that the input voltage signal V_lpf of the VCO approaches Vref adjustment. According to the invention, the external clock synchronization and the internal clock bidirectional soft switching circuit are used for continuously detecting and adjusting the voltage signal V_lpf input by the VCO, so that the voltage signal V_lpf approaches to the target voltage, the stable transition switching between the external clock synchronous phase lock and the internal clock is realized, the switching speed and the transition region time length are adjustable, the DC-DC constant voltage or constant current output drastic change of the switching power supply caused by the original hard switching is improved, and the reliability of the switching power supply chip is improved.
As in fig. 2, the pll & inter_clk module includes: the device comprises a Clk detection module, a phase frequency detector PFD, a first switch S1, a second switch S2, a first bias current I A, a second bias current I B, a capacitor low-pass filter LPF and a voltage-controlled oscillator VCO, wherein the CLKIN pin of the Clk detection module is used for receiving external clock input, the output end of the Clk detection module is connected with the first input end of the phase frequency detector PFD, the first output end of the phase frequency detector PFD is connected with one end of the first switch S1 and the output end of the first bias current I A in series, the input end of the first bias current I A is connected with an operating voltage VDD, the second output end of the phase frequency detector PFD is connected with one end of the second switch S2, one end of the second switch S2 is also connected with the other end of the first switch S1, the capacitor low-pass filter LPF and the input end of the voltage-controlled oscillator VCO, and the other end of the second switch S2 is connected with the input end of the second bias current I B, and the output end of the second bias current I B is grounded; the output end of the voltage controlled oscillator VCO is connected to the driver in the switching power supply DC-DC, the first input end of the phase frequency detector PFD, respectively. The voltage controlled oscillator VCO comprises: the output end of the voltage control current module Gm is connected with one end of the third switch S3, the other end of the third switch S3 is connected with the input end of the current type relaxation oscillator, and the output end of the current type relaxation oscillator is respectively connected with a driver in a switching power supply DC-DC and the first input end of a phase frequency detector PFD. As shown in fig. 3, the internal clock frequency and the external frequency often differ by several hundred KHz to up MHz, and the hard switching can cause the PLL & inter_clk module to generate frequency abrupt change, so that PWM frequency, constant voltage or constant current output of the driving power MOS transistor can also generate drastic change, which adversely affects the load.
The invention is also provided with a sixth switch S6, wherein the first input end of the voltage comparator is respectively connected with the other end of the first switch S1, one end of the second switch S2, the input end of the capacitive low-pass filter LPF, one end of the sixth switch S6, the first input end of the voltage control current module Gm, the input end of the fourth switch S4 and the output end of the fifth switch S5, and the second input end of the voltage comparator is connected with the other end of the sixth switch S6; the Clk_det signal end of the voltage comparator is connected with the Clk_det signal end of the Clk detection module. The output end of the counting latch is also connected with a third switch S3 and a sixth switch S6 respectively. The counting latch is used for recording the times that the voltage signal V_lpf input by the VCO approaches Vref adjustment, when the external clock is evacuated, the third switch S3 is opened, the sixth switch S6 is closed, the input voltage signal V_lpf is continuously detected, the switch control logic circuit is used for controlling the switch-off of the fourth switch S4 or the fifth switch S5, so that the input voltage signal V_lpf finally approaches Vref, at the moment, because the two ends of the voltage control current module Gm are almost equal, the current flowing out or extracted is 0, and the PLL & inter_clk module generating circuit does not have abrupt frequency change; in addition, the input voltage signal V_lpf is always clamped at Vref, when the subsequent chip is switched from the internal clk operation to the external clock synchronization, the whole PLL loop can be adjusted by taking the input voltage signal V_lpf as a starting point, and the frequency is not changed suddenly during the switching; when the external clock signal is loaded, the sixth switch S6 is opened, the third switch S3 is closed, the phase-locked loop PLL process for synchronizing the external clock is started, and when the voltage signal V_lpf input by the voltage-controlled oscillator VCO approaches Vref, the internal clock is again in soft switching.
The switch control logic circuit of the present invention comprises: the input end of the first inverter Inv1 is connected with the Clk_det signal end of the Clk detection module, the output end of the first inverter Inv1 is respectively connected with the input end of the second inverter Inv2 And the first input end of the AND gate And2, the output end of the second inverter Inv2 is connected with the first input end of the OR gate Or2, the second input end of the OR gate Or2 And the second input end of the AND gate And2 are connected with the output end of the voltage comparator, the output end of the OR gate Or2 is connected with the fourth switch S4, and the output end of the AND gate And2 is connected with the fifth switch S5. The voltage comparator compares the input voltage signal V_lpf with Vref, and the corresponding fourth switch S4 or fifth switch S5 is opened respectively, and the input voltage signal V_lpf is regulated by continuous charge or discharge to finally approach Vref.
In the invention, the fourth switch S4 is a PMOS transistor, the grid electrode of the PMOS transistor is connected with the output end of the OR gate Or2, the source electrode of the PMOS transistor is connected with the output end of the upper current source I4, and the input end of the upper current source I4 is connected with the working voltage VDD; the drain of the PMOS transistor is connected to the first input of the voltage comparator.
In the invention, the fifth switch S5 is an NMOS transistor, the grid electrode of the NMOS transistor is connected with the output end of the AND gate nd2, the source electrode of the NMOS transistor is connected with the input end of the lower current source I5, and the output end of the lower current source I5 is grounded; the drain of the NMOS transistor is connected to the first input of the voltage comparator.
The invention also provides a bidirectional soft switching method of the external clock synchronization and internal clock bidirectional soft switching circuit, which comprises the following specific processes:
When the external clock signal is evacuated, the Clk detection module generates a clk_det=0 signal, the first switch S1 And the second switch S2 are disconnected, the third switch S3 is kept, the external clock synchronization And the internal clock bidirectional soft switching circuit are enabled, the voltage signal v_lpf input to the voltage comparator is continuously detected And regulated, specifically, when the voltage signal v_lpf is smaller than Vref, the output result of the voltage comparator controls the conduction of the fourth switch S4 through an Or gate Or2 in the switch control logic circuit, the fifth switch S5 is controlled to be disconnected through the And gate And2, and the upper current source I4 continuously charges a capacitor low-pass filter LPF hung on the voltage signal v_lpf, so that the voltage signal v_lpf is gradually increased And approaches Vref; when the voltage signal V_lpf is larger than Vref, the output result of the voltage comparator controls the disconnection of the fourth switch S4 and the conduction of the fifth switch S5 through the switch control logic circuit, the lower current source I5 continuously discharges the capacitive low-pass filter LPF hung on the voltage signal V_lpf, so that the V_lpf is continuously reduced and approaches Vref;
The final voltage signal V_lpf is regulated back and forth near Vref, the voltage comparator outputs high and low turnover, the voltage comparator is counted by the counting latch, the result is latched after the counting is full, the third switch S3, the fourth switch S4 and the fifth switch S5 are disconnected, the voltage comparator is closed, the sixth switch S6 is turned on, at the moment, the two ends of the voltage control current module Gm are equal, the current flowing out or extracted is 0, the current is thoroughly switched to an internal clock signal generated by the internal second bias current Ib, the starting point of phase locking synchronization is the internal clock frequency, and the starting point is continuously approaching and synchronizing the external clock signal, so that the circuit generated by the PLL & Inter_clk module does not have abrupt frequency change;
When the external clock signal is loaded, the Clk detection module generates a clk_det=1 signal, turns off the sixth switch S6, keeps turning off the sixth switch S6, the fourth switch S4, the fifth switch S5, turns off the voltage comparator, clears the latch of the count latch, turns on the third switch S3, and enters the phase-locked loop PLL process of synchronizing the external clock.
The invention successfully realizes the bidirectional soft switching between the synchronous phase lock and the internal clk soft switching, continuously detects and adjusts the voltage signal V_lpf input by the VCO in the switching process, realizes the stable transition switching between the external clock synchronous phase lock and the internal clk, can adjust the sizes of the upper current source I4 and the lower current source I5 according to the size of the capacitance of the LPF, realizes the controllable length of the soft switching transition region time, can greatly improve the abrupt change of the chip working frequency caused by hard switching, has the effect schematic diagram shown in figure 6, and finally can adjust the switching speed and the transition region duration according to the actual measurement result, realize the stable change of DC-DC constant voltage or constant current output of the switching power supply and improve the reliability of the DC-DC of the switching power supply.
The above is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above embodiment, and all technical solutions belonging to the concept of the present invention are within the scope of the present invention. It should be noted that modifications and adaptations to the invention without departing from the principles thereof are intended to be within the scope of the invention as set forth in the following claims.
Claims (6)
1. An external clock synchronization and internal clock bidirectional soft switching circuit, which is arranged on a PLL & inter_clk module, comprising: the output end of the voltage comparator is connected with the input end of the counting latch and the switch control logic circuit respectively, the output end of the counting latch is connected with the enabling end of the voltage comparator, the output end of the switch control logic circuit is connected with the fourth switch S4 and the fifth switch S5 respectively, the fourth switch S4 is also connected with the upper current source I4, and the fifth switch S5 is also connected with the lower current mirror I5;
after the external clock signal is removed, the voltage comparator continuously detects an input voltage signal V_lpf, compares the input voltage signal V_lpf with Vref, and controls the fourth switch S4 to be conducted through the switch control logic circuit if the input voltage signal V_lpf is smaller than Vref, so that the upper current source I4 charges the input voltage signal V_lpf; if the input voltage signal V_lpf is more than Vref, the switch control logic circuit controls the fifth switch to be turned on, so that the lower circuit source I5 discharges the input voltage signal V_lpf, and a soft switching process is realized;
the counting latch is used for recording the times that the voltage signal V_lpf input by the VCO approaches Vref adjustment;
The PLL & inter_clk module includes: the device comprises a Clk detection module, a phase frequency detector PFD, a first switch S1, a second switch S2, a first bias current I A, a second bias current I B, a capacitive low-pass filter LPF and a voltage-controlled oscillator VCO, wherein the CLKIN pin of the Clk detection module is used for receiving external clock input, the output end of the Clk detection module is connected with the first input end of the phase frequency detector PFD, the first output end of the phase frequency detector PFD is connected with one end of the first switch S1 and the output end of the first bias current I A in series, the input end of the first bias current I A is connected with an operating voltage VDD, the second output end of the phase frequency detector PFD is connected with one end of the second switch S2, one end of the second switch S2 is also connected with the other end of the first switch S1, the capacitive low-pass filter LPF and the input end of the voltage-controlled oscillator VCO, the other end of the second switch S2 is connected with the input end of the second bias current I B, and the output end of the second bias current I B is grounded; the output end of the voltage controlled oscillator VCO is respectively connected with a driver in the DC-DC of the switching power supply and the first input end of the phase frequency detector PFD;
The voltage controlled oscillator VCO comprises: the voltage control current module Gm, the third switch S3 and the current-type relaxation oscillator, wherein the output end of the voltage control current module Gm is connected with one end of the third switch S3, the other end of the third switch S3 is connected with the input end of the current-type relaxation oscillator, and the output end of the current-type relaxation oscillator is used as the output end of the voltage control oscillator VCO and is respectively connected with a driver in a switching power supply DC-DC and the first input end of the phase frequency detector PFD;
The voltage comparator is further provided with a sixth switch S6, a first input end of the voltage comparator is respectively connected with the other end of the first switch S1, one end of the second switch S2, an input end of the capacitive low-pass filter LPF, one end of the sixth switch S6, a first input end of the voltage control current module Gm, an input end of the fourth switch S4 and an output end of the fifth switch S5, and a second input end of the voltage comparator is connected with the other end of the sixth switch S6; the Clk_det signal end of the voltage comparator is connected with the Clk_det signal end of the Clk detection module;
the output end of the counting latch is also connected with a third switch S3 and a sixth switch S6 respectively.
2. The external clock synchronization and internal clock bi-directional soft switching circuit of claim 1, wherein said switch control logic circuit comprises: the input end of the first inverter Inv1 is connected with the Clk_det signal end of the Clk detection module, the output end of the first inverter Inv1 is respectively connected with the input end of the second inverter Inv2 And the first input end of the AND gate And2, the output end of the second inverter Inv2 is connected with the first input end of the OR gate Or2, the second input end of the OR gate Or2 And the second input end of the AND gate And2 are connected with the output end of the voltage comparator, the output end of the OR gate Or2 is connected with the fourth switch S4, and the output end of the AND gate And2 is connected with the fifth switch S5.
3. The bidirectional soft switching circuit of external clock synchronization and internal clock according to claim 2, wherein the fourth switch S4 is a PMOS transistor, a gate of the PMOS transistor is connected to an output terminal of the Or gate Or2, a source of the PMOS transistor is connected to an output terminal of the upper current source I4, and an input terminal of the upper current source I4 is connected to the operating voltage VDD; the drain of the PMOS transistor is connected to the first input of the voltage comparator.
4. The external clock synchronization And internal clock bidirectional soft switching circuit according to claim 3, wherein the fifth switch S5 is an NMOS transistor, a gate of the NMOS transistor is connected to an output terminal of the And gate nd2, a source of the NMOS transistor is connected to an input terminal of the lower current source I5, and an output terminal of the lower current source I5 is grounded; the drain of the NMOS transistor is connected with the first input end of the voltage comparator.
5. A bi-directional soft switching method of an external clock synchronization and internal clock bi-directional soft switching circuit according to any one of claims 1-4, characterized by the following specific procedures:
When the external clock signal is evacuated, the Clk detection module generates a clk_det=0 signal, the external clock synchronization and internal clock bidirectional soft switching circuit is enabled, the voltage signal V_lpf input into the voltage comparator starts to be continuously detected and adjusted, the final voltage signal V_lpf is adjusted back and forth nearby Vref, the voltage comparator outputs high and low turnover and is counted by the counting latch, the result is latched after the counting is full, the third switch S3, the fourth switch S4 and the fifth switch S5 are disconnected, the voltage comparator is closed, the sixth switch S6 is turned on, at the moment, the two ends of the voltage control current module Gm are equal, and the circuit generated by the PLL & inter_clk module does not have abrupt frequency change;
When the external clock signal is loaded, the Clk detection module generates a clk_det=1 signal, keeps turning off the sixth switch S6, the fourth switch S4, the fifth switch S5, turns off the voltage comparator, clears the latch of the count latch, turns on the third switch S3, and enters the phase-locked loop PLL process of synchronizing the external clock.
6. The bidirectional soft switching method of the external clock synchronization And internal clock bidirectional soft switching circuit according to claim 5, wherein when the voltage signal v_lpf < Vref of the input voltage comparator is detected, the output result of the voltage comparator controls the turn-on of the fourth switch S4 through the Or gate Or2 in the switch control logic circuit, and controls the turn-off of the fifth switch S5 through the And gate nd2, the upper current source I4 continuously charges the capacitive low pass filter LPF hanging on the voltage signal v_lpf, so that the voltage signal v_lpf gradually increases And approaches Vref;
When the voltage signal V_lpf > Vref input to the voltage comparator is detected, the output result of the voltage comparator controls the disconnection of the fourth switch S4 and the conduction of the fifth switch S5 through the switch control logic circuit, and the lower current source I5 continuously discharges the capacitor low-pass filter LPF hung on the voltage signal V_lpf, so that the V_lpf is continuously reduced and approaches Vref.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410167729.1A CN118041349B (en) | 2024-02-06 | 2024-02-06 | External clock synchronization and internal clock bidirectional soft switching circuit and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410167729.1A CN118041349B (en) | 2024-02-06 | 2024-02-06 | External clock synchronization and internal clock bidirectional soft switching circuit and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118041349A CN118041349A (en) | 2024-05-14 |
| CN118041349B true CN118041349B (en) | 2024-08-23 |
Family
ID=90983610
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410167729.1A Active CN118041349B (en) | 2024-02-06 | 2024-02-06 | External clock synchronization and internal clock bidirectional soft switching circuit and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118041349B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111510130A (en) * | 2020-05-15 | 2020-08-07 | 电子科技大学 | Phase-locked loop circuit capable of being used for synchronizing switching frequency of COT mode switching power supply |
| CN114465620A (en) * | 2020-11-10 | 2022-05-10 | 圣邦微电子（北京）股份有限公司 | Switch converter and clock synchronization circuit thereof |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3790076B2 (en) * | 1999-11-15 | 2006-06-28 | 株式会社東芝 | Analog synchronous circuit |
| KR100510519B1 (en) * | 2003-02-05 | 2005-08-26 | 삼성전자주식회사 | Phase locked loop with elevated phase lock/unlock detecting function |
| US6828830B2 (en) * | 2003-02-20 | 2004-12-07 | Intersil Americas, Inc. | Low power, area-efficient circuit to provide clock synchronization |
| JP2005252934A (en) * | 2004-03-08 | 2005-09-15 | Matsushita Electric Ind Co Ltd | Pll circuit |
| CN100338967C (en) * | 2005-05-19 | 2007-09-19 | 北京北方烽火科技有限公司 | Method and apparatus for realizing clock redundancy back-up in WCDMA system base station |
| US10459467B1 (en) * | 2018-07-05 | 2019-10-29 | Fci Inc. | Switching regulator with soft start circuit and operation method thereof |
| CN110635803B (en) * | 2019-10-07 | 2024-06-14 | 珠海一微半导体股份有限公司 | Phase-locked acceleration circuit and phase-locked loop system based on level width extraction |
-
2024
- 2024-02-06 CN CN202410167729.1A patent/CN118041349B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111510130A (en) * | 2020-05-15 | 2020-08-07 | 电子科技大学 | Phase-locked loop circuit capable of being used for synchronizing switching frequency of COT mode switching power supply |
| CN114465620A (en) * | 2020-11-10 | 2022-05-10 | 圣邦微电子（北京）股份有限公司 | Switch converter and clock synchronization circuit thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN118041349A (en) | 2024-05-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6586976B2 (en) | Charge pump circuit for improving switching characteristics and reducing leakage current and phase locked loop having the same | |
| US7622996B2 (en) | Multi-loop phase locked loop circuit | |
| US6960949B2 (en) | Charge pump circuit and PLL circuit using same | |
| CN109660253B (en) | Digital amplitude controlled voltage controlled oscillator | |
| US20090033429A1 (en) | Phase locked loop for stably operating in a matter that is insensitive to variation in process, voltage and temperature and method of operating the same | |
| JPH07202690A (en) | Clock signal generation circuit | |
| CN110474634B (en) | Fast locking phase-locked loop circuit capable of avoiding cycle slip | |
| US20140049329A1 (en) | Divider-less phase locked loop (pll) | |
| JPWO2007029428A1 (en) | PLL circuit | |
| CN210899136U (en) | Phase-locked loop circuit, chip, circuit board and electronic equipment | |
| CN109921790B (en) | Quick start circuit, self-adaptive phase-locked loop and quick start method | |
| US20100207673A1 (en) | Asymmetric charge pump and phase locked loops having the same | |
| US6873670B1 (en) | Automatic pre-scaler control for a phase-locked loop | |
| US7511580B2 (en) | Charge pump circuit with dynamic current biasing for phase locked loop | |
| CN118041349B (en) | External clock synchronization and internal clock bidirectional soft switching circuit and method | |
| US7791420B2 (en) | Phase-locked loop with start-up circuit | |
| US7576578B2 (en) | Frequency synthesizer and charge pump circuit used for the same | |
| CN112737508B (en) | Clock circuit and chip circuit | |
| US10992306B1 (en) | Oscillation circuit and a self-start-up control circuit adaptable thereto | |
| US9257899B1 (en) | Charge pump circuit and phase lock loop circuit having the same | |
| US7605663B2 (en) | Method and apparatus for stabilizing output frequency of PLL (phase lock loop) and phase lock loop thereof | |
| CN111835344A (en) | Phase-locked loop circuit and terminal | |
| US7449962B2 (en) | Phase-controlled current source for phase-locked loop | |
| CN113452367B (en) | Oscillator circuit and self-starting control circuit | |
| TWI657664B (en) | Two-steps switching method of circuit switch |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |