CN116230798A - A kind of high-efficiency heterojunction solar cell and its manufacturing method - Google Patents

Abstract

The invention relates to a method for manufacturing a high-efficiency heterojunction solar cell, which comprises forming a first semiconductor film layer with N-type doping or P-type doping on the first passivation layer of a passivated semiconductor substrate, The specific steps are as follows, step A, forming a first microcrystalline silicon stack on the first passivation layer of the passivated semiconductor substrate; step B, forming a first amorphous silicon stack on the first microcrystalline silicon stack layer. The purpose of the present invention is to provide a high-efficiency heterojunction solar cell and its manufacturing method, by using the N-type semiconductor film layer or/and P-type semiconductor film layer combined with the microcrystalline silicon layer and the amorphous silicon layer, the battery can be improved at the same time. Due to the influence of short-circuit current, open-circuit voltage and fill factor, the battery efficiency can be significantly improved.

Description

A high-efficiency heterojunction solar cell and a method for manufacturing the same

Technical Field

The invention relates to a high-efficiency heterojunction solar cell and a manufacturing method thereof.

Background Art

The preparation process of heterojunction solar cells is simple, with low process temperature, and the product has the advantages of high power generation, high stability, no attenuation and low cost. With the continuous technological progress and policy promotion in the industry, the cost-effectiveness advantage of heterojunction batteries is emerging, and it is possible to replace crystalline silicon solar cells and become the next generation of mainstream photovoltaic cells.

Traditional heterojunction solar cells use N-type monocrystalline silicon wafers as substrates, intrinsic I-layer amorphous silicon passivates the crystalline silicon surface, boron-doped P-type amorphous silicon film is used as the emission layer, and phosphorus-doped N-type amorphous silicon film forms the back field; as a core process technology, it is crucial to the efficiency of heterojunction solar cells; compared with doped amorphous silicon film, doped microcrystalline silicon film has the advantages of higher doping efficiency, higher conductivity and lower light absorption, and its application in heterojunction cells is expected to further improve the efficiency of cells. However, the higher barrier height between the microcrystalline silicon layer and the TCO film reduces the open circuit voltage of the cell, and also increases the series resistance of the cell. The increase in series resistance will lead to a decrease in the conversion efficiency of the cell.

Summary of the invention

The purpose of the present invention is to provide a high-efficiency heterojunction solar cell and a method for manufacturing the same. By using an N-type semiconductor film layer or/and a P-type semiconductor film layer composed of a microcrystalline silicon stack and an amorphous silicon layer, the short-circuit current, open-circuit voltage and fill factor of the battery can be improved simultaneously, thereby significantly improving the battery efficiency.

The purpose of the present invention is achieved through the following technical solutions:

A high-efficiency heterojunction solar cell comprises a semiconductor substrate, a first passivation layer arranged on a first main surface of the semiconductor substrate, and a first semiconductor film layer arranged on the first passivation layer and having N-type doping or P-type doping; the first semiconductor film layer comprises a first microcrystalline silicon stack arranged on the first passivation layer and a first amorphous silicon layer arranged on the first microcrystalline silicon stack and having the same conductive type doping as the first microcrystalline silicon stack.

A method for manufacturing a high-efficiency heterojunction solar cell includes forming a first semiconductor film layer with N-type doping or P-type doping on a first passivation layer of a semiconductor substrate that has been passivated. The specific steps are as follows:

Step A, forming a first microcrystalline silicon stack on the first passivation layer of the semiconductor substrate that has been passivated;

Step B: forming a first amorphous silicon layer on the first microcrystalline silicon stack.

Compared with the prior art, the advantages of the present invention are:

By designing the doped semiconductor film layer as a composite layer structure, on the one hand, the microcrystalline silicon stack is used to improve the thin film optical band gap and doping efficiency so that the battery can obtain high short-circuit current and open-circuit voltage; on the other hand, good contact is formed between the thin doped amorphous silicon layer and the conductive film layer to reduce the series resistance, improve the battery's fill factor, and enable the battery to obtain high conversion efficiency.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic structural diagram of an embodiment of a high-efficiency heterojunction solar cell provided by the present invention.

FIG. 2 is a schematic structural diagram of an implementation scheme of a high-efficiency heterojunction solar cell provided by the present invention.

FIG3 is a schematic structural diagram of an implementation scheme of a high-efficiency heterojunction solar cell provided by the present invention.

FIG4 is a flow chart of a method for manufacturing a high-efficiency heterojunction solar cell provided by the present invention.

FIG5 is a schematic structural diagram of an implementation scheme of a high-efficiency heterojunction solar cell provided by the present invention.

DETAILED DESCRIPTION

A high-efficiency heterojunction solar cell comprises a semiconductor substrate, a first passivation layer arranged on a first main surface of the semiconductor substrate, and a first semiconductor film layer arranged on the first passivation layer and having N-type doping or P-type doping; the first semiconductor film layer comprises a first microcrystalline silicon stack arranged on the first passivation layer and a first amorphous silicon layer arranged on the first microcrystalline silicon stack and having the same conductive type doping as the first microcrystalline silicon stack.

The first microcrystalline silicon stack includes a first microcrystalline silicon seed layer, a first microcrystalline silicon oxide layer with N-type doping or P-type doping, and a first microcrystalline silicon layer with the same conductive type doping as the first microcrystalline silicon oxide layer, which are sequentially arranged from bottom to top with the first passivation layer as the substrate.

When the first semiconductor film layer is N-type doped, the thickness of the first microcrystalline silicon seed layer is 1-4 nm, the thickness of the first microcrystalline silicon oxide layer is 4-8 nm, the thickness of the first microcrystalline silicon layer is 1-4 nm, and the thickness of the first amorphous silicon layer is 1-4 nm;

When the first semiconductor film layer is P-type doped, the thickness of the first microcrystalline silicon seed layer is 1-4 nm, the thickness of the first microcrystalline silicon oxide layer is 2-6 nm, the thickness of the first microcrystalline silicon layer is 8-20 nm, and the thickness of the first amorphous silicon layer is 1-4 nm.

In a specific embodiment, the high-efficiency heterojunction solar cell also includes a second passivation layer arranged on the second main surface of the semiconductor substrate and a second semiconductor film layer arranged on the second passivation layer and having a conductivity type doping different from that of the first semiconductor film layer; the second semiconductor film layer includes a second microcrystalline silicon stack arranged on the second passivation layer and a second amorphous silicon layer arranged on the second microcrystalline silicon stack and having the same conductivity type doping as the second microcrystalline silicon stack.

In a specific embodiment, the first passivation layer is only provided on a portion of the first main surface of the semiconductor substrate; a second passivation layer is provided on the first main surface not covering the first passivation layer, and a second semiconductor film layer is provided on the second passivation layer and has a different conductivity type doping from the first semiconductor film layer; the second semiconductor film layer includes a second microcrystalline silicon stack provided on the second passivation layer and a second amorphous silicon layer is provided on the second microcrystalline silicon stack and has the same conductivity type doping as the second microcrystalline silicon stack.

A method for manufacturing a high-efficiency heterojunction solar cell includes forming a first semiconductor film layer with N-type doping or P-type doping on a first passivation layer of a semiconductor substrate that has been passivated. The specific steps are as follows:

Step A, forming a first microcrystalline silicon stack on the first passivation layer of the semiconductor substrate that has been passivated;

Step B: forming a first amorphous silicon layer on the first microcrystalline silicon stack.

The specific procedures of step A are: a1, depositing a first microcrystalline silicon seed layer on the first passivation layer of the semiconductor substrate that has been passivated; a2, depositing a first microcrystalline silicon oxide layer with N-type doping or P-type doping on the first microcrystalline silicon seed layer; a3, depositing a first microcrystalline silicon layer with the same conductive type doping as the first microcrystalline silicon oxide layer on the first microcrystalline silicon oxide layer.

The specific method of step a1 is to first preset the PECVD film forming temperature to 150-250° C., and then introduce a mixed gas of silane and hydrogen with a reaction gas pressure of 100-300 Pa to deposit a first microcrystalline silicon seed layer.

When preparing the N-type doped first semiconductor film layer, the specific method of step a2 is to first preset the PECVD film forming temperature to 150-250° C., then introduce a mixed gas of silane, phosphine, hydrogen and carbon dioxide, the reaction gas pressure is 150-500 Pa, the ratio of phosphine to silane is 1%-10%, and the ratio of carbon dioxide to silane is 50%-100%, so as to deposit the N-type first microcrystalline silicon oxide layer;

When preparing a P-type doped first semiconductor film layer, the specific method of step a2 is to first preset the PECVD film forming temperature to 150-250°C, and then introduce a mixed gas of silane, diborane, hydrogen and carbon dioxide, with a reaction gas pressure of 150-500Pa, a ratio of diborane to silane of 0.5%-4%, and a ratio of carbon dioxide to silane of 50%-100%, to deposit a P-type first microcrystalline silicon oxide layer.

When preparing the N-type doped first semiconductor film layer, the specific method of step a3 is to first preset the PECVD film forming temperature to 150-250°C, then introduce a mixed gas of silane, phosphine and hydrogen, the reaction gas pressure is 150-500Pa, the deposition power density is 0.08-0.3W/cm ² , and the ratio of phosphine to silane is 1%-10%, so as to deposit the N-type first microcrystalline silicon layer;

When preparing the P-type doped first semiconductor film layer, the specific method of step a3 is to first preset the PECVD film forming temperature to 150-250°C, then introduce a mixed gas of silane, diborane and hydrogen, the reaction gas pressure is 150-500Pa, the deposition power density is 0.1-0.5W/ ^cm2 , and the ratio of diborane to silane is 0.5%-4%, so as to deposit the P-type first microcrystalline silicon layer.

When preparing the N-type doped first semiconductor film layer, the specific method of step B is to first preset the PECVD film forming temperature to 150-250°C, then introduce a mixed gas of silane, phosphine and hydrogen, the reaction gas pressure is 30-150Pa, the deposition power density is 0.01-0.02W/cm ² , and the ratio of phosphine to silane is 1%-10%, so as to deposit the N-type first amorphous silicon layer;

When preparing the P-type doped first semiconductor film layer, the specific method of step B is to first preset the PECVD film forming temperature to 150-250°C, then introduce a mixed gas of silane, diborane and hydrogen, the reaction gas pressure is 30-150Pa, the deposition power density is 0.01-0.02W/ ^cm2 , and the ratio of diborane to silane is 1%-10%, so as to deposit the P-type first amorphous silicon layer.

In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

As shown in FIG1 , a high-efficiency heterojunction solar cell provided by the present invention comprises: an N-type silicon wafer 10, a first intrinsic amorphous silicon layer 20 (i.e., a first passivation layer), an N-type semiconductor film layer 30 (i.e., a first semiconductor film layer), a front transparent conductive layer 60-1, and a front metal grid line 70-1, which are sequentially arranged on the front side of the silicon wafer 10, and a second intrinsic amorphous silicon layer 40 (i.e., a second passivation layer), a P-type semiconductor film layer 50 (i.e., a second semiconductor film layer), a back transparent conductive layer 60-2, and a back metal grid line 70-2, which are sequentially arranged on the back side of the silicon wafer 10. The N-type semiconductor film layer 30 and/or the P-type semiconductor film layer 50 are a multi-layer composite structure, wherein the N-type semiconductor film layer 30 includes an N-face microcrystalline silicon seed layer 31, an N-type microcrystalline silicon oxide layer 32, an N-type microcrystalline silicon layer 33, and an N-type amorphous silicon layer 34; the P-type semiconductor film layer 50 includes a P-face microcrystalline silicon seed layer 51, a P-type microcrystalline silicon oxide layer 52, a P-type microcrystalline silicon layer 53, and a P-type amorphous silicon layer 54.

The N-type silicon wafer is a single crystal silicon wafer or a polycrystalline silicon wafer.

The thickness of the N-side microcrystalline silicon seed layer 31 is 1-4 nm; the thickness of the N-type microcrystalline silicon oxide layer 32 is 4-8 nm; the thickness of the N-type microcrystalline silicon layer 33 is 1-4 nm; and the thickness of the N-type amorphous silicon layer 34 is 1-4 nm.

The thickness of the P-face microcrystalline silicon seed layer 51 is 1-4 nm; the thickness of the P-type microcrystalline silicon oxide layer 52 is 2-6 nm; the thickness of the P-type microcrystalline silicon layer 53 is 8-20 nm; and the thickness of the P-type amorphous silicon layer 54 is 1-4 nm.

In another embodiment, as shown in FIG. 5 , a back-contact heterojunction solar cell (HBC) comprises an N-type single crystal silicon wafer 80, a third intrinsic amorphous silicon layer 97 and an anti-reflection layer 98 sequentially stacked on the front side of the silicon wafer 80, a P-region intrinsic amorphous silicon layer 81 (i.e., a first passivation layer), a P-region semiconductor film layer (i.e., a first semiconductor film layer, including a P-region microcrystalline silicon seed layer 82, a P-type microcrystalline silicon oxide layer 83, P-type microcrystalline silicon layer 84, P-type amorphous silicon layer 85), P-region transparent conductive film layer 93, P-region metal gate line 94, N-region intrinsic amorphous silicon layer 87 (i.e., second passivation layer), N-region semiconductor film layer (i.e., second semiconductor film layer, including N-region microcrystalline silicon seed layer 88, N-type microcrystalline silicon oxide layer 89, N-type microcrystalline silicon layer 90, N-type amorphous silicon layer 91), N-region transparent conductive layer 92, N-region metal gate line 95 are sequentially stacked on the N-region surface on the back side of the silicon wafer. At the junction of the N-region and the P-region, the N-region intrinsic amorphous silicon layer 87 (i.e., second passivation layer) and the N-region semiconductor film layer are stacked on the P-region semiconductor film layer through the insulating film layer 86, and an insulating groove 96 is provided between the P-region transparent conductive film layer 93 and the N-region transparent conductive layer 92 for separation.

As shown in FIGS. 1 and 4 , the method for manufacturing a high-efficiency heterojunction solar cell comprises the following steps:

S01, provide N-type silicon wafers that have been cleaned and textured;

S02, depositing a second intrinsic amorphous silicon layer on the back side of the silicon wafer by PECVD;

S03, depositing a first intrinsic amorphous silicon layer on the front side of the silicon wafer by PECVD;

S04, depositing an N-type semiconductor film layer on the first intrinsic amorphous silicon layer on the front side of the silicon wafer by PECVD; specifically, depositing an N-type doped layer or sequentially depositing an N-surface seed layer, an N-type microcrystalline silicon oxide layer, an N-type microcrystalline silicon layer, and an N-type amorphous silicon layer to form an N-type semiconductor film layer 30 with a multi-layer composite structure;

S05, depositing a P-type semiconductor film layer on the second intrinsic amorphous silicon layer on the back side of the silicon wafer by PECVD; specifically, depositing a P-type doped layer or sequentially depositing a P-side microcrystalline silicon seed layer, a P-type microcrystalline silicon oxide layer, a P-type microcrystalline silicon layer, and a P-type amorphous silicon layer to form a P-type semiconductor film layer 50 with a multi-layer composite structure;

S06, depositing a front transparent conductive layer 60-1 on the silicon wafer and a back transparent conductive layer 60-2 on the back of the silicon wafer by PVD magnetron sputtering;

S07, forming a front metal gate line 70-1 and a back metal gate line 70-2 on the front and back sides of the silicon wafer respectively;

The process of depositing the N-side microcrystalline silicon seed layer in step S04 and the process of depositing the P-side microcrystalline silicon seed layer in step S05 is to introduce a mixed gas of silane and hydrogen, and the reaction gas pressure is 100-300Pa.

The process of depositing the N-type microcrystalline silicon oxide layer in step S04 is to introduce a mixed gas of silane, phosphine, hydrogen and carbon dioxide, the reaction gas pressure is 150-500 Pa, the ratio of phosphine to silane is 1%-10%, and the ratio of carbon dioxide to silane is 50%-100%.

The process of depositing the N-type microcrystalline silicon layer in step S04 is to introduce a mixed gas of silane, phosphine and hydrogen, the reaction gas pressure is 150-500 Pa, the deposition power density is 0.08-0.3 W/cm ² , and the ratio of phosphine to silane is 1%-10%;

The process of depositing the N-type amorphous silicon layer in step S04 is to introduce a mixed gas of silane, phosphine and hydrogen, the reaction gas pressure is 30-150 Pa, the deposition power density is 0.01-0.02 W/cm ² , and the ratio of phosphine to silane is 1%-10%.

The preset film forming temperature of PECVD in step S04 is 150-250°C.

The process of depositing the P-type microcrystalline silicon oxide layer in step S05 is to first preset the PECVD film forming temperature to 150-250°C, then introduce a mixed gas of silane, diborane, hydrogen and carbon dioxide, the reaction gas pressure is 150-500Pa, the ratio of diborane to silane is 0.5%-4%, and the ratio of carbon dioxide to silane is 50%-100%.

The process of depositing the P-type microcrystalline silicon layer in step S05 is to preset the PECVD film forming temperature to 150-250°C, then introduce a mixed gas of silane, diborane and hydrogen, the reaction gas pressure to 150-500Pa, the deposition power density to 0.1-0.5W/ ^cm2 , and the ratio of diborane to silane to 0.5%-4%.

In the process of depositing the P-type amorphous silicon layer in step S05, a mixed gas of silane, diborane and hydrogen is introduced, the reaction gas pressure is 30-150 Pa, the deposition power density is 0.01-0.02 W/cm ² , and the ratio of diborane to silane is 1%-10%.

Example 1

A method for manufacturing a high-efficiency heterojunction solar cell (as shown in FIG1 ), the specific process may be as follows:

S01, providing a cleaned N-type silicon wafer 10; the specific process is to form a pyramid texture surface on the surface of the N-type silicon wafer 10 by a texture cleaning method and keep it clean; the N-type silicon wafer 10 is a single crystal silicon wafer.

S02, depositing a second intrinsic amorphous silicon layer 40 on the back side of the silicon wafer 10 treated in S01 by PECVD; the specific process is to introduce silane and hydrogen into the reaction chamber; the preset film forming temperature is 150-250°C; the reaction gas pressure is 30-150Pa; the deposition thickness is 5-10nm.

S03, depositing a first intrinsic amorphous silicon layer 20 on the front side of the silicon wafer 10 treated by S02 by PECVD; the specific process is to introduce silane and hydrogen into the reaction chamber; the preset film forming temperature is 150-250°C; the reaction gas pressure is 30-150Pa; the deposition thickness is 4-7nm.

S04, depositing an N-face microcrystalline silicon seed layer 31, an N-type microcrystalline silicon oxide layer 32, an N-type microcrystalline silicon layer 33 and an N-type amorphous silicon layer 34 in sequence on the first intrinsic amorphous silicon layer 20 on the front side of the silicon wafer 10 treated by S03 by PECVD to form a multi-layer composite structure N-type doped layer; the specific process is as follows: the preset film forming temperature is 150-250°C; firstly, a mixed gas of silane and hydrogen is introduced into the reaction chamber, and the reaction gas pressure is 100-300Pa, and the first layer is deposited as the N-face microcrystalline silicon seed layer 31, and the thickness thereof is 1-4nm; then, silane and phosphorus are introduced into the reaction chamber. A mixed gas of silane, hydrogen and carbon dioxide is introduced into the reaction chamber, the ratio of phosphine to silane is 1%-10%, the ratio of carbon dioxide to silane is 50%-100%, and the reaction gas pressure is 150-500Pa, and the second layer is deposited as an N-type microcrystalline silicon oxide layer 32, and the thickness thereof is 4-8nm; finally, a mixed gas of silane, phosphine and hydrogen is introduced into the reaction chamber, the ratio of phosphine to silane is 1%-10%, and the reaction gas pressure is 150-500Pa, and the third layer is deposited as an N-type microcrystalline silicon layer 33, and the thickness thereof is 1-4nm; and the fourth layer is deposited as an N-type amorphous silicon layer 34, and the thickness thereof is 1-4nm;

S05, depositing a P-face microcrystalline silicon seed layer 51, a P-type microcrystalline silicon oxide layer 52, a P-type microcrystalline silicon layer 53 and a P-type amorphous silicon layer 54 on the back side of the silicon wafer 10 treated by S04 by PECVD to form a multi-layer composite structure P-type doped layer; the specific process is as follows: the preset film forming temperature is 150-250°C; firstly, a mixed gas of silane and hydrogen is introduced into the reaction chamber, and the reaction gas pressure is 100-300Pa, and the first layer is deposited as the P-face microcrystalline silicon seed layer 51, and the thickness thereof is 1-4nm; then, silane, diborane and hydrogen are introduced into the reaction chamber to form a P-face microcrystalline silicon seed layer 51, and the thickness thereof is 1-4nm; then, silane, diborane and hydrogen are introduced into the reaction chamber to form a P-face microcrystalline silicon seed layer 51, and the thickness thereof is 1-4nm; and carbon dioxide, the ratio of diborane to silane is 0.5%-4%, the ratio of carbon dioxide to silane is 50%-100%, the reaction gas pressure is 150-500Pa, and the second layer is deposited as a P-type microcrystalline silicon oxide layer 52, whose thickness is 2-6nm; finally, a mixed gas of silane, diborane and hydrogen is introduced into the reaction chamber, the ratio of diborane to silane is 0.5%-4%, the reaction gas pressure is 150-500Pa, and the third layer is deposited as a P-type microcrystalline silicon layer 53, whose thickness is 8-20nm; the fourth layer is deposited as a P-type amorphous silicon layer 54, whose thickness is 1-4nm;

S06, depositing a front transparent conductive layer 60-1 (ITO) by PVD magnetron sputtering on the front side of the silicon wafer 10 processed by S05, and depositing a back transparent conductive layer 60-2 (ITO) by PVD magnetron sputtering on the back side of the silicon wafer 10 of S05; the deposition thickness is 90-110nm.

S07, forming a front metal grid line 70-1 (silver grid) on the front transparent conductive layer 60-1 of the silicon wafer 10 processed by S06 by screen printing, and forming a back metal grid line 70-2 (silver grid) on the back transparent conductive layer 60-2 of the silicon wafer 10 by screen printing.

Example 2

A method for manufacturing a high-efficiency heterojunction solar cell (as shown in FIG2 ), the specific process differs from that of Example 1 only in that:

S05, depositing a P-type semiconductor film layer 50 on the second intrinsic amorphous silicon layer 40 on the back side of the silicon wafer treated by S04 by PECVD; the specific process is to introduce diborane, silane and hydrogen into the reaction chamber; the preset film forming temperature is 150-250°C; the reaction gas pressure is 30-150Pa; the deposition thickness is 6-14nm.

Example 3

A method for manufacturing a high-efficiency heterojunction solar cell (as shown in FIG3 ), the specific process differs from that of Example 1 only in that:

S04, depositing an N-type semiconductor film layer 30 on the first intrinsic amorphous silicon layer 20 on the front side of the silicon wafer treated by S03 by PECVD; the specific process is to introduce phosphine, silane and hydrogen into the reaction chamber; the preset film forming temperature is 150-250°C; the reaction gas pressure is 30-150Pa; the deposition thickness is 4-7nm.

Table 1 lists the efficiency comparison between the heterojunction solar cell provided by the present invention and the conventional heterojunction solar cell. The results show that the heterojunction solar cell provided by the present invention has better electrical performance, as shown below:

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Claims (11)

1. the utility model provides a high-efficient heterojunction solar cell which characterized in that: the semiconductor device comprises a semiconductor substrate, a first passivation layer arranged on a first main surface of the semiconductor substrate, and a first semiconductor film layer which is arranged on the first passivation layer and has N-type doping or P-type doping; the first semiconductor film layer comprises a first microcrystalline silicon lamination layer arranged on the first passivation layer and a first amorphous silicon layer which is arranged on the first microcrystalline silicon lamination layer and has the same conductive type doping as the first microcrystalline silicon lamination layer.

2. The high efficiency heterojunction solar cell of claim 1, wherein: the first microcrystalline silicon lamination comprises a first microcrystalline silicon seed layer, a first microcrystalline silicon oxide layer with N-type doping or P-type doping and a first microcrystalline silicon layer with the same conductive type doping as the first microcrystalline silicon oxide layer, which are sequentially arranged from bottom to top by taking the first passivation layer as a substrate.

3. The high efficiency heterojunction solar cell of claim 2, wherein: when the first semiconductor film layer is doped in an N type, the thickness of the first microcrystalline silicon seed layer is 1-4nm, the thickness of the first microcrystalline silicon oxide layer is 4-8nm, the thickness of the first microcrystalline silicon layer is 1-4nm, and the thickness of the first amorphous silicon layer is 1-4nm;

when the first semiconductor film layer is doped in a P type, the thickness of the first microcrystalline silicon seed layer is 1-4nm, the thickness of the first microcrystalline silicon oxide layer is 2-6nm, the thickness of the first microcrystalline silicon layer is 8-20nm, and the thickness of the first amorphous silicon layer is 1-4nm.

4. A high efficiency heterojunction solar cell as claimed in any one of claims 1 to 3, wherein: the semiconductor device further comprises a second passivation layer arranged on the second main surface of the semiconductor substrate and a second semiconductor film layer which is arranged on the second passivation layer and doped with different conductive types from the first semiconductor film layer; the second semiconductor film layer comprises a second microcrystalline silicon lamination layer arranged on the second passivation layer and a second amorphous silicon layer which is arranged on the second microcrystalline silicon lamination layer and has the same conductive type doping as the second microcrystalline silicon lamination layer.

5. A high efficiency heterojunction solar cell as claimed in claims 1-3, wherein: the first passivation layer is only arranged on a part of the first main surface of the semiconductor substrate; a second passivation layer and a second semiconductor film layer which is arranged on the second passivation layer and has different conduction type doping with the first semiconductor film layer are arranged on the first main surface which is not covered by the first passivation layer; the second semiconductor film layer comprises a second microcrystalline silicon lamination layer arranged on the second passivation layer and a second amorphous silicon layer which is arranged on the second microcrystalline silicon lamination layer and has the same conductive type doping as the second microcrystalline silicon lamination layer.

6. The method for manufacturing a high-efficiency heterojunction solar cell as claimed in any one of claims 1 to 5, wherein: it comprises forming a first semiconductor film layer with N-type doping or P-type doping on a first passivation layer of a passivation-treated semiconductor substrate,

step A, forming a first microcrystalline silicon stack on a first passivation layer of a passivated semiconductor substrate;

and step B, forming a first amorphous silicon layer on the first microcrystalline silicon lamination.

7. The method for manufacturing the high-efficiency heterojunction solar cell as claimed in claim 6, wherein: the specific procedure of the step A is that a1, a first microcrystalline silicon seed layer is deposited on a first passivation layer of a semiconductor substrate after passivation treatment; a2, depositing a first microcrystalline silicon oxide layer with N-type doping or P-type doping on the first microcrystalline silicon seed layer; a3, depositing a first microcrystalline silicon layer with the same conductive type doping as the first microcrystalline silicon oxide layer on the first microcrystalline silicon oxide layer.

8. The method for manufacturing the high-efficiency heterojunction solar cell as claimed in claim 7, wherein: the specific method of the procedure a1 is that the PECVD film forming temperature is preset to be 150-250 ℃, then the mixed gas of silane and hydrogen is introduced, and the pressure of the reaction gas is 100-300Pa, so as to deposit a first microcrystalline silicon seed layer.

9. The method for manufacturing the high-efficiency heterojunction solar cell as claimed in claim 7, wherein: when the N-type doped first semiconductor film layer is prepared, the specific method of the step a2 is that the PECVD film forming temperature is preset to be 150-250 ℃, then the mixed gas of silane, phosphane, hydrogen and carbon dioxide is introduced, the pressure of the reaction gas is 150-500Pa, the ratio of the phosphane to the silane is 1-10%, and the ratio of the carbon dioxide to the silane is 50-100%, so as to deposit the N-type first microcrystalline silicon oxide layer;

when the P-type doped first semiconductor film layer is prepared, the specific method of the step a2 is that the PECVD film forming temperature is preset to be 150-250 ℃, then the mixed gas of silane, diborane, hydrogen and carbon dioxide is introduced, the pressure of the reaction gas is 150-500Pa, the ratio of diborane to silane is 0.5% -4%, and the ratio of carbon dioxide to silane is 50% -100%, so as to deposit the P-type first microcrystalline silicon oxide layer.

10. The method for manufacturing the high-efficiency heterojunction solar cell as claimed in claim 7, wherein: when preparing the N-type doped first semiconductor film layer, the specific method of the step a3 is that the PECVD film forming temperature is preset to be 150-250 ℃, then the mixed gas of silane, phosphane and hydrogen is introduced, the pressure of the reaction gas is 150-500Pa, and the deposition power density is 0.08-0.3W/cm ² The ratio of the phosphane to the silane is 1-10 percent so as to deposit an N-type first microcrystalline silicon layer;

when preparing the P-type doped first semiconductor film layer, the specific method of the procedure a3 is that the PECVD film forming temperature is preset to be 150-250 ℃, then the mixed gas of silane, diborane and hydrogen is introduced, the pressure of the reaction gas is 150-500Pa, and the deposition power density is 0.1-0.5W/cm ² The diborane to silane ratio is 0.5% -4% to deposit a P-type first microcrystalline silicon layer.

11. The method for manufacturing the high-efficiency heterojunction solar cell as claimed in claim 7, wherein: when makingWhen preparing the N-type doped first semiconductor film layer, the specific method in the step B is that the PECVD film forming temperature is preset to be 150-250 ℃, then the mixed gas of silane, phosphane and hydrogen is introduced, the pressure of the reaction gas is 30-150Pa, and the deposition power density is 0.01-0.02W/cm ² The ratio of phosphane to silane is 1% -10% to deposit an N-type first amorphous silicon layer;

when preparing the P-type doped first semiconductor film layer, the specific method in the step B is that the PECVD film forming temperature is preset to be 150-250 ℃, then the mixed gas of silane, diborane and hydrogen is introduced, the pressure of the reaction gas is 30-150Pa, and the deposition power density is 0.01-0.02W/cm ² The ratio of diborane to silane is 1% -10% to deposit a P-type first amorphous silicon layer.

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