CN115513281A - Insulated Gate Bipolar Transistor - Google Patents

Abstract

The present application discloses an insulated gate bipolar transistor. The insulated gate bipolar transistor includes a gate bus, a built-in resistance region, and a gate lead bonding region. The built-in resistance region includes at least one built-in resistance island, and the built-in resistance island includes The first polysilicon, the second polysilicon and the third polysilicon, the first polysilicon is respectively connected to one end of the second polysilicon and one end of the third polysilicon, and the other end of the second polysilicon It is connected with the gate bus line; the gate lead bonding area is connected with the other end of the third polysilicon. This solution can flexibly adjust the built-in resistance of the gate of the insulated gate bipolar transistor by adjusting the number of built-in resistance islands in the built-in resistance area, without redesigning the polysilicon layer and metal layer, that is, without redesigning Carry out tape-out production, thereby saving manufacturing cost and time cost.

Description

Insulated Gate Bipolar Transistor

technical field

The present application relates to the technical field of semiconductors, in particular to an insulated gate bipolar transistor.

Background technique

Insulated Gate Bipolar Transistor (IGBT) is a new type of power electronic device that combines MOS field effect transistors and bipolar transistors. It not only has the advantages of easy driving and simple control of MOSFET, but also has the advantages of low conduction voltage of power transistor, large on-state current and small loss. It has become one of the core electronic components in modern power electronic circuits and is widely used in Various fields of the national economy such as communications, energy, transportation, industry, medicine, household appliances and aerospace. The application of IGBT plays an extremely important role in improving the performance of power electronic systems.

At present, some IGBTs with specific requirements require built-in resistors in the gate, and the resistors need to be customized according to application requirements. In the actual tape-out of IGBT, due to the deviation between simulation and reality, the gate built-in resistance is usually adjusted several times to obtain a satisfactory gate built-in resistance. At present, the mainstream technology is to introduce built-in gate resistors by designing the polysilicon layer and the metal layer. Therefore, if the resistance of the built-in gate resistor is adjusted, it is necessary to redesign the polysilicon layer and the metal layer, that is, it is necessary to perform tape-out again.

Contents of the invention

The embodiment of the present application provides an insulated gate bipolar transistor, which can adjust the built-in resistance of the gate without re-spinning.

An embodiment of the present application provides an insulated gate bipolar transistor, including:

gate bus;

Built-in resistance area, the built-in resistance area includes at least one built-in resistance island, the built-in resistance island includes first polysilicon, second polysilicon and third polysilicon, and the first polysilicon is respectively connected with the One end of the second polysilicon is connected to one end of the third polysilicon, and the other end of the second polysilicon is connected to the gate bus line;

A gate wire bonding area, the gate wire bonding area is connected to the other end of the third polysilicon.

In the IGBT provided in the embodiment of the present application, the resistivity of the second polysilicon and the third polysilicon are both smaller than the resistivity of the first polysilicon.

In the IGBT provided in the embodiment of the present application, the first polysilicon has a first grain size and a first raw material concentration, and both the second polysilicon and the third polysilicon are having a second grain size and a second raw material concentration.

In the IGBT provided in the embodiment of the present application, when the first grain size is equal to the second grain size, the first raw material concentration is greater than the second raw material concentration.

In the IGBT provided in the embodiment of the present application, when the concentration of the first material is equal to the concentration of the second material, the first grain size is smaller than the second grain size.

In the IGBT provided in the embodiment of the present application, the sheet resistance of the first polysilicon is 5Ω/sq˜20Ω/sq.

In the IGBT provided in the embodiment of the present application, the sheet resistances of the second polysilicon and the third polysilicon are both 0.1Ω/sq˜1Ω/sq.

In the IGBT provided in the embodiment of the present application, the doping impurity in the first polysilicon is phosphorus, and the doping concentration of the doping impurity is 1e19 ⁻³ to 1e20 cm ⁻³ .

In the IGBT provided in the embodiment of the present application, the doping impurities in the second polysilicon and the third polysilicon are both phosphorus, and the doping concentration of the doping impurities is 1e20cm ^-3 ~1e21cm ^-3 .

In the IGBT provided in the embodiment of the present application, the thickness of the first polysilicon is 0.2 μm˜2 μm.

To sum up, the IGBT provided by the embodiment of the present application includes a gate bus, a built-in resistance area and a gate lead bonding area, the built-in resistance area includes at least one built-in resistance island, and the built-in resistance island includes a first a polysilicon, a second polysilicon and a third polysilicon, the first polysilicon is respectively connected to one end of the second polysilicon and one end of the third polysilicon, and the first polysilicon The other end of the second polysilicon is connected to the gate bus line; the gate lead bonding area is connected to the other end of the third polysilicon. In this solution, the number of built-in resistance islands in the built-in resistance region can be adjusted, and/or the thickness of the first polysilicon can be adjusted through an etching process or a deposition process, so that the gate of the insulated gate bipolar transistor can be built-in The resistance can be adjusted flexibly, without redesigning the polysilicon layer and the metal layer, that is, without re-making the tape-out, thereby saving manufacturing cost and time cost.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained based on these drawings without any creative effort.

FIG. 1 is a schematic diagram of a first structure of an IGBT provided by an embodiment of the present application.

FIG. 2 is a schematic diagram of a second structure of an IGBT provided by an embodiment of the present application.

FIG. 3 is a schematic diagram of a third structure of an IGBT provided by an embodiment of the present application.

detailed description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with aspects of the present application as recited in the appended claims.

It should be noted that, in this document, the term "comprising", "comprising" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article or apparatus comprising a set of elements includes not only those elements, It also includes other elements not expressly listed, or elements inherent in the process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a..." does not exclude the existence of other identical elements in the process, method, article, or device that includes the element. In addition, different implementations of the present application Components, features, and elements with the same name in the example may have the same meaning, or may have different meanings, and the specific meaning shall be determined based on the explanation in the specific embodiment or further combined with the context in the specific embodiment.

It should be understood that the specific embodiments described here are only used to explain the present application, and are not intended to limit the present application.

In the following description, the use of suffixes such as 'module', 'part' or 'unit' for denoting elements is only for facilitating the description of the present application and has no specific meaning by itself. Therefore, 'module', 'part' or 'unit' may be mixedly used.

In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", "inner" and "outer" are based on the Orientation or positional relationship is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and should not be construed as indicating or implying relative importance.

The technical solutions shown in this application will be described in detail below through specific embodiments. It should be noted that the order of description of the following embodiments is not intended to limit the order of priority of the embodiments.

At present, some IGBTs with specific requirements require built-in resistors in the gate, and the resistors need to be customized according to application requirements. In the actual tape-out of IGBT, due to the deviation between simulation and reality, the gate built-in resistance is usually adjusted several times to obtain a satisfactory gate built-in resistance. At present, the mainstream technology is to introduce built-in gate resistors by designing the polysilicon layer and the metal layer. Therefore, if the resistance of the built-in gate resistor is adjusted, it is necessary to redesign the polysilicon layer and the metal layer, that is, it is necessary to perform tape-out again.

Based on this, an embodiment of the present application provides an insulated gate bipolar transistor. As shown in Figure 1, Figure 1 is a schematic structural diagram of an insulated gate bipolar transistor provided by an embodiment of the present application, which may include a gate bus 10, a built-in resistance region 20, and a gate lead bonding region 30.

Wherein, the gate bus line 10 is made of polysilicon. The gate bus 10 is connected to the gates of tens of thousands of cells in the active region, and provides overall transmission of gate control signals for each cell.

Wherein, the built-in resistance region includes at least one built-in resistance island 21 . The built-in resistor island 21 includes a first polysilicon 211, a second polysilicon 212 and a third polysilicon 213, and the first polysilicon 211 is connected to one end of the second polysilicon 212 and the third polysilicon 213 respectively. One end of the second polysilicon 212 is connected to the other end of the second polysilicon 212 and the gate bus 10 is connected.

Wherein, the gate wire bonding area 30 is connected to the other end of the third polysilicon 213 . The gate lead bonding area 30 is made of polysilicon material.

Generally, when making power devices, certain impurities are doped in the polysilicon material, so that the polysilicon material has a certain resistance. Therefore, the first polysilicon 211 , the second polysilicon 212 and the third polysilicon 213 all have resistance.

Therefore, in this embodiment, the built-in resistance of the gate of the IGBT can be flexibly adjusted by adjusting the number of built-in resistance islands 21 in the built-in resistance region 20, without re-adjusting the polysilicon layer and metal Layers are designed, that is, there is no need to re-strip production, thereby saving manufacturing costs and time costs.

For example, when the resistance of each built-in resistance island 21 is 10Ω and the number is 1, the gate built-in resistance at this time is 10Ω. When the resistance of each built-in resistance island 21 is 10Ω and the number is 2, the built-in resistance of the gate is 5Ω. When the resistance of each built-in resistance island 21 is 10Ω and the number is 3, the built-in resistance of the gate is about 3.3Ω.

In the embodiment of the present application, the doping impurity in the first polysilicon 211 is phosphorus, and the doping concentration of the doping impurity is 1e19 ⁻³ to 1e20 cm ⁻³ . The doping impurities in the second polysilicon 212 are all phosphorus, and the doping concentration of the doping impurities is 1e20cm ⁻³ to 1e21cm ⁻³ . The doping impurities in the third polysilicon 213 are all phosphorus, and the doping concentration of the doping impurities is 1e20cm ⁻³ to 1e21cm ⁻³ .

It should be noted that the doping concentrations of doping impurities in the second polysilicon 212 and the third polysilicon 213 may be the same or different, which may be set according to actual conditions.

It should be noted that the doping impurities in the second polysilicon 212 and the third polysilicon 213 include but not limited to phosphorus. The doping impurities in the second polysilicon 212 and the third polysilicon 213 may also include other non-phosphorous doping impurities. For example, the doping impurity in the second polysilicon 212 and the third polysilicon 213 can also be boron.

It can be understood that, in order to transmit the gate electrical signal to the gate bus 10 , the built-in resistance region needs to have at least one built-in resistance island 21 . It should be noted that, in the embodiment of the present application, the number of the built-in resistance islands 21 may be 1-5.

In the embodiment of the present application, the first polysilicon 211 is used to form a built-in gate resistor, while the second polysilicon 212 and the third polysilicon 213 are used to conduct current. In order to facilitate the first polysilicon 211 to form a gate built-in resistor, and the second polysilicon 212 and the third polysilicon 213 conduct current, in the embodiment of the present application, the second polysilicon 212 and the third polysilicon The resistivity of 213 is smaller than the resistivity of the first polysilicon 211 .

In some embodiments, by adjusting the grain size and/or raw material concentration of the first polysilicon 211, the second polysilicon 212 and the third polysilicon 213, the first polysilicon 211, the second polysilicon The resistivities of the crystalline silicon 212 and the third polysilicon 213 are adjusted.

In some embodiments, it can be preset that the first polysilicon 211 has a first grain size and a first raw material concentration, and both the second polysilicon 212 and the third polysilicon 213 have a second grain size and a second raw material concentration.

At this time, in order to make the resistivity of the second polysilicon 212 and the third polysilicon 213 smaller than the resistivity of the first polysilicon 211 . In some embodiments, the details can be as follows:

When the first grain size is equal to the second grain size, the first raw material concentration is greater than the second raw material concentration. When the first raw material concentration is equal to the second raw material concentration, the first grain size is smaller than the second grain size.

It should be noted that there are many ways to adjust the resistivity of the first polysilicon 211 , the second polysilicon 212 and the third polysilicon 213 , including but not limited to the above ways.

In some embodiments, the second polysilicon 212 and the third polysilicon 213 may be directly connected to the first polysilicon 211 .

In another embodiment, the second polysilicon 212 and the first polysilicon 211 may be connected to each other through a contact hole.

Specifically, a dielectric layer may be provided between the first polysilicon 211 and the second polysilicon 212 , so that the first polysilicon 211 and the second polysilicon 212 are formed. However, a contact hole may be provided on the dielectric layer, through which the connection between the second polysilicon 212 and the first polysilicon 211 is realized.

It can be understood that resistivity is directly proportional to resistance. In a unit area, the higher the resistivity, the greater the resistance; the smaller the resistivity, the smaller the resistance.

In the embodiment of the present application, the resistances of the second polysilicon 212 and the third polysilicon 213 are both smaller than the resistance of the first polysilicon 211 . The resistances of the second polysilicon 212 and the third polysilicon 213 are both less than 1Ω.

In some embodiments, in order to make the resistance of the second polysilicon 212 and the third polysilicon 213 much smaller than the resistance of the first polysilicon 211, the resistance of the second polysilicon 212 and the third polysilicon 213 can be The size is set to be smaller than that of the first polysilicon 211 .

It can be understood that the size of the second polysilicon 212 may be the same as that of the third polysilicon 213, or may be different from the size of the third polysilicon 213, which may be set according to actual conditions.

It should be noted that, in the embodiment of the present application, the aspect ratio of the first polysilicon 211 may be 1:1˜4:1. In this embodiment, each first polysilicon 211 can be set with a different aspect ratio, so that each first polysilicon 211 has a different single resistance, which is beneficial to flexibly adjust the built-in gate resistance.

Since the resistances of the second polysilicon 212 and the third polysilicon 213 are too small, they can be ignored. Therefore, by adjusting the aspect ratio of the first polysilicon 211 , the resistance of the built-in resistance island 21 can be adjusted, and further the built-in resistance of the gate of the IGBT can be adjusted.

For example, when the aspect ratio of the first polysilicon 211 is 2:1 and the sheet resistance of the first polysilicon 211 is 5Ω/sq, the resistance of the built-in resistor island 21 is about 10Ω. For another example, when the aspect ratio of the first polysilicon 211 is 3:1 and the sheet resistance of the first polysilicon 211 is 5Ω/sq, the resistance of the built-in resistance island 21 is about 15Ω.

In the embodiment of the present application, the sheet resistance of the first polysilicon 211 is 5Ω/sq˜20Ω/sq. The sheet resistance of the second polysilicon 212 is 0.1Ω/sq˜1Ω/sq. The sheet resistance of the third polysilicon 213 is 0.1Ω/sq˜1Ω/sq.

It can be understood that the sheet resistance of the second polysilicon 212 may be the same as that of the third polysilicon 213 , or may be different from that of the third polysilicon 213 , which may be set according to actual conditions.

It should be noted that Ω/sq is the unit of square resistance, that is, ohm/square.

In some embodiments, the resistance of the first polysilicon 211 can be adjusted by adjusting the thickness of the first polysilicon 211 to adjust the resistance of the built-in resistance island 21, and then the gate of the IGBT Built-in resistors for adjustment. For example, the preset number of built-in resistance islands 21 is 1, and the resistance of the first polysilicon 211 with a thickness t is 10Ω. At this time, when the thickness of the first polysilicon 211 is t/2, the resistance of the built-in resistance island 21 is 20Ω. When the thickness of the first polysilicon 211 is t/3, the resistance of the built-in resistance island 21 is 30Ω.

It should be noted that, in the embodiment of the present application, the thickness of the first polysilicon 211 is 0.2 μm˜2 μm. In a specific implementation process, the thickness of the first polysilicon 211 can be adjusted through an etching process or a deposition process. For example, the thickness of the first polysilicon 211 can be reduced through an etching process, or the thickness of the first polysilicon 211 can be increased through a deposition process.

In some embodiments, as shown in FIG. 2 , the IGBT may further include package bonding wires 34 and bonding pads 40 . The wire bonding pad 40 is connected to the gate lead bonding area 30 through the package bonding wire 34 , so that the electrical signal applied to the gate from the outside is introduced into the IGBT.

In some embodiments, in order to facilitate the connection between the package bonding wire 34 and the gate lead bonding area 30 , as shown in FIG. 3 , a metal bonding area 50 may be provided on the gate lead bonding area 30 .

This embodiment also provides a method for manufacturing the insulated gate bipolar transistor. The method for manufacturing the insulated gate bipolar transistor may include the following steps: step 1, providing a semiconductor substrate, and making field oxygen and terminal rings; step Two, forming an active region; step three, forming and etching the first polysilicon layer, thereby forming the first polysilicon; step four, forming and etching the second polysilicon layer, thereby forming the second polysilicon and the third polysilicon; step five, forming a contact hole by etching; step six, forming a metal layer and photolithography; step seven, forming a passivation layer and back process.

It should be noted that the above is the general manufacturing process of the IGBT, and the specific manufacturing process of the IGBT is the same as that of the traditional IGBT, and will not be repeated here.

To sum up, the IGBT provided by the embodiment of the present application may include a gate bus 10, a built-in resistance area 20 and a gate lead bonding area 30, the built-in resistance area includes at least one built-in resistance island 21, and the built-in resistance island 21 It includes a first polysilicon 211, a second polysilicon 212 and a third polysilicon 213, the first polysilicon 211 is respectively connected to one end of the second polysilicon 212 and one end of the third polysilicon 213, and the second polysilicon 213 is connected to one end of the third polysilicon 213 The other end of the second polysilicon 212 is connected to the gate bus line 10 ; the gate wire pad 30 is connected to the other end of the third polysilicon 213 . In this solution, the number of built-in resistance islands 21 in the built-in resistance region 20 can be adjusted, and/or the thickness of the first polysilicon 211 can be adjusted through an etching process or a deposition process, so as to improve the performance of the insulated gate bipolar transistor. The built-in resistance of the gate can be flexibly adjusted without redesigning the polysilicon layer and the metal layer, that is, without re-making the tape-out, thereby saving manufacturing cost and time cost.

The insulated gate bipolar transistor provided by this application has been introduced in detail above. This article uses specific examples to illustrate the principle and implementation of this application. The description of the above embodiments is only used to help understand the core idea of this application. At the same time, for those skilled in the art, according to the idea of this application, there will be changes in the specific implementation and application scope. In summary, the content of this specification should not be construed as limiting the application.

Claims (10)

1. An insulated gate bipolar transistor, comprising:

a gate bus line;

the embedded resistor area comprises at least one embedded resistor island, the embedded resistor island comprises first polycrystalline silicon, second polycrystalline silicon and third polycrystalline silicon, the first polycrystalline silicon is respectively connected with one end of the second polycrystalline silicon and one end of the third polycrystalline silicon, and the other end of the second polycrystalline silicon is connected with the grid bus;

and the grid lead pressure welding area is connected with the other end of the third polysilicon.

2. The insulated gate bipolar transistor of claim 1 wherein the resistivity of each of the second polysilicon and the third polysilicon is less than the resistivity of the first polysilicon.

3. The insulated gate bipolar transistor of claim 2, wherein the first polysilicon has a first grain size and a first raw material concentration, and the second polysilicon and the third polysilicon each have a second grain size and a second raw material concentration.

4. The insulated gate bipolar transistor of claim 3, wherein the first raw material concentration is greater than the second raw material concentration when the first grain size is equal to the second grain size.

5. The insulated gate bipolar transistor of claim 3, wherein the first grain size is smaller than the second grain size when the first raw material concentration is equal to the second raw material concentration.

6. The insulated gate bipolar transistor of any of claims 1-5, wherein the first polysilicon has a sheet resistance of 5 Ω/sq to 20 Ω/sq.

7. The insulated gate bipolar transistor according to any one of claims 1 to 5, wherein the sheet resistance of the second polysilicon and the third polysilicon are each 0.1 Ω/sq to 1 Ω/sq.

8. The insulated gate bipolar transistor according to any one of claims 1 to 5, wherein the dopant impurity in the first polysilicon is phosphorus, and the dopant impurity has a dopant concentration of 1e19 ^-3 ~1e20cm ^-3 。

9. The insulated gate bipolar transistor according to any one of claims 1 to 5, wherein the doping impurities in the second polysilicon and the third polysilicon are both phosphorus, and the doping concentration of the doping impurities is 1e20cm ^-3 ~1e21cm ^-3 。

10. The insulated gate bipolar transistor according to any one of claims 1 to 5, wherein the first polysilicon has a thickness of 0.2 μm to 2 μm.

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