CN115407541B - Array substrate, manufacturing method thereof and display device - Google Patents

Abstract

The present invention discloses an array substrate and a manufacturing method thereof, and a display device, and relates to the field of display technology, a substrate, a transistor arranged on one side of the substrate; a first insulating layer and a second insulating layer arranged on the side of the transistor away from the substrate, the first insulating layer being located between the second insulating layer and the substrate along the thickness direction of the array substrate; a first opening, the first opening penetrating the first insulating layer and the second insulating layer along the thickness direction of the array substrate, and exposing the drain of the transistor; an auxiliary pad layer, located between the first insulating layer and the second insulating layer, the auxiliary pad layer being arranged around the first opening, and the first opening exposing the side wall of the auxiliary pad layer; a first electrode, located on the side of the second insulating layer away from the substrate, and at least part of the first electrode being located in the first opening, contacting the side wall of the auxiliary pad layer and being electrically connected to the drain of the transistor. This is conducive to reducing the risk of side engraving of the first insulating layer in the process of forming the first opening, and improving the dark spot defect phenomenon.

Description

Array substrate and manufacturing method thereof, and display device

Technical Field

The present invention relates to the field of display technology, and more specifically, to an array substrate and a manufacturing method thereof, and a display device.

Background technique

From the CRT (Cathode Ray Tube) era to the LCD (Liquid Crystal Display) era, and now to the OLED (Organic Light-Emitting Diode) era and the LED display era, the display industry has experienced decades of development and has changed with each passing day. The display industry is closely related to our lives, from traditional mobile phones, tablets, TVs and PCs to today's smart wearable devices, VR, car displays and other electronic devices, all of which are inseparable from display technology.

The array substrate is an important component of the display panel. The array substrate includes multiple transistors. In the manufacturing process of the array substrate, after the transistor is manufactured, an insulating layer is deposited on one side of the transistor, and a via is formed on the insulating layer by etching, and then an electrode layer is formed on the insulating layer, so that the electrode layer is electrically connected to the transistor. However, in the manufacturing process of the traditional array substrate, in the process of forming the via on the insulating layer, side etching will inevitably occur in the via, resulting in poor contact between the electrode layer and the transistor, resulting in abnormal product display, such as the appearance of dark spots, and reducing the product yield.

Summary of the invention

In view of this, the present invention provides an array substrate and a manufacturing method thereof, and a display device, aiming to reduce the risk of side etching of the first insulating layer during the formation of the first opening, improve the dark spot defect phenomenon, and improve the product yield.

In a first aspect, the present application provides an array substrate, comprising:

A substrate and a transistor disposed on one side of the substrate;

A first insulating layer and a second insulating layer are provided on a side of the transistor away from the substrate, wherein the first insulating layer is located between the second insulating layer and the substrate along a thickness direction of the array substrate;

A first opening, along a thickness direction of the array substrate, the first opening penetrating the first insulating layer and the second insulating layer and exposing the drain of the transistor;

an auxiliary pad layer, located between the first insulating layer and the second insulating layer, the auxiliary pad layer being disposed around the first opening, and the first opening exposing a side wall of the auxiliary pad layer;

The first electrode is located on a side of the second insulating layer away from the substrate, and at least a portion of the first electrode is located in the first opening, in contact with a side wall of the auxiliary pad layer and electrically connected to a drain of the transistor.

In a second aspect, the present invention provides a method for manufacturing an array substrate, comprising:

Providing a substrate, and manufacturing a transistor layer on the substrate, wherein the transistor layer includes a plurality of transistors;

Forming a first insulating layer on a side of the transistor layer facing away from the substrate;

An auxiliary layer is formed on a side of the first insulating layer away from the substrate, wherein the auxiliary layer overlaps with the drain of the transistor along a thickness direction of the array substrate;

forming a second insulating layer on a side of the auxiliary layer away from the first insulating layer;

Etching the first insulating layer, the auxiliary layer and the second insulating layer through an etching process to form a first opening and an auxiliary pad layer, wherein the auxiliary pad layer surrounds the first opening, and the first opening exposes the drain of the transistor and the sidewall of the auxiliary pad layer;

A first electrode is formed on a side of the second insulating layer away from the substrate, so that at least a portion of the first electrode is located in the first opening, contacts the side wall of the auxiliary pad layer and is electrically connected to the drain of the transistor.

In a third aspect, the present invention further provides a display device, comprising the array substrate provided in the first aspect of the present invention.

Compared with the prior art, the array substrate and the manufacturing method thereof, and the display device provided by the present invention achieve at least the following beneficial effects:

In the array substrate and display device provided by the present invention, a first insulating layer and a second insulating layer and a first opening penetrating the first insulating layer and the second insulating layer are provided on the side of the transistor of the array substrate facing away from the substrate, and at least a portion of the first electrode is located in the first opening to form an electrical connection with the drain of the transistor. In particular, the present invention introduces an auxiliary pad layer between the first insulating layer and the second insulating layer, the auxiliary pad layer is arranged around the first opening, and the first opening exposes the side wall of the auxiliary pad layer, so that when the first opening is formed by etching, due to the blocking effect of the auxiliary pad layer, the phenomenon of side engraving of the first opening at the junction of the first insulating layer and the second insulating layer can be avoided to a large extent, so it is helpful to avoid or reduce the phenomenon of unreliable connection between the first electrode and the transistor caused by side engraving, so it is helpful to improve the connection reliability between the first electrode and the transistor, avoid or reduce the occurrence of dark spot defects, so it is helpful to improve the display reliability and production yield of the product.

In the manufacturing method of the array substrate provided by the embodiment of the present invention, an auxiliary layer is introduced between the first insulating layer and the second insulating layer, and the first insulating layer, the auxiliary layer and the second insulating layer are etched by an etching process to form a first opening, and the etched auxiliary layer forms an auxiliary pad layer surrounding the opening. The introduction of the auxiliary layer effectively reduces or avoids the phenomenon that the first opening forms side etching at the junction of the first insulating layer and the second insulating layer, so it is helpful to avoid or reduce the phenomenon that the connection between the first electrode and the transistor is unreliable due to side etching. The method of forming the first opening by an etching process is not only helpful to avoid the occurrence of dark spot defects, but also helpful to simplify the production process and improve production efficiency.

Of course, any product implementing the present invention does not necessarily need to achieve all of the technical effects described above at the same time.

Further features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention with reference to the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG1 is a schematic diagram of a film layer of an array substrate in the related art;

FIG2 is a top view of an array substrate provided by an embodiment of the present invention;

FIG3 is a schematic diagram of a film layer of the array substrate in FIG2 ;

FIG4 is a top view of an auxiliary pad layer, a first electrode and a first opening in an array substrate provided by an embodiment of the present invention;

FIG5 is a schematic diagram of another film layer of the array substrate in FIG2 ;

FIG6 is a schematic diagram showing another film layer of the array substrate in FIG2 ;

FIG. 7 is a schematic diagram of another film layer of the array substrate in FIG. 2 ;

FIG8 is a schematic diagram of another film layer of the array substrate in FIG2 ;

FIG9 is a flowchart showing a manufacturing process of an array substrate provided by an embodiment of the present invention;

FIG10 is a schematic structural diagram of an intermediate product formed in the process of manufacturing an array substrate provided in an embodiment of the present invention;

FIG. 11 is another schematic structural diagram of an intermediate product formed in the process of manufacturing an array substrate provided in an embodiment of the present invention;

FIG. 12 is another schematic structural diagram of an intermediate product formed in the process of manufacturing an array substrate provided in an embodiment of the present invention;

FIG. 13 is another schematic structural diagram of an intermediate product formed in the process of manufacturing an array substrate provided in an embodiment of the present invention;

FIG. 14 is another schematic structural diagram of an intermediate product formed in the process of manufacturing an array substrate provided in an embodiment of the present invention;

FIG. 15 is a schematic diagram showing a structure of a display device provided in an embodiment of the present invention.

Detailed ways

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless otherwise specifically stated.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

In all examples shown and discussed herein, any specific values should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

FIG1 is a schematic diagram of a film layer of an array substrate 100' in the related art. Please refer to FIG1. In the related art, two passivation layers 20' are arranged on the array substrate 100', and the electrode 41' and the transistor 10' are respectively located on both sides of the two passivation layers 20'. Since the film layer of the passivation layer 20' is relatively thick, and the two passivation layers 20' are made of the same material, in the process of forming another passivation layer 20' on one passivation layer 20', if the overlap of the two passivation layers 20' is not reliable, when the two passivation layers 20' are etched to form an etching hole K1' connecting the electrode 41' and the transistor 10', the position where the two passivation layers 20' intersect in the etching hole K1' is prone to side etching (as shown by the circular dotted frame in FIG1). In order to achieve the electrical connection between the electrode 41' and the transistor 10', part of the material of the electrode 41' will flow from the top of the etching hole K1' to the bottom of the hole and overlap the transistor 10'. However, due to the side etching phenomenon in the etching hole K1’, the electrode 41’ material in the etching hole K1’ is very easy to break, which will cause the overlapping impedance between the electrode 41’ material in the etching hole K1’ and the transistor 10’ to increase or even disconnect. The direct impact on the display effect is that dark spots may appear in the corresponding area, affecting the overall display effect of the display panel.

In view of this, the present invention provides an array substrate and a manufacturing method thereof, and a display device, aiming to reduce the risk of side etching of the first insulating layer during the formation of the first opening, improve the dark spot defect phenomenon, and improve the product yield.

FIG. 2 is a top view of an array substrate 100 provided in an embodiment of the present invention. FIG. 3 is a schematic diagram of a film layer of the array substrate 100 in FIG. 2 , which shows a schematic diagram of a connection between a first electrode 41 in the array substrate 100 and a transistor 10. FIG. 4 is a top view of an auxiliary pad layer 30, a first electrode 41 and a first opening K1 in the array substrate 100 provided in an embodiment of the present invention. Referring to FIG. 2 to FIG. 4 , the present invention provides an array substrate 100, including:

A substrate 00 and a transistor 10 disposed on one side of the substrate 00;

A first insulating layer 21 and a second insulating layer 22 are provided on a side of the transistor 10 away from the substrate 00 , and along the thickness direction of the array substrate 100 , the first insulating layer 21 is located between the second insulating layer 22 and the substrate 00 ;

A first opening K1 is formed along the thickness direction of the array substrate 100 . The first opening K1 penetrates the first insulating layer 21 and the second insulating layer 22 and exposes the drain of the transistor 10 .

The auxiliary pad layer 30 is located between the first insulating layer 21 and the second insulating layer 22. The auxiliary pad layer 30 is disposed around the first opening K1, and the first opening K1 exposes the side wall of the auxiliary pad layer 30.

The first electrode 41 is located on a side of the second insulating layer 22 facing away from the substrate 00 , and at least a portion of the first electrode 41 is located in the first opening K1 , in contact with a sidewall of the auxiliary pad layer 30 and electrically connected to the drain of the transistor 10 .

It should be noted that FIG. 2 only illustrates an array substrate 100 with a rectangular structure, and does not limit the actual shape of the array substrate 100. In some other embodiments of the present invention, the shape of the array substrate 100 may also be a rounded rectangle, a circle or other special shapes. Moreover, FIG. 2 only illustrates a portion of the first electrodes 41 on the array substrate 100, and does not represent the actual number of first electrodes 41 included in the array substrate 100. FIG. 3 only illustrates a film layer structure of the array substrate 100, and does not represent the actual number of film layers and the thickness of the film layers included in the array substrate 100. FIG. 4 only illustrates a top-down relationship between the auxiliary pad 30, the first electrode 41 and the first opening K1, and does not represent the actual size.

Specifically, referring to FIG. 2 and FIG. 3 , the array substrate 100 provided by the present invention is generally provided with a plurality of pixel driving circuits, and the pixel driving circuit includes a plurality of transistors 10. Although FIG. 2 and FIG. 3 only show one transistor 10 connected to the first electrode 41, they do not represent the actual number of transistors in the pixel driving circuit corresponding to the first electrode 41. Optionally, the array substrate further includes a plurality of scanning lines S and a plurality of data lines D, and the gate of the transistor connected to the first electrode 41 is connected to the scanning line S, and the source is connected to the data line D. In the embodiment of the present invention, a first insulating layer 21 and a second insulating layer 22 are provided on the side of the transistor 10 of the array substrate 100 away from the substrate 00, and the first electrode 41 is located on the side of the second insulating layer 22 away from the first insulating layer 21. In order to realize the electrical connection between the first electrode 41 and the transistor 10, a first opening K1 is provided that penetrates the first insulating layer 21 and the second insulating layer 22 along the thickness direction of the array substrate 100, and at least a portion of the first electrode 41 is located in the first opening K1, and is electrically connected to the drain of the transistor 10.

In particular, the embodiment of the present invention introduces an auxiliary pad layer 30 between the first insulating layer 21 and the second insulating layer 22, that is, the auxiliary pad layer 30 is introduced into at least a portion of the junction area of the first insulating layer 21 and the second insulating layer 22, the auxiliary pad layer 30 is arranged around the first opening K1, and the first opening K1 exposes the side wall of the auxiliary pad layer 30. In this way, when the first opening K1 is formed by etching, due to the blocking effect of the auxiliary pad layer 30, the first opening K1 can be prevented from forming side etching at the junction of the first insulating layer 21 and the second insulating layer 22 to a large extent. Therefore, it is beneficial to avoid or reduce the unreliable connection between the first electrode 41 and the transistor 10 caused by the side etching, and therefore it is beneficial to improve the connection reliability between the first electrode 41 and the transistor 10. When the array substrate 100 provided by the present invention is applied to a display product, it can avoid or reduce the occurrence of dark spot defects, so it is beneficial to improve the display reliability and production yield of the product.

Optionally, the first insulating layer 21 and the second insulating layer 22 in the embodiment of the present invention are both passivation layers.

In an optional embodiment of the present invention, the auxiliary pad layer 30 is a conductive material layer.

Specifically, in the embodiment of the present invention, the auxiliary pad layer 30 between the first insulating layer 21 and the second insulating layer 22 is set as a conductive material layer, and the portion of the first electrode 41 located in the first opening K1 will be able to overlap with the auxiliary pad layer 30. The auxiliary pad layer 30 can be regarded as a conductive overlapping platform between the first electrode 41 and the transistor 10, which is beneficial to avoid the portion of the first electrode 41 located in the first opening K1 from breaking in the first opening K1, thereby ensuring the reliability of the electrical connection between the first electrode 41 and the transistor 10, and avoiding the occurrence of dark spot defects when the array substrate 100 is applied to display products.

Optionally, the auxiliary pad layer 30 in the embodiment of the present invention may be a non-conductive material layer different from the first insulating layer 21 and the second insulating layer 22 in addition to being a conductive material layer.

It should be noted that, in addition to forming an electrical connection with the first electrode 41, the auxiliary pad layer 30 in the embodiment of the present invention is not electrically connected to other conductive layers on the array substrate 100. That is to say, the signal on the auxiliary pad layer 30 is consistent with the signal on the first electrode 41 connected thereto, thereby avoiding affecting the accuracy of the signal on the first electrode 41 when the auxiliary pad layer 30 is connected to other film layers.

FIG5 is another film layer schematic diagram of the array substrate 100 in FIG2 . In addition to illustrating the connection between the first electrode 41 in the array substrate 100 and the transistor 10 , the film layer schematic diagram further illustrates a relative position relationship between the first electrode 41 and the second electrode 42 when the array substrate 100 includes the first electrode 41 and the second electrode 42 .

Please refer to Figure 5. In an optional embodiment of the present invention, the array substrate 100 in the embodiment of the present invention also includes a second electrode 42 located between the first insulating layer 21 and the second insulating layer 22. The second electrode 42 is insulated from the auxiliary pad layer 30, and along the thickness direction of the array substrate 100, the thickness of the auxiliary pad layer 30 is the same as that of the second electrode 42.

Optionally, the array substrate 100 provided in the embodiment of the present invention can be applied to liquid crystal display products. The first electrode 41 and the second electrode 42 introduced in the embodiment of the present invention correspond to the pixel electrode and the common electrode in the liquid crystal display product, respectively. A voltage signal is provided to the pixel electrode through the transistor 10, so that a voltage for driving the liquid crystal deflection is formed between the pixel electrode and the common electrode, thereby realizing the display function.

Optionally, the second electrode 42 and the auxiliary pad layer 30 are both located between the first insulating layer 21 and the second insulating layer 22. In the actual manufacturing process, after the second electrode 42 and the auxiliary pad layer 30 are formed on the first insulating layer 21, the second insulating layer 22 is formed on the side of the second electrode 42 and the auxiliary pad layer 30 away from the first insulating layer 21. In the embodiment of the present invention, when the thickness of the auxiliary pad layer 30 and the second electrode 42 are the same, when the second insulating layer 22 is formed on the side of the auxiliary pad layer 30 and the second electrode 42 away from the first insulating layer 21, it is beneficial to ensure the flatness of the surface of the side of the second insulating layer 22 away from the first insulating layer 21, thereby facilitating the flatness of the second electrode 42 formed on the second insulating layer 22, and further facilitating the display uniformity of the display product when the array substrate 100 is applied to the display product.

FIG6 is another schematic diagram of a film layer of the array substrate 100 in FIG2. In an optional embodiment of the present invention, the auxiliary pad layer 30 and the second electrode 42 are made in the same manufacturing process using the same mask. It should be noted that in order to reflect that the auxiliary pad layer 30 and the second electrode 42 are made in the same manufacturing process, the auxiliary pad layer 30 and the second electrode 42 are filled in the same way in FIG6. Of course, in other embodiments, when the auxiliary pad layer 30 and the second electrode 42 are filled differently, it can mean that the two are made of the same material or different materials.

Specifically, in the array substrate 100 provided by the embodiment of the present invention, when the auxiliary pad layer 30 and the second electrode 42 are both arranged between the first insulating layer 21 and the second insulating layer 22, in the process of forming the auxiliary pad layer 30 and the second electrode 42 on the first insulating layer 21, the auxiliary pad layer 30 and the second electrode 42 can be produced using the same mask plate in the same production process. In this way, there is no need to introduce additional mask plates and production processes for the auxiliary pad layer 30. The production of the auxiliary pad layer 30 can be completed in the process of producing the second electrode 42, which is beneficial to simplify the overall production process of the array substrate 100 and improve the production efficiency of the entire array substrate.

FIG7 is another schematic diagram of the film layer of the array substrate 100 in FIG2, which not only shows the connection diagram of the first electrode 41 and the transistor 10 in the array substrate 100, but also shows another relative position relationship between the auxiliary pad layer 30 and the second insulating layer 22. In the schematic diagrams of the film layer shown in FIG5 and FIG6, the first opening K1 only exposes the side surface of the auxiliary pad layer 30; in the schematic diagram of the film layer shown in FIG7, the first opening K1 not only exposes the side surface of the auxiliary pad layer 30, but also exposes at least a portion of the surface of the auxiliary pad layer 30 facing the second insulating layer 22.

Please refer to FIG. 7 . In an optional embodiment of the present invention, the first opening K1 exposes at least part of the surface of the auxiliary pad layer 30 facing away from the substrate 00 , and the first electrode 41 is also in contact with at least part of the surface of the auxiliary pad layer 30 facing away from the substrate 00 .

Specifically, in the array substrate 100 provided in the embodiment of the present invention, an auxiliary pad layer 30 is introduced between the first insulating layer 21 and the second insulating layer 22. When the first opening K1 is formed, the first opening K1 actually penetrates the second insulating layer 22, the auxiliary pad layer 30 and the first insulating layer 21 respectively. In this way, the first opening K1 will expose the side wall of the auxiliary pad layer 30. Furthermore, the first opening K1 in the present embodiment also exposes at least a portion of the surface of the auxiliary pad 30 toward the second insulating layer 22. When the first electrode 41 is formed on the side of the second insulating layer 22 away from the first insulating layer 21, the portion of the first electrode 41 located in the first opening K1 will contact both the side wall of the auxiliary pad 30 and the surface of the auxiliary pad 30 facing the second insulating layer 22. This effectively increases the contact area between the first electrode 41 and the auxiliary pad 30, thereby facilitating the improvement of the reliability of the electrical connection between the first electrode 41 and the auxiliary pad 30, and further facilitating the avoidance of the breakage of the portion of the first electrode 41 located in the first opening K1. Therefore, it is more conducive to improving the connection reliability between the first electrode 41 and the transistor 10, and avoiding the occurrence of dark spots when the array substrate 100 is applied to display products.

7 , in an optional embodiment of the present invention, at least a portion of the surface of the auxiliary pad layer 30 facing away from the substrate 00 is covered by the second insulating layer 22 .

It should be noted that when the surface of the auxiliary pad layer 30 facing away from the substrate 00 is exposed by the first opening, in the process of etching to form the first opening K1, the first insulating layer 21 located on the side of the auxiliary pad layer 30 far from the opening along the surface parallel to the plane where the second insulating layer 22 is located is very likely to be undesirably etched, affecting the functional reliability of the entire array substrate. Therefore, when the first opening K1 in the present invention exposes at least part of the surface of the auxiliary pad layer 30 facing the second insulating layer 22 to improve the connection reliability between the first electrode 41 and the auxiliary pad layer 30, it is also ensured that the remaining surface of the auxiliary pad layer 30 facing the second insulating layer 22 is covered by the second insulating layer 22, that is, in the process of etching to form the first opening K1, the undesirable etching phenomenon of the first insulating layer 21 located on the side of the auxiliary pad layer 30 far from the first opening K1 is effectively avoided, thereby helping to improve the functional stability of the array substrate 100.

Please refer to Figures 5 to 7. In an optional embodiment of the present invention, the array substrate 100 also includes a planar layer 50 located between the transistor 10 and the first insulating layer 21. The planar layer 50 includes a second opening K2 exposing the drain of the transistor 10. Along the thickness direction of the array substrate 100, the first opening K1 and the second opening K2 overlap.

Specifically, the embodiment of the present invention forms a flat layer 50 on the side of the transistor 10 away from the substrate 00, thereby providing a flat surface for the remaining film layers on the transistor 10, which is convenient for the subsequent film layer production. In this way, the insulating layer between the transistor 10 and the first electrode 41 includes not only the first insulating layer 21 and the second insulating layer 22, but also the flat layer 50 located on the side of the first insulating layer 21 facing the substrate 00. In the actual production process, after the flat layer 50 is produced on the transistor 10, in order to realize the electrical connection between the subsequently formed first electrode 41 and the transistor 10, a second opening K2 can be first formed on the flat layer 50, and the second opening K2 exposes the drain of the transistor 10, and then the first insulating layer 21, the auxiliary pad layer 30, the second electrode 42 layer, and the second insulating layer 22 are formed on the side of the flat layer 50 away from the substrate 00. After the second insulating layer 22 is produced, the first opening K1 penetrating the second insulating layer 22, the auxiliary pad layer 30 and the first insulating layer 21 is formed by etching. In the embodiment of the present invention, the first opening K1 and the second opening K2 are arranged to overlap along the thickness direction of the array substrate 100, so that the first opening K1 can expose the drain of the transistor 10 through the second opening K2. In this way, when the first electrode 41 is formed on the side of the second insulating layer 22 away from the substrate 00, the first electrode 41 entering the first opening K1 can form an electrical connection with the drain of the transistor 10, thereby improving the reliability of the electrical connection between the first electrode 41 and the transistor 10. In addition, in the process of forming the first opening K1, due to the blocking effect of the auxiliary pad layer 30, the phenomenon of side engraving of the first opening K1 at the junction of the first insulating layer 21 and the second insulating layer 22 can be avoided to a large extent, so it is helpful to avoid or reduce the phenomenon of unreliable connection between the first electrode 41 and the transistor 10 caused by side engraving, so it is helpful to improve the connection reliability between the first electrode 41 and the transistor 10. When the array substrate 100 provided by the present invention is applied to a display product, it can avoid or reduce the occurrence of dark spot defects, so it is helpful to improve the display reliability and production yield of the product.

FIG8 is another schematic diagram of a film layer of the array substrate 100 in FIG2 , and this embodiment shows another solution of the first opening K1 and the drain of the transistor 10. In an optional embodiment of the present invention, along the thickness direction of the array substrate 100, the drain of the transistor 10 is located in the second opening K2; the orthographic projection of the first opening K1 on the substrate 00 is located within the orthographic projection range of the drain on the substrate 00.

Specifically, when the first opening K1 exposing the drain of the transistor 10 is formed on the planar layer 50, the aperture of the first opening K1 is set larger in this embodiment so that the drain of the transistor 10 is completely exposed, that is, the drain of the transistor 10 is completely located in the first opening K1. When the first opening K1 is formed again, this embodiment defines that the orthographic projection of the first opening K1 on the substrate 00 is located within the orthographic projection range of the drain of the transistor 10 on the substrate 00, which is conducive to increasing the contact area between the portion of the first electrode 41 located in the first opening K1 and the drain of the transistor 10, thereby facilitating the improvement of the electrical connection reliability between the first electrode 41 and the transistor 10.

FIG9 is a flowchart of manufacturing an array substrate 100 provided in an embodiment of the present invention. Referring to FIG9 , based on the same inventive concept, the present invention further provides a method for manufacturing the array substrate 100, including:

S201, providing a substrate 00, and manufacturing a transistor layer 11 on the substrate 00, wherein the transistor layer 11 includes a plurality of transistors 10. Please refer to FIG. 10, which is a schematic structural diagram of an intermediate product formed in the manufacturing process of the array substrate 100 provided in an embodiment of the present invention;

Optionally, after forming the transistor layer 11 on the substrate 00, the step further includes forming a planar layer 50 on the side of the transistor layer 11 facing away from the substrate 00, and forming a second opening K2 on the planar layer 50, wherein the second opening K2 overlaps with the drain of the transistor 10 along the thickness direction of the substrate 00.

S202, forming a first insulating layer 21 on the side of the transistor layer 11 away from the substrate 00, specifically, forming the first insulating layer 21 on the side of the flat layer 50 away from the substrate 00, at this time, at least part of the first insulating layer 21 will be filled in the second opening K2. Please refer to Figure 11, which is another structural schematic diagram of an intermediate product formed in the process of manufacturing the array substrate 100 provided in an embodiment of the present invention;

S203, forming an auxiliary layer 31 on the side of the first insulating layer 21 away from the substrate 00, and the auxiliary layer 31 overlaps with the drain of the transistor 10 along the thickness direction of the array substrate 100. Please refer to FIG. 12, which is another structural schematic diagram of an intermediate product formed in the process of manufacturing the array substrate 100 provided in an embodiment of the present invention;

S204, forming a second insulating layer 22 on a side of the auxiliary layer 31 away from the first insulating layer 21, referring to FIG. 13, which is another structural schematic diagram of an intermediate product formed in the manufacturing process of the array substrate 100 provided in an embodiment of the present invention;

S205, etching the first insulating layer 21, the auxiliary layer 31 and the second insulating layer 22 through an etching process to form a first opening K1 and an auxiliary pad layer 30, wherein the auxiliary pad layer 30 surrounds the first opening K1, and the first opening K1 exposes the drain of the transistor 10 and the side wall of the auxiliary pad layer 30. Please refer to FIG. 14, which is another schematic structural diagram of an intermediate product formed in the manufacturing process of the array substrate 100 provided in an embodiment of the present invention;

S206 , forming a first electrode 41 on the side of the second insulating layer 22 facing away from the substrate 00 , so that at least a portion of the first electrode 41 is located in the first opening K1 , contacts the side wall of the auxiliary pad layer 30 , and is electrically connected to the drain of the transistor 10 , please refer to FIG. 3 .

Specifically, in the manufacturing method of the array substrate 100 provided in the embodiment of the present invention, an auxiliary layer 31 is introduced between the first insulating layer 21 and the second insulating layer 22, and the first insulating layer 21, the auxiliary layer 31 and the second insulating layer 22 are etched by an etching process to form the first opening K1. The etched auxiliary layer 31 forms an auxiliary pad layer 30 surrounding the first opening K1. The introduction of the auxiliary layer 31 effectively reduces or avoids the phenomenon that the first opening K1 is side-etched at the junction of the first insulating layer 21 and the second insulating layer 22, so it is helpful to avoid or reduce the phenomenon that the connection between the first electrode 41 and the transistor 10 is unreliable due to the side etching. In addition, the method of forming the first opening K1 by an etching process is not only helpful to avoid the occurrence of dark spot defects, but also helpful to simplify the production process and improve production efficiency.

Continuing to refer to Figure 12, in an optional embodiment of the present invention, after the first insulating layer 21 is formed on the side of the transistor layer 11 facing away from the substrate 00 and before the second insulating layer 22 is formed on the side of the auxiliary layer 31 facing away from the first insulating layer 21, it also includes: forming a second electrode 42 on the side of the first insulating layer 21 facing away from the substrate 00, so that the second electrode 42 is insulated from the auxiliary layer 31, and the second electrode 42 has the same thickness as the auxiliary layer 31.

Optionally, the second electrode 42 and the auxiliary pad layer 30 are both located between the first insulating layer 21 and the second insulating layer 22. In the actual manufacturing process, after the second electrode 42 and the auxiliary pad layer 30 are formed on the first insulating layer 21, the second insulating layer 22 is formed on the side of the second electrode 42 and the auxiliary pad layer 30 away from the first insulating layer 21. In the embodiment of the present invention, when the thickness of the auxiliary pad layer 30 and the second electrode 42 are the same, when the second insulating layer 22 is formed on the side of the auxiliary pad layer 30 and the second electrode 42 away from the first insulating layer 21, it is beneficial to ensure the flatness of the surface of the side of the second insulating layer 22 away from the first insulating layer 21, thereby facilitating the flatness of the second electrode 42 formed on the second insulating layer 22, and further facilitating the display uniformity of the display product when the array substrate 100 is applied to the display product.

In an optional embodiment of the present invention, the second electrode 42 is produced on the side of the first insulating layer 21 facing away from the substrate 00, specifically: a first mask is set on the side of the first insulating layer 21 facing away from the substrate 00, and the auxiliary layer 31 and the second electrode 42 are simultaneously formed on the side of the first insulating layer 21 facing away from the substrate 00 by using the first mask.

Specifically, in the array substrate 100 provided by the embodiment of the present invention, when the auxiliary pad layer 30 and the second electrode 42 are both arranged between the first insulating layer 21 and the second insulating layer 22, in the process of forming the auxiliary pad layer 30 and the second electrode 42 on the first insulating layer 21, the auxiliary pad layer 30 and the second electrode 42 are produced using the same mask plate in the same production process. In this way, there is no need to introduce another mask plate and production process for the auxiliary pad layer 30. The production of the auxiliary pad layer 30 can be completed in the process of producing the second electrode 42, which is beneficial to simplify the overall production process of the array substrate 100 and improve the production efficiency of the entire array substrate.

Based on the same inventive concept, the present invention further provides a display device 300. FIG. 15 is a schematic structural diagram of a display device 300 provided by an embodiment of the present invention. The display device 300 includes an array substrate 100 provided by any of the above embodiments of the present invention.

It is understandable that the display device 300 provided in the embodiment of the present invention may be a computer, a mobile phone, a tablet, or other display device 300 with a display function, and the present invention does not specifically limit this. The display device 300 provided in the embodiment of the present invention has the beneficial effects of the array substrate 100 provided in the embodiment of the present invention, and the specific description of the display panel in the above embodiments can be referred to, and this embodiment will not be repeated here.

In summary, the array substrate and the manufacturing method thereof, and the display device provided by the present invention achieve at least the following beneficial effects:

In the array substrate and display device provided by the present invention, a first insulating layer and a second insulating layer and a first opening penetrating the first insulating layer and the second insulating layer are provided on the side of the transistor of the array substrate facing away from the substrate, and at least a portion of the first electrode is located in the first opening to form an electrical connection with the drain of the transistor. In particular, the present invention introduces an auxiliary pad layer between the first insulating layer and the second insulating layer, the auxiliary pad layer is arranged around the first opening, and the first opening exposes the side wall of the auxiliary pad layer, so that when the first opening is formed by etching, due to the blocking effect of the auxiliary pad layer, the phenomenon of side engraving of the first opening at the junction of the first insulating layer and the second insulating layer can be avoided to a large extent, so it is helpful to avoid or reduce the phenomenon of unreliable connection between the first electrode and the transistor caused by side engraving, so it is helpful to improve the connection reliability between the first electrode and the transistor, avoid or reduce the occurrence of dark spot defects, so it is helpful to improve the display reliability and production yield of the product.

In the manufacturing method of the array substrate provided by the embodiment of the present invention, an auxiliary layer is introduced between the first insulating layer and the second insulating layer, and the first insulating layer, the auxiliary layer and the second insulating layer are etched by an etching process to form a first opening, and the etched auxiliary layer forms an auxiliary pad layer surrounding the opening. The introduction of the auxiliary layer effectively reduces or avoids the phenomenon that the first opening forms side etching at the junction of the first insulating layer and the second insulating layer, so it is helpful to avoid or reduce the phenomenon that the connection between the first electrode and the transistor is unreliable due to side etching. The method of forming the first opening by an etching process is not only helpful to avoid the occurrence of dark spot defects, but also helpful to simplify the production process and improve production efficiency.

Although some specific embodiments of the present invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that the above embodiments may be modified without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims (12)

1. An array substrate, comprising: A substrate and a transistor disposed on one side of the substrate; A first insulating layer and a second insulating layer are provided on a side of the transistor away from the substrate, wherein the first insulating layer is located between the second insulating layer and the substrate along a thickness direction of the array substrate; A first opening, along a thickness direction of the array substrate, the first opening penetrating the first insulating layer and the second insulating layer and exposing the drain of the transistor; an auxiliary pad layer, located between the first insulating layer and the second insulating layer, the auxiliary pad layer being disposed around the first opening, and the first opening exposing a side wall of the auxiliary pad layer; The first electrode is located on a side of the second insulating layer away from the substrate, and at least a portion of the first electrode is located in the first opening, in contact with a side wall of the auxiliary pad layer and electrically connected to a drain of the transistor. 2 . The array substrate according to claim 1 , wherein the auxiliary pad layer is a conductive material layer. 3 . 3. The array substrate according to claim 1 is characterized in that it also includes a second electrode located between the first insulating layer and the second insulating layer, the second electrode is insulated from the auxiliary pad layer, and along the thickness direction of the array substrate, the auxiliary pad layer has the same thickness as the second electrode. 4 . The array substrate according to claim 3 , wherein the auxiliary pad layer and the second electrode are manufactured using the same mask plate in the same manufacturing process. 5. The array substrate according to claim 1, wherein the first opening exposes at least a portion of the surface of the auxiliary pad layer facing away from the substrate, and the first electrode is also in contact with at least a portion of the surface of the auxiliary pad layer facing away from the substrate. 6 . The array substrate according to claim 5 , wherein at least a portion of a surface of the auxiliary pad layer facing away from the substrate is covered by the second insulating layer. 7. The array substrate according to claim 1 is characterized in that it also includes a planar layer located between the transistor and the first insulating layer, the planar layer includes a second opening exposing the drain of the transistor, and along the thickness direction of the array substrate, the first opening and the second opening overlap. 8. The array substrate according to claim 7, characterized in that, along the thickness direction of the array substrate, the drain of the transistor is located in the second opening; and the orthographic projection of the first opening on the substrate is located within the orthographic projection range of the drain on the substrate. 9. A method for manufacturing an array substrate, comprising: Providing a substrate, and manufacturing a transistor layer on the substrate, wherein the transistor layer includes a plurality of transistors; Forming a first insulating layer on a side of the transistor layer facing away from the substrate; An auxiliary layer is formed on a side of the first insulating layer away from the substrate, wherein the auxiliary layer overlaps with the drain of the transistor along a thickness direction of the array substrate; forming a second insulating layer on a side of the auxiliary layer away from the first insulating layer; Etching the first insulating layer, the auxiliary layer and the second insulating layer through an etching process to form a first opening and an auxiliary pad layer, wherein the auxiliary pad layer surrounds the first opening, and the first opening exposes the drain of the transistor and the sidewall of the auxiliary pad layer; A first electrode is formed on a side of the second insulating layer away from the substrate, so that at least a portion of the first electrode is located in the first opening, contacts the side wall of the auxiliary pad layer and is electrically connected to the drain of the transistor. 10. The method for manufacturing an array substrate according to claim 9 is characterized in that after the first insulating layer is formed on the side of the transistor layer away from the substrate and before the second insulating layer is formed on the side of the auxiliary layer away from the first insulating layer, it also includes: forming a second electrode on the side of the first insulating layer away from the substrate, so that the second electrode is insulated from the auxiliary layer, and the second electrode has the same thickness as the auxiliary layer. 11. The method for manufacturing an array substrate according to claim 9 is characterized in that a second electrode is manufactured on a side of the first insulating layer away from the substrate, specifically: a first mask is set on a side of the first insulating layer away from the substrate, and the auxiliary layer and the second electrode are simultaneously formed on the side of the first insulating layer away from the substrate by using the first mask. 12. A display device, comprising the array substrate according to any one of claims 1 to 8.