CN103077895A - Laterally diffused metal oxide semiconductor (LDMOS) transistor and formation method thereof - Google Patents
Laterally diffused metal oxide semiconductor (LDMOS) transistor and formation method thereof Download PDFInfo
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
- H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
- H10D62/126—Top-view geometrical layouts of the regions or the junctions
- H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D64/251—Source or drain electrodes for field-effect devices
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/113—Isolations within a component, i.e. internal isolations
- H10D62/115—Dielectric isolations, e.g. air gaps
- H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
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Abstract
一种LDMOS晶体管及其形成方法，所述LDMOS晶体管的形成方法包括：提供半导体衬底，并在所述半导体衬底内形成第一导电类型的阱区；在所述阱区内形成第一导电类型的重掺杂区，并在所述重掺杂区两侧的阱区内形成第二导电类型的漂移区；在所述漂移区内形成第二导电类型的漏极区域；在所述重掺杂区内形成第一导电类型的隔离件，并在所述隔离件两侧的重掺杂区内形成第二导电类型的源极区域；在半导体衬底上形成与源极区域连接的金属插塞。本发明所形成的LDMOS晶体管安全工作范围较大，相同面积下导通电阻小、内耗小。
An LDMOS transistor and a method for forming the same, the method for forming the LDMOS transistor includes: providing a semiconductor substrate, and forming a well region of a first conductivity type in the semiconductor substrate; forming a first conductivity type in the well region type of heavily doped region, and form a drift region of the second conductivity type in the well region on both sides of the heavily doped region; form a drain region of the second conductivity type in the drift region; A spacer of the first conductivity type is formed in the doped region, and a source region of the second conductivity type is formed in the heavily doped region on both sides of the spacer; a metal layer connected to the source region is formed on the semiconductor substrate. plug. The LDMOS transistor formed by the invention has a large safe working range, small conduction resistance and small internal friction under the same area.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to ldmos transistor and forming method thereof.
Background technology
Lateral double diffusion metal oxide semiconductor (lateral double diffusion MOS, LDMOS) transistor, owing to possessing high-breakdown-voltage, the characteristic with complementary metal oxide semiconductors (CMOS) (CMOS) process compatible is widely used in the power device.
The transistorized source region of conventional MOS and drain region are symmetrical with respect to grid; And the drain region in the ldmos transistor than source electrode further from grid, long lightly doped region is arranged between drain region and grid, be called as the drift region.When ldmos transistor is missed high pressure in the source, bear higher voltage drop by the drift region, obtain the purpose of high-breakdown-voltage.
With reference to figure 1, the schematic diagram for N-type ldmos transistor in the existing technique comprises:
Be positioned at the P type well region 103 of Semiconductor substrate 101;
Be positioned at the P type heavily doped region 105 of P type well region 103;
Be positioned at the N-type drift region 107 of P type well region 103, described N-type drift region 107 is adjacent with described P type heavily doped region 105;
Be positioned at the N-type source region 111 of P type heavily doped region 105; Be positioned at the N-type drain region 113 of N-type drift region 107;
Be positioned at the fleet plough groove isolation structure 115 of N-type drift region 107, described fleet plough groove isolation structure 115 is between N-type source region 111 and N-type drain region 113 and adjacent with described N-type drain region 113;
Be positioned at the grid structure 117 of Semiconductor substrate 101 upper surfaces, described grid structure 117 cover part P type heavily doped region 105 and part fleet plough groove isolation structures 115;
Wherein, described grid structure 117 comprises the gate dielectric layer 117a that is positioned at Semiconductor substrate 101 upper surfaces, is positioned at the grid 117b on the described gate dielectric layer 117a and is positioned at gate dielectric layer 117a and the side wall 117c of grid 117b semiconductor substrates on two sides 101 upper surfaces.
When the N-type ldmos transistor is opened, apply voltage to N-type source region 111 and N-type drain region 113, electric current can pass through P type heavily doped regions 105, N-type drift region 107 by N-type source region 111, and is gathered in N-type drain region 113.Because the existence of fleet plough groove isolation structure 115, the Electric Field Distribution in the N-type drift region 107 changes, and fleet plough groove isolation structure 115 has born larger electric field, and then can obtain higher LDMOS puncture voltage.
Yet the shared area of the ldmos transistor of said structure is large, complex process.
In being the Chinese patent application of CN101266930A, publication number can also find more information relevant with ldmos transistor.
Summary of the invention
The problem that the present invention solves provides a kind of ldmos transistor and forming method thereof, reduces the conducting resistance of the ldmos transistor that forms, and reduces the in-fighting of ldmos transistor.
For addressing the above problem, the invention provides a kind of formation method of ldmos transistor, comprising: Semiconductor substrate is provided, and in described Semiconductor substrate, forms the well region of the first conduction type; In described well region, form the heavily doped region of the first conduction type, and in the well region of described heavily doped region both sides, form the drift region of the second conduction type; In described drift region, form the drain region of the second conduction type; In described heavily doped region, form the separator of the first conduction type, and in the heavily doped region of described separator both sides, form the source region of the second conduction type; Form the metal plug that is connected with the source region in Semiconductor substrate.
Optionally, forming the metal plug that is connected with the source region in Semiconductor substrate comprises: form the metal plug that connects source region, separator both sides in Semiconductor substrate.
Optionally, form before the drain region of the second conduction type in described drift region, also comprise: form fleet plough groove isolation structure in described drift region, described fleet plough groove isolation structure is positioned at described drain region near the drift region of heavily doped region one side.
Optionally, after forming fleet plough groove isolation structure, also comprise: form grid structure in described Semiconductor substrate, described grid structure cover part heavily doped region and part fleet plough groove isolation structure.
Optionally, described grid structure comprises: be positioned at gate dielectric layer on the Semiconductor substrate, be positioned on the described gate dielectric layer grid and be positioned at gate dielectric layer and the side wall of grid semiconductor substrates on two sides upper surface; Form before the metal plug that connects source region, separator both sides in Semiconductor substrate, also comprise: form the functional layer that covers described Semiconductor substrate upper surface and top portions of gates.
Optionally, the material of described functional layer is cobalt silicide, titanium silicide or nickle silicide.
Optionally, the material of described metal plug is copper or tungsten.
Optionally, described the first conduction type is N-type or P type, and described the first conduction type is different from the second conduction type.
Accordingly, the present invention also provides a kind of ldmos transistor, comprising: Semiconductor substrate; Be positioned at the well region of the first conduction type of Semiconductor substrate; Be positioned at the heavily doped region of the first conduction type of described well region; Be positioned at the drift region of the second conduction type of described heavily doped region both sides well region; Be positioned at the separator of the first conduction type of described heavily doped region; Be positioned at the source region of the second conduction type of described separator both sides heavily doped region; Be positioned at the drain region of the second conduction type of described drift region; Fleet plough groove isolation structure between described source region and drain region in the drift region, described fleet plough groove isolation structure and drain region are adjacent; Be positioned at the grid structure on the described Semiconductor substrate, described grid structure cover part heavily doped region 105 and part fleet plough groove isolation structure; Be positioned at the metal plug that connects described source region on the Semiconductor substrate.
Optionally, described metal plug connects the source region of separator both sides at least.
Optionally, described grid structure comprises: be positioned at gate dielectric layer on the Semiconductor substrate, be positioned on the described gate dielectric layer grid and be positioned at gate dielectric layer and the side wall of grid semiconductor substrates on two sides upper surface, described ldmos transistor also comprises: the functional layer that covers described Semiconductor substrate upper surface and top portions of gates.
Optionally, the material of described functional layer is cobalt silicide, titanium silicide or nickle silicide.
Optionally, the material of described metal plug is copper or tungsten.
Optionally, described the first conduction type is N-type or P type, and described the first conduction type is different from the second conduction type.
Compared with prior art, technical solution of the present invention has the following advantages:
Share the heavily doped region of first conduction type by the source region that makes two identical ldmos transistors, save the shared area of ldmos transistor, simultaneously, simplified the formation technique of ldmos transistor.
Further, after two ldmos transistors that share the heavily doped region of first conduction type in the source region form, form the metal plug that connects source region, separator both sides in Semiconductor substrate, make two ldmos transistors share a metal plug, when not violating design specification, dwindle the distance between the separator and source region in the heavily doped region as far as possible, under the condition that electric current is identical in Semiconductor substrate, strengthened the difficulty that parasitic triode is opened in the Semiconductor substrate, made formed ldmos transistor have larger range of safety operation.
In addition, owing to having increased the cross-sectional area of the metal plug that is connected with the source region, the resistance of single metal connector reduces, in the situation that the Semiconductor substrate area is identical, can increase the quantity that is arranged at metal plug on the ldmos transistor source region, reduce the conducting resistance of ldmos transistor, reduced the in-fighting of the ldmos transistor that forms.
Description of drawings
Fig. 1 is the cross-sectional view of ldmos transistor in the existing technique;
Fig. 2 is the schematic flow sheet of formation method one execution mode of ldmos transistor of the present invention;
Fig. 3～Fig. 9, Figure 11～Figure 13 are the schematic diagram of an embodiment of formation method of ldmos transistor of the present invention;
Figure 10 is the schematic diagram of the range of safety operation of N-type ldmos transistor among Fig. 7, Fig. 8 and Figure 12;
Figure 14～19 are the schematic diagram of another embodiment of formation method of ldmos transistor of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Set forth in the following description a lot of details so that fully understand the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not been subjected to the restriction of following public specific embodiment.
Hereinafter, be the demonstration purpose, product embodiments reference method embodiment describes.Yet, should be appreciated that the realization of product and method among the present invention is independent mutually.That is to say, disclosed product embodiments can prepare according to additive method, and disclosed embodiment of the method is not limited only to realize product embodiments.
Just as described in the background section, large, the complex process of the shared area of the ldmos transistor that forms of existing technique.
For defects, the invention provides a kind of formation method of ldmos transistor, the heavily doped region that shares first conduction type by the source region that makes identical ldmos transistor is saved the shared area of ldmos transistor; And, in the identical ldmos transistor situation that forms same number, can reduce the number that forms heavily doped region, simplified the formation technique of ldmos transistor.
With reference to figure 2, the schematic flow sheet for the formation method of ldmos transistor of the present invention comprises:
Step S1 provides Semiconductor substrate, and forms the well region of the first conduction type in described Semiconductor substrate;
Step S2 forms the heavily doped region of the first conduction type in described well region, and forms the drift region of the second conduction type in the well region of described heavily doped region both sides;
Step S3 forms fleet plough groove isolation structure in described drift region, described fleet plough groove isolation structure is positioned at described drain region near the drift region of heavily doped region one side;
Step S4 forms grid structure in described Semiconductor substrate, described grid structure cover part heavily doped region and part fleet plough groove isolation structure;
Step S5, the drain region of formation the second conduction type in described drift region;
Step S6 forms the separator of the first conduction type in described heavily doped region, and forms the source region of the second conduction type in the heavily doped region of described separator both sides;
Step S7 forms the functional layer that covers described Semiconductor substrate upper surface and top portions of gates;
Step S8 forms the metal plug that is connected with the source region in Semiconductor substrate.
Need to prove, the present invention is the sequencing of conditioning step S5 and step S6 not, in other embodiments, also can carry out first step S6 and carry out step S5 again, and it does not affect protection scope of the present invention.
Embodiment one
The present embodiment describes the formation method of ldmos transistor of the present invention to form the N-type ldmos transistor as example (that is, the first conduction type is the P type, and the second conduction type is N-type).
With reference to figure 3, at first, provide Semiconductor substrate 201, and at the described Semiconductor substrate 201 interior well regions 203 that form the P types; Then, at the heavily doped regions 205 of described well region 203 interior formation P types, and in the drift region 207 of the well region 203 interior formation N-types of described heavily doped region 205 both sides; Follow, at described drift region 207 interior formation fleet plough groove isolation structures 215, described fleet plough groove isolation structure 215 is positioned at the drift region 207 near heavily doped region 205 1 sides again; Follow again, 201 form grid structure 217 on described Semiconductor substrate, described grid structure 217 cover part heavily doped regions 205 and part fleet plough groove isolation structure 215, described grid structure 217 further comprise the gate dielectric layer 217a that is positioned at described Semiconductor substrate 201 upper surfaces, are positioned at the grid 217b on the described gate dielectric layer 217a and are positioned at gate dielectric layer 217a and the side wall 217c of grid 217b semiconductor substrates on two sides 201 upper surfaces; Follow again, drain region 213 in described drift region 207 interior formation N-types, separator 209 in described heavily doped region 205 interior formation P types, and in the source region 211 of the heavily doped region 205 interior formation N-types of described separator 209 both sides, described separator 209 is used for connecting the Semiconductor substrate 201 of ldmos transistor.
Particularly, described Semiconductor substrate 201 can be body silicon substrate, germanium silicon substrate or silicon-on-insulator substrate.In the present embodiment, described Semiconductor substrate 201 is the body silicon substrate.
The well region 203 of described P type, heavily doped region 205 and separator 209 can be by carrying out the ion doping formation that conduction type is the P type to Semiconductor substrate 201; The drift region 207 of described N-type, source region 211 and drain region 213 can be by carrying out the ion doping formation that conduction type is N-type to Semiconductor substrate 201.Described conduction type is that the ion of P type can comprise boron ion, boron difluoride ion etc., and described conduction type is that the ion of N-type can comprise phosphonium ion, arsenic ion etc.Described ion doping technique is known by those skilled in the art, does not repeat them here.
With reference to figure 4, form the functional layer 219 that covers described Semiconductor substrate 201 upper surfaces and grid 217b top.
In the present embodiment, the material of described functional layer 219 is cobalt silicide, titanium silicide or nickle silicide, and the method that forms described functional layer 219 is chemical vapor deposition method.Described functional layer 219 can reduce the contact resistance between source region 211 and the follow-up metal plug that is formed at 211 tops, source region, and then reduces the conducting resistance of ldmos transistor.
Continuation forms dielectric layer 221 with reference to figure 4 in described functional layer 219, and the upper surface of described dielectric layer 221 is not less than the top of described grid structure 217.
In the present embodiment, the material of described dielectric layer 221 can be low-k materials or ultralow k material, forms described dielectric layer 221 and can be chemical vapor deposition method.
With reference to figure 5, form the opening 220 run through Fig. 4 medium layer 221 thickness, the source region 211 in described opening 220 and the heavily doped region 205 over against.
In the present embodiment, can comprise the steps: at described dielectric layer 221 interior formation openings 220
Form the photoresist layer (not shown) at described dielectric layer 221;
Graphical described photoresist layer, in described photoresist layer, form litho pattern, described litho pattern respectively with Semiconductor substrate 201 in each source region 211 corresponding with the follow-up shape that is formed at the metal plug in the dielectric layer 221 over against, the shape of described litho pattern;
Take described photoresist layer as mask, along the described dielectric layer 221 of litho pattern etching, form and run through the described opening 220 of stating dielectric layer 221 thickness;
Remove described photoresist layer.
With reference to figure 6, at described opening 220 interior filling metal materials, form metal plug 218.
In the present embodiment, the material of described metal plug 218 is copper or tungsten, can be physical gas-phase deposition in the method for described opening 222 interior filling metal materials.
With reference to figure 7, for being formed with the vertical view of the Semiconductor substrate of ldmos transistor among a plurality of Fig. 6, Fig. 6 is that Fig. 7 is along the cutaway view of AA direction.
In the present embodiment, separator 209 in the adjacent two row ldmos transistors in the heavily doped region 205 is a bearing of trend bar-shaped zone identical with the bearing of trend of grid structure 217, source region, separator 209 both sides 211 is connected with external power source by metal plug 218 respectively, applies voltage with the source region 211 to ldmos transistor.
As shown in Figure 6, in order to reduce the contact resistance between metal plug and source region 211, drain region 213 and the grid 217b, described grid 217b top and Semiconductor substrate 201 upper surfaces also are formed with functional layer 219.The material of described functional layer 219 is metal silicide, such as cobalt silicide, titanium silicide or nickle silicide.
For the separator 209 among Fig. 7, its metal silicide by separator 209 surfaces links to each other with metal plug 218 on the source region 211, to apply voltage to it.
In other embodiments, the vertical view that is formed with the Semiconductor substrate of a plurality of above-mentioned ldmos transistors also can be as shown in Figure 8, and the separator 209 in the adjacent two row ldmos transistors in the heavily doped region is several rectangular region of arranging along the bearing of trend of grid structure 217.Fig. 8 along the cutaway view of BB direction as shown in Figure 9.
For the separator 209 among Fig. 8, then need at least one metal plug 225 all is set on each separator 209, to apply voltage to it.
With reference to Figure 10, show respectively when the voltage Vgs between the N-type ldmos transistor grid structure 217 and source region 211 is 5 volts (V) among Fig. 7 and Fig. 8, the range of safety operation of N-type ldmos transistor among Fig. 7 and Fig. 8, electric current I ds(unit between N-type ldmos transistor drain region 213 and the source region 211 among Fig. 7 and Fig. 8: peace/centimetre) and voltage Vds(unit: lie prostrate) relation satisfy respectively the maximum voltage Vds that can bear between the N-type ldmos transistor drain region 213 and source region 211 among curve 331 and 333, Fig. 7 and Fig. 8 and be respectively 22 volts and 14 volts.
As shown in Figure 10, although the method for above-mentioned formation ldmos transistor has reduced the shared area of single ldmos transistor, simplified the formation technique of ldmos transistor, its range of safety operation is less.
The inventor finds through research, and the range of safety operation of the ldmos transistor that above-mentioned technique forms is less to be owing to being arranged at that the cross-sectional area of ldmos transistor upper metal connector 218 is less, resistance causes more greatly; And, because the distance between the metal plug 218 need to be greater than certain threshold value (take 0.18um technique as example, distance should be greater than 0.25um between the adjacent metal connector, otherwise possibility short circuit between the metal plug), be so limited, be arranged at the limited amount of the metal plug 218 on the Semiconductor substrate 201, can't reduce by abundant metal plug 218 is set the conducting resistance of ldmos transistor, cause the conducting resistance of ldmos transistor larger, the in-fighting of the ldmos transistor that forms is larger.
In view of the foregoing, the inventor has done further improvement to the formation technique of above-mentioned ldmos transistor in the present embodiment.In forming Fig. 4 after the ldmos transistor, with reference to Figure 11, at the 221 interior formation openings 222 of dielectric layer described in Fig. 4, the separator 209 in described opening 222 and the heavily doped region 205 and the source region 211 of separator 209 both sides over against.
In the present embodiment, the position of Fig. 5 dielectric layer 221 inner openings 220 is different from the position of Figure 11 dielectric layer 221 inner openings 222, but it is similar to form technique, does not repeat them here.
With reference to Figure 12, at the 222 interior filling metal materials of opening described in Figure 11, form metal plug 223.
In the present embodiment, the material of described metal plug 223 is copper or tungsten, can be physical gas-phase deposition in the method for described opening 222 interior filling metal materials.
The source region 211 of described separator 209 and separator 209 both sides connects by a metal plug 223, make two ldmos transistors share a metal plug 223, when not violating design specification, dwindled the distance between the separator 209 and source region 211 in the heavily doped region 205, under the condition that electric current is identical in Semiconductor substrate 201, strengthened the difficulty that parasitic triode is opened in the Semiconductor substrate 201, made formed ldmos transistor have larger range of safety operation.
In addition, because the cross-sectional area of the metal plug 223 that is connected with source region 211 is larger, the resistance of single metal connector 223 reduces, when the source region 211 to an equal number ldmos transistor applies voltage, the quantity of required formation metal plug 223 reduces by half, to vacate more large-area Semiconductor substrate 201 surfaces, satisfying under the prerequisite of design specification, can in identical Semiconductor substrate 201 areas, increase the quantity that is arranged at metal plug 223 on the ldmos transistor source region 211, further reduce the conducting resistance of ldmos transistor, reduced the in-fighting of the ldmos transistor that forms.
With reference to Figure 13, for being formed with the vertical view of the Semiconductor substrate of ldmos transistor among a plurality of Figure 12, separator 209 among Figure 13 between the two row ldmos transistor source regions 211 of a shared metal plug 223 is a bar-shaped zone identical with grid structure 217 bearing of trends, separator 209 can be connected with metal plug 223 by the functional layer 219 of its top, and then is connected with external power source.
Figure 12 is that Figure 13 is along the cutaway view of CC direction.With reference to Figure 10, when also showing the grid structure 217 of N-type ldmos transistor among Figure 12 and the voltage Vgs between the source region 211 and being 5 volts (V), electric current I ds(unit between N-type ldmos transistor drain region 213 and the source region 211 among Figure 12: peace/centimetre) and voltage Vds(unit: relation volt) satisfies curve 335 among Figure 10, and the maximum voltage Vds that can bear between N-type ldmos transistor drain region 213 and the source region 211 among Figure 12 can reach about 48 volts.
Hence one can see that, shares a metal plug 223 by making two ldmos transistors, increased the range of safety operation of ldmos transistor, and the performance of ldmos transistor has had very large improvement.
As shown in figure 12, the formed N-type ldmos transistor of the present embodiment comprises:
Be positioned at the well region 203 of the P type of Semiconductor substrate 201;
Be positioned at the heavily doped region 205 of the P type of described well region;
Be positioned at the drift region 207 of the N-type of described heavily doped region 205 both sides well regions 203;
Be positioned at the separator 209 of the P type of described heavily doped region 205;
Be positioned at the source region 211 of the N-type of described separator 209 both sides heavily doped regions 205;
Be positioned at the drain region 213 of the N-type of described drift region 207;
Fleet plough groove isolation structure 215 between described source region 211 and drain region 213 in the drift region 207, described fleet plough groove isolation structure 215 is adjacent with drain region 213;
Be positioned at the grid structure 217 on the described Semiconductor substrate 201, described grid structure 217 cover part heavily doped regions 205 and part fleet plough groove isolation structure 215;
Be positioned at the metal plug 223 that connects separator 209 and source region, both sides 211 thereof on the Semiconductor substrate 201.
Wherein, described grid structure 217 comprises the gate dielectric layer 217a that is positioned at described Semiconductor substrate 201 upper surfaces, is positioned at the grid 217b on the described gate dielectric layer 217a and is positioned at gate dielectric layer 217a and the side wall 217c of grid 217b semiconductor substrates on two sides 201 upper surfaces.
In the present embodiment, the top of described Semiconductor substrate 201 upper surfaces and grid 217b also is formed with functional layer 219, the material of described functional layer 219 is cobalt silicide, titanium silicide or nickle silicide, in order to reducing the contact resistance between metal plug 223 and the source region 211, and then reduce the conducting resistance of ldmos transistor.
Need to prove, in the present embodiment, described metal plug 223 also is connected with described separator 209 by functional layer 219, in order to apply voltage to separator 209.
Also need to prove, also be formed with the metal plug (not shown) on described grid structure 217, the drain region 213, in order to apply voltage to grid structure 217, drain region 213.The metal plug that is positioned on grid structure 217, the drain region 213 can form simultaneously with metal plug 223, also can form respectively, and it does not limit protection scope of the present invention.
In other embodiments, can also change the conduction type of above-mentioned well region 203, heavily doped region 205 and separator 209 into N-type by the P type, change the conduction type of drift region 207, source region 211 and drain region 213 into the P type, to form P type ldmos transistor.
Technical scheme in the present embodiment, be formed in the same heavily doped region by the source region with adjacent two identical ldmos transistors (N-type ldmos transistor or P type ldmos transistor), saved the area of single ldmos transistor, and reduced the processing step that forms heavily doped region, simplified the formation technique that forms ldmos transistor.
Better, separator 209 in the heavily doped region 205 and the source region 211 that is positioned at separator 209 both sides are connected with external power source by a metal plug 223, when not violating design specification, dwindled the distance between the separator 209 and source region 211 in the heavily doped region 205, made the range of safety operation of the ldmos transistor that forms larger.And, since connect separator 209 with and the cross-sectional area of the metal plug 223 of the source region 211 of both sides larger, effectively reduced the resistance of single metal connector 223, increased the quantity that can be arranged at metal plug on the unit are Semiconductor substrate 201, reduced the conducting resistance of ldmos transistor, made the in-fighting of ldmos transistor lower.
Embodiment two
The present embodiment describes the formation method of ldmos transistor of the present invention to form P type ldmos transistor as example (that is, the first conduction type is N-type, and the second conduction type is the P type).
With reference to Figure 14, at first, provide Semiconductor substrate 301, and at the well region 303 of described Semiconductor substrate 301 interior formation N-types; Then, at the heavily doped region 305 of described well region 303 interior formation N-types, and in the drift regions 307 of the interior formation of the well region 303 of described heavily doped region 305 both sides P types; Follow, at described drift region 307 interior formation fleet plough groove isolation structures 315, described fleet plough groove isolation structure 315 is positioned at the drift region 307 near heavily doped region 305 1 sides again; Follow again, 301 form grid structure 307 on described Semiconductor substrate, described grid structure 307 cover part heavily doped regions 305 and part fleet plough groove isolation structure 315, described grid structure 317 further comprise the gate dielectric layer 317a that is positioned at described Semiconductor substrate 301 upper surfaces, are positioned at the grid 317b on the described gate dielectric layer 317a and are positioned at gate dielectric layer 317a and the side wall 317c of grid 317b semiconductor substrates on two sides 301 upper surfaces; Follow again, the drain regions 313 of 307 interior formation P types in described drift region, at the separator 309 of described heavily doped region 305 interior formation N-types, and in the source regions 311 of the heavily doped region 305 interior formation P types of described separator 309 both sides.
Particularly, described Semiconductor substrate 301 can be body silicon substrate, germanium silicon substrate or silicon-on-insulator substrate.In the present embodiment, described Semiconductor substrate 301 is the body silicon substrate.The well region 303 of described N-type, heavily doped region 305 and separator 309 can be by carrying out the ion doping formation that conduction type is N-type to Semiconductor substrate 301; The drift region 307 of described P type, source region 311 and drain region 313 can be by carrying out the ion doping formation that conduction type is the P type to Semiconductor substrate 301.Described conduction type is that the ion of P type can comprise boron ion, boron difluoride ion etc.Described conduction type is that the ion of N-type can comprise phosphonium ion, arsenic ion etc.Described ion doping technique is known by those skilled in the art, does not repeat them here.
With reference to Figure 15, for being formed with the vertical view of the Semiconductor substrate of ldmos transistor among a plurality of Figure 14, Figure 15 be Figure 14 along the cutaway view of DD direction, Figure 15 is along the cutaway view of EE direction as shown in figure 16.
With reference to Figure 17 to Figure 19, form dielectric layer 321 in Semiconductor substrate described in Figure 15 301 and grid structure 317, and in described dielectric layer 321, form the metal plug 325 that is connected with separator 309 and the metal plug 323 that is connected with source region 311.Figure 18 and Figure 19 are respectively Figure 17 along the cutaway view of DD direction and EE direction.
Need to prove, form the metal plug 325 be connected with separator 309 with metal plug 323 that source region 311 is connected in, also can form the metal plug (not shown) that is connected with grid structure 317 and drain region 313, to apply voltage to grid structure 317 and drain region 313.
In other embodiments, the metal plug that is connected with grid structure 317 and drain region 313 also can be before metal plug 323 forms or forms afterwards, and it does not limit protection scope of the present invention.
In other embodiments, form before the dielectric layer 321 on described Semiconductor substrate 301 and the grid structure 317, also comprise: form the functional layer (not shown) at described Semiconductor substrate 301 upper surfaces and grid 317b top, with metal plug 323 and the contact resistance between source region 311, metal plug 325 and the separator 309, the further conducting resistance of the reduction ldmos transistor that forms that reduces follow-up formation.The material of described functional layer and formation method please refer to material and the formation method of functional layer 219 among the embodiment one, do not repeat them here.
In the present embodiment, the material of described dielectric layer 321 can be low-k materials or ultralow k material, and described metal plug 323 and 325 material are copper or tungsten, and described metal plug 323 does not overlap with the position of metal plug 325.The method of the formation method of described dielectric layer 321 and metal plug 323 and 325 and embodiment one medium layer 221 and metal plug 223 is similar, does not repeat them here.Described metal plug 323 is used for to the source region 311 and applies voltage, and described metal plug 325 is in order to apply voltage to separator 309.
Shown in Figure 17 to 19, the formed P type of the present embodiment ldmos transistor comprises:
Be positioned at the well region 303 of the N-type of Semiconductor substrate 301;
Be positioned at the heavily doped region 305 of the N-type of described well region;
Be positioned at the drift region 307 of the P type of described heavily doped region 305 both sides well regions 303;
Be positioned at the separator 309 of the N-type of described heavily doped region 305;
Be positioned at the source region 311 of the P type of described separator 309 both sides heavily doped regions 305;
Be positioned at the drain region 313 of the P type of described drift region 307;
Fleet plough groove isolation structure 315 between described source region 311 and drain region 313 in the drift region 307, described fleet plough groove isolation structure 315 is adjacent with drain region 313;
Be positioned at the grid structure 317 on the described Semiconductor substrate 301, described grid structure 317 cover part heavily doped regions 305 and part fleet plough groove isolation structure 315;
Be positioned at the metal plug 323 that connects source region, separator 309 both sides 311 on the Semiconductor substrate 301.
Wherein, described grid structure 317 further comprises the gate dielectric layer 317a that is positioned at Semiconductor substrate 301 upper surfaces, is positioned at the grid 317b on the described gate dielectric layer 317a and is positioned at gate dielectric layer 317a and the side wall 317c of grid 317b semiconductor substrates on two sides 301 upper surfaces.Described Semiconductor substrate 301 upper surfaces and grid 317b top also can be formed with the functional layer (not shown), the material of described functional layer is cobalt silicide, titanium silicide or nickle silicide, in order to reducing the contact resistance between metal plug 323 and the source region 311, and then reduce the conducting resistance of ldmos transistor.
Also need to prove, also be formed with the metal plug (not shown) on described grid structure 317, the drain region 313, in order to apply voltage to grid structure 317, drain region 313.The metal plug that is positioned on grid structure 317, the drain region 313 can form simultaneously with metal plug 323, also can form respectively, and it does not limit protection scope of the present invention.
In other embodiments, can also change the conduction type of above-mentioned well region 303, heavily doped region 305 and separator 309 into the P type by N-type, change the conduction type of drift region 307, source region 311 and drain region 313 into N-type by the P type, to form the N-type ldmos transistor.
Compare with the two row ldmos transistors that share a metal plug 223 among embodiment one Figure 13, the separator 309 that shares between 323 liang of capable ldmos transistor source regions 311 of a metal plug among the present embodiment Figure 17 is along spaced several rectangular region of grid structure 317 bearing of trends, all be formed with metal plug 325 on each separator 309, and then be connected with external power source.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (14)
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| CN114975609A (en) * | 2021-02-24 | 2022-08-30 | 联华电子股份有限公司 | Lateral double-diffused metal-oxide-semiconductor field-effect transistor and method of making the same |
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