CN102568571A - NOR type cache memory and over-erasure verification and repair method thereof - Google Patents

Abstract

The invention discloses a NOR type cache memory and an over-erasure verification and repair method thereof. The method performs an over-erased column verification on a sector of the NOR-gate type cache memory row by row respectively, and performs an over-erased column repair on a column which cannot pass the over-erased column verification. In addition, the method further performs an over-erased bit verification on the columns which can not pass the over-erased column repair and pass the over-erased column verification, and performs an over-erased bit repair on the bits which can not pass the over-erased bit verification. The NOR type cache memory and the over-erasing verification and repair method thereof in the embodiment of the invention can solve the problem of leakage current generated by over-erasing.

Description

NOR gate type cache memory and its over-erased verification and restoration method

technical field

The invention relates to a NOR type stack flash and its over-erased verification and repair method.

Background technique

The design of the NOR-type cache memory includes an erase operation to clear the contents of all memory cells to the same value. However, in the erasing operation, some memory cells may be over-erased, causing the threshold voltage (threshold voltage) of the transistors (such as MOS) in these memory cells to be too low, which is easy to generate leakage current ( leakage).

In order to solve the above-mentioned leakage current problem, it is necessary to deal with the above-mentioned over-erase problem accordingly.

Contents of the invention

An embodiment of the present invention provides a NOR gate type cache memory and its over-erased verification and repair method. In the method, an over-erased row verification is performed row by row on a sector of the NOR-type cache memory, and an over-erased row repair is performed on the rows that cannot pass the over-erased row verification. In addition, the method further implements an over-erased bit verification on the rows that cannot pass the over-erased row and restores the over-erased row verification bit by bit, and performs an over-erased bit verification on the bits that cannot pass the over-erased bit verification. Divide fixes.

The NOR gate type cache memory and its over-erasing verification and repair method of the embodiments of the present invention can solve the leakage current problem caused by over-erasing.

Description of drawings

The drawings described here are used to provide further understanding of the present invention, constitute a part of the application, and do not limit the present invention. In the attached picture:

Fig. 1 is a kind of implementation mode of a memory cell array in the diagram NOR gate type cache memory (NOR type stack flash);

FIG. 2 is a flow chart disclosing an embodiment of the NOR gate type cache memory over-erasing verification and repairing method of the present invention, wherein the over-erasing verification and repairing of a sector is described;

FIG. 3 is a flow chart disclosing an implementation mode of over-erasure verification and repair with “bit” as the object, and the disclosed process 300 can be used to realize step S220 in FIG. 2 ; and

FIG. 4 illustrates an embodiment of the NOR-type cache memory of the present invention.

Figure number:

100～memory cell array

400～NOR gate type cache memory;

402～controller;

BL1...BLM～bit line;

S202...S220～multiple steps of sector over-erasure verification and repair;

S302...S316～about steps S220—the over-erasure verification and repair of the “bit” of the current “test line” as the object—multiple steps of an implementation;

WL1...WLN ~ word line.

Detailed ways

In order to make the above-mentioned objects, features and advantages of the present invention more comprehensible, the following specific examples will be described in detail with reference to the accompanying drawings.

FIG. 1 is a diagram illustrating an implementation of a memory cell array (corresponding to a sector) in a NOR type stack flash memory (NOR type stack flash), labeled 100. During an erase operation, over-erased problems may occur. For example, take the memory cells in the first row (the memory cells connected to the data line BL1) as an example, if some memory cells in the first row are found to be difficult to erase during the erasing process, the memory cells in the first row will be continuously erased. All memory cells in the first row are erased until all memory cells in the first row are indeed erased. However, such an operation may cause over-erasing of other memory cells in the first row even though the non-erasable memory cells can be erased. A phenomenon of over-erasing is that the threshold voltage of the transistor (such as MOS) of the memory cell will be pushed down very low, resulting in leakage current.

Regarding the above-mentioned over-erased problem, the present invention proposes an appropriate solution, which involves "over-erased line verification", "over-erased line repair", "over-erased bit verification" and "over-erased bit repair" technologies. They are described separately below.

With regard to "over-erase row verification", the verification object is a whole row of storage units. The verification result of this technique is whether any memory cells in the row have had erasure problems. It must be noted that the verification of the erased row does not necessarily indicate exactly which memory unit of the row has a problem. The over-erase row verification technology can be realized by any over-erase verification technology developed in the technical field with "column" as the verification unit.

Regarding the "over-erase row repair", it is to perform a one-time erase repair operation on a whole row of memory cells, and not to repair the memory cells of the row separately. The over-erased row repairing technology can be implemented by any over-erased repairing technology developed in the technical field with a "column" as a repairing unit.

Regarding "over-erased bit verification", the verification object is a single storage unit (bit) or a single group of storage units (bit group), and the verification result obtained is whether the storage unit of the bit/bit group has been erased. . The over-erased bit verification technology can be implemented by any over-erased verification technology developed in this technical field with "bit" or "byte" as the verification unit. In the following, for the convenience of discussion, all of them are discussed in terms of "bit". What needs to be declared is that the following discussions about "bits" all include examples of "bit groups".

With regard to "over-erased bit restoration", the erasure restoration operation is performed on a single storage unit (bit) or a single group of storage units (bit group). The over-erased bit repair technology can be implemented by any over-erased repair technology developed in the technical field with “bit” or “byte” as the repair unit. Similarly, for the convenience of discussion below, all are discussed in terms of "bit". What needs to be declared is that the following discussions about "bits" all include examples of "bit groups".

In addition, regarding the above-mentioned "over-erased row repair" and "over-erased bit repair", the purpose includes raising the threshold voltage of the repaired row of memory cells or transistors (such as MOS) in the memory cell to avoid leakage. current occurs. Regarding the above-mentioned technique of increasing the critical voltage of transistors, it is usually called "soft program (soft program or post program)". The unified operation of the entire row of memory cells is called "row soft programming", which can be used in the "over-erased row repair". The operation of each bit is called "bit soft programming", which can be used in the "over-erased bit repair".

This section describes an implementation of the over-erased verifying and repairing method of the NOR-gate cache memory disclosed in the present invention. In this method, the above-mentioned "over-erase line verification" is respectively implemented on a sector (sector, which can correspond to the aforementioned memory cell array 100) on a NOR gate type cache memory (for each column), and the "over-erase row verification" cannot be passed. "Erase Row Verification" row performs the above "Erase Row Repair". In addition, the method further implements the above-mentioned "over-erased bit verification" bit by bit (for each bit or byte) for the rows that cannot pass the "over-erased row repair" and pass the "over-erased row verification", and for the rows that cannot pass the "over-erased row verification" The "over-erase bit verification" bit is subjected to the above-mentioned "over-erase bit repair". This verification and repair method does not need to verify each storage unit in the sector in order to ensure that each storage unit in the sector has no over-erasing problem as in the traditional technology. In fact, the verification and repair method of the present invention firstly handles the erasure problem with "row" as the unit of verification and repair, and only the row that cannot be remedied by "over-erased row repair" needs to be processed for each bit. Erase verification and repair. The method disclosed in the present invention can complete the over-erasing verification and repair of a sector in a shorter time and with fewer operations.

Taking the memory cell matrix 100 disclosed in FIG. 1 as an example, the technology disclosed in the present invention selects a row of memory cells—for example, the first row of memory cells connected to the bit line BL1—as an initial setting of a “test row”. Next, the above-described "over-erased row verification" is performed on the "test row (first row)". Next, it is judged whether the "test row (first row)" has passed the above-mentioned "over-erased row verification". If the "test row (first row)" passes the "over-erase row verification", select an unverified row from the sector (memory cell array 100)—for example, the second row connected to the bit line BL2 Storage unit-update the "test row", and return to the above-mentioned step of performing "over-erase row verification" on the "test row", so as to switch to performing "over-erase row verification" on the storage cells of the second row. Or, if the aforementioned judgment shows that the "test row (first row)" has not passed the "over-erased row verification", then "repair of over-erased row" is performed on the "test row (first row)". If the "test line (first line)" cannot pass the "over-erasure line verification" by the "over-erasure line repair", then the above-mentioned " over-erase bit verification", and perform the above-mentioned "over-erase bit repair" on the bits that cannot pass the "over-erase bit verification"; in addition, if there is no bit in "this test row (first row)" that cannot pass the "Over-erase bit repair" passes "over-erase bit verification", then select an unverified row from the sector (memory cell array 100)—for example, the second row of memory cells connected to the bit line BL2—update " Test row", and return to the above-mentioned step of performing "over-erase row verification" on the "test row", so as to switch to "over-erase row verification" for the memory cells of the second row. Some implementations further consider the situation that a bit in the "test row (first row)" cannot pass the "over-erased bit repair" and pass the "over-erased bit verification", wherein a "failure message" will be sent to display all The executed NOR cache failed the erase verification and repair method.

FIG. 2 is a flow chart disclosing an implementation of the over-erasure verification and repair method of the NOR-type cache memory of the present invention, wherein the over-erasure verification and repair of a sector is described.

Step S202 is used to set the "test row" initially (as mentioned above, select a row from the memory cell array 100 as the "test row"), and reset the "row test cycle number" to zero. Step S204 executes "over-erase row verification" on the "test row". Step S206 judges whether the "test row" has passed the "verification of erased row". If step S206 determines that the "test row" cannot pass the "over-erased row verification", the process enters into "over-erased row repair" (including the loop formed by steps S208, S212, S214, S204 and S206 in FIG. 2).

This paragraph discusses the "over-erase row repair". Firstly, step S208 is executed to determine whether the "number of test cycles" reaches a first upper limit (which can be set by the user according to requirements). When it is judged in step S208 that the "number of row test cycles" has not reached the first upper limit, step S212 is executed to perform "row soft programming" on the "test row". Next, step S214 is executed to add 1 to the "row test cycle number". Again, get back to step S204, implement "over erase row verification" again to the "test row" processed through "row soft programming", and judge whether the current "test row" passes the "over erase row verification" in step S206. ". If step S206 shows that the "test row" processed by "row soft programming" can pass the "over-erase row verification", then execute step S216 to judge whether there are unverified rows in the sector, and execute step S216. S218, select one of the unverified rows to update the "test row", and reset the "row test cycle number" to zero. Then, the process returns to step S204, so as to additionally perform "verification of erased row" and subsequent actions on the updated "test row". However, if the "test row" of the "row soft programming" effect still cannot pass through "over-erase row verification" (judged by step S206), then as shown in the flow chart of Figure 2, step S208 is executed again to judge the current Whether the "line test cycle number" reaches the first upper limit is determined to perform step S212, or to perform step S210 instead. Regarding step S210, it is implemented after it is determined in step S208 that the "number of row test cycles" reaches the first upper limit. If step S208 determines that the "row test cycle number" reaches the first upper limit, the disclosed method will determine that the "test row" cannot pass the "over-erased row repair" and pass the "over-erased row verification". The process enters step S210, where the "test row" is subjected to "over-erased bit verification" bit by bit, and "over-erased bit correction" is performed on the bits that cannot pass the "over-erased bit verification". In some embodiments, as shown in the flowchart in FIG. 2 , a step S220 is executed after step S210 to determine whether all the bits of the "test line" have successfully passed the "over-erased bit verification". If all are successful, the process goes to step S216. If not all of them are successful, then a failure message is sent, indicating that the implemented NOR-gate cache memory verification and repair method has failed.

This paragraph compares the memory cell array in FIG. 1 to illustrate an implementation of step S220 in FIG. 2—the over-erased verification and restoration of “bits” as objects. Assume that the current "test row" is "the first row (the row of memory cells connected to the bit line BL1)". If the "test row (first row)" needs to be erased and verified and repaired with "bit" as the object, one bit can be selected from the "test row (first row)" (for example, by word line The storage unit controlled by WL1, that is, the storage unit in the first row and the first column) is used as the initial setting of a "test bit", and the "test bit (the storage unit in the first row and the first column)" is set as " Over-erase bit verification" and judge whether the "test bit (memory cell in the first row and first column)" passes the "over-erase bit verification". If this " test bit (the storage cell of the first row first column) " by this " erasing bit verification ", then from " this test row (first row) " select an unverified bit-for example, by The memory cell controlled by the word line WL2, that is, the memory cell in the first row and the second column-updates the "test bit", and returns to the above-mentioned step of performing "over-erase bit verification" on the "test bit" to switch Perform "over-erase bit verification" on the memory cells in the first row and the second column. Or, if this "test bit (the storage unit of the first row and the first column)" fails to pass the "verification of the erasing bit", then the "test bit (the storage unit of the first row and the first column)" Perform "over-erased bit repair". If the "test bit (memory unit in the first row and first column)" cannot pass the "over-erase bit repair" and pass the "over-erase bit verification", a failure message will be issued to indicate the implemented NOR gate cache The memory has failed the erase verification and repair method.

FIG. 3 is a flow chart disclosing an implementation manner of over-erasure verification and repair for "bits". The process 300 can be used to implement step S220 in FIG. 2 .

Step S302 is used to initially set the "test bit" (as mentioned above, select a bit from the current "test row" as the "test bit"), and reset the "bit test cycle number" to zero. Step S304 performs "over-erased bit verification" on the "test bit". Step S306 judges whether the "test bit" passes the "over-erased bit verification". If step S306 determines that the "test bit" cannot pass the "over-erased bit verification", the process enters into "over-erased bit repair" (including the loop formed by steps S308, S310, S312, S304 and S306 in FIG. 3).

This paragraph discusses the "over-erase bit repair". Firstly, step S308 is executed to determine whether the "bit test cycle number" reaches a second upper limit (which can be set by the user according to requirements). If the "number of bit test cycles" does not reach the second upper limit, step S310 is performed to perform "bit soft programming" on the "test bit". Next, step S312 is executed to add 1 to the "number of bit test cycles". Again, get back to step S304, implement "over erasure bit verification" again to the "test bit" processed through "bit soft programming", and judge whether the current "test bit" passes the "over erasure bit verification" in step S306 ". If step S306 shows that the "test bit" processed by "bit soft programming" can pass through "over-erase bit verification", then step S314 is executed to determine whether there are unverified bits in the current "test row", and Execute step S316, select one of the unverified bits to update the "test bit", and reset the "bit test cycle number" to zero. Then, the process returns to step S304 to additionally perform "over-erase bit verification" and subsequent actions on the updated "test bit". However, if the "test bit" of the "bit soft programming" effect still cannot pass through "over-erase bit verification" (judged by step S306), then as shown in the flow chart of Figure 3, step S308 is executed again to judge the current Whether the "number of bit test cycles" has reached the second upper limit. If the "number of bit test cycles" does not reach the second upper limit, step S310 is performed to continue the "repair of over-erased bits". If the "bit test cycle number" has reached the second upper limit, it means that the "test bit" cannot pass the "over-erased bit repair" and "over-erased bit verification", and the disclosed method will issue a failure message.

FIG. 4 illustrates an embodiment of the NOR-type cache memory of the present invention. The NOR-type cache memory 400 includes at least one sector (the sector can be the memory cell array 100 shown in FIG. 1 ) and a controller 402 . The controller 402 can implement the above-mentioned over-erased verification and repair technology, including performing the above-mentioned "over-erased row verification" row by row on the memory cell array 100, and perform "over-erased row verification" for rows that cannot pass the "over-erased row verification". The above-mentioned "over-erased line repair", and for the lines that cannot pass the "over-erased line verification" through the "over-erased line repair", perform the above-mentioned "over-erased bit verification" bit by bit, and for the lines that cannot pass the "over-erased line Over-erased bit verification” bits are subjected to the above-mentioned “over-erased bit repair”.

In addition, the controller 402 can also be used to implement other aforementioned erasure verification and restoration techniques.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall prevail as defined by the scope of the claims.

Claims (7)

1. a rejection gate type memory cache is crossed erase checking and restorative procedure, it is characterized in that, comprising:

A sector on the one rejection gate type memory cache is implemented one line by line respectively cross the row checking of erasing, and to carrying out one and cross the row reparation of erasing through the erase row of row checking of said mistake; And

For repairing through the erase row of row checking of said mistake, implement one by turn respectively and cross the erased bit checking, and cross the erased bit reparation carrying out one through the said position of crossing the erased bit checking through the said mistake row of erasing.

2. the method for claim 1 is characterized in that, more comprises:

In said sector, select delegation's storage unit, as the initial setting of a test line;

Said test line is carried out the erase row checking of said mistake;

Judge that said test line is whether through the row checking of erasing of said mistake;

If said test line is through the erase row checking of said mistake, the row of then selecting from said sector not verify upgrades said test line, and gets back to and above-mentioned said test line is carried out the erase step of row checking of said mistake; And

If said test line is through the do not erase row checking of said mistake, then said test line is carried out the said mistake row reparation of erasing, wherein:

If said test line can't be repaired through the row checking of erasing of said mistake through the said mistake row of erasing; Then a plurality of positions in the said test line are implemented the said erased bit checking of crossing respectively, and to carrying out the said erased bit reparation of crossing through the said position of crossing the erased bit checking; And

If there is not in the said test line position to cross the erased bit reparation and cross the erased bit checking through said through said, the row of then selecting from said sector not verify upgrades said test line, and gets back to and above-mentionedly said test line is carried out said mistake erase and go the step of verifying.

3. method as claimed in claim 2; It is characterized in that; If can't repair to erase and have in the said test line of row checking the position to cross the erased bit reparation and cross the erased bit checking, then send failure information and show that said rejection gate type memory cache crosses erase checking and restorative procedure and fail through the said mistake row of erasing through said through said through said mistake.

4. method as claimed in claim 3 is characterized in that, said method comprises that more the initial value with delegation's test loop number is set at zero, and carries out following steps when said mistake is erased the row reparation in implementing:

Judge whether said capable test loop number reaches one first upper limit;

Reach on said first in limited time in this row test loop number, judge that said test line can't repair through the row checking of erasing of said mistake through the said mistake row of erasing; And

Do not reach on said first in limited time in said capable test loop number, said test line carried out delegation's soft programming, and said capable test loop number is added 1, and judge that once more said test line is whether through the row checking of erasing of said mistake, wherein:

If said test line is able to through said capable soft programming through the erase row checking of said mistake; The row of then selecting from said sector not verify upgrades the said test line and the said capable test loop number that makes zero, with row checking that the said mistake of the other execution of the said test line that upgraded is erased; And

If said test line can't be through said capable soft programming through the erase row checking of said mistake, then carry out again and saidly judge whether said capable test loop number reaches the step of said first upper limit.

5. method as claimed in claim 4 is characterized in that, said method more comprises:

, the row of can't erasing through said mistake selects one in repairing institute's rheme of said test line of the row checking of erasing through said mistake, as the initial setting of a test position;

The said erased bit checking of crossing is done in said test position;

Judge whether said test position is verified through the said erased bit of crossing;

If the erased bit checking is crossed through said in said test position, then upgrade said test position from the position that said test line is selected not verify, and get back to said to said test position execution said the step verified of erased bit; And,

If said test position is not verified through the said erased bit of crossing, then the said erased bit reparation of crossing is carried out in said test position, wherein:

If said test position can't be crossed the erased bit reparation and crosses the erased bit checking through said through said, then send failure information and show that said rejection gate type memory cache is crossed to erase and verify and restorative procedure is failed.

6. method as claimed in claim 5; It is characterized in that; More be included in and judge that said test line can't be set at zero through the said mistake initial value that row repairs when erasing the row checking through said mistake a bit test period of erasing, and carry out following steps when erased bit is repaired in implementing said the mistake:

Judge whether said bit test period reaches one second upper limit;

Reach on said second in limited time in said bit test period, judges that said test position can't cross the erased bit reparation and erase to go through said mistake and verify through said; And

Do not reach on said second in limited time in said bit test period, a soft programming is carried out in said test position, and said bit test period is added 1, and judge once more whether said test position erases to go through said mistake and verify, wherein:

If said test position is able to verify through the said erased bit of crossing through institute's rheme soft programming; Then upgrade the said test position and the said bit test period that makes zero, and get back to the said step of crossing the erased bit checking is carried out in said test position from the position that said test line is selected not verify; And

If said test position can't be verified through the said erased bit of crossing through institute's rheme soft programming, then get back to and judge whether said bit test period reaches the step of said second upper limit.

7. a rejection gate type memory cache is characterized in that, comprising:

At least one sector comprises a memory cell array;

One controller; Cross the row checking of erasing in order to the said memory cell array of said sector is implemented line by line one respectively; And to carrying out one and cross the row reparation of erasing through the erase row of row checking of said mistake; And, implement one by turn respectively and cross the erased bit checking, and cross the erased bit reparation carrying out one through the said position of crossing the erased bit checking for repairing through the erase row of row checking of said mistake through the said mistake row of erasing.

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