CN102347359B - Power metal oxide semiconductor field effect transistor (MOSFET) device and method for manufacturing same - Google Patents
Power metal oxide semiconductor field effect transistor (MOSFET) device and method for manufacturing same Download PDFInfo
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Abstract
The invention relates to a power metal oxide semiconductor field effect transistor (MOSFET) device, which can selectively deposit conductive materials with different work functions on different parts in the same contact channel so as to form the respective optimized metal-semiconductor contact characteristics of the different parts, wherein one conductive material is deposited on the sidewall and corners of the bottom of the contact channel and contacted with a P-type heavily-doped region to form an ohm junction; and another conductive material is deposited in a middle region of the bottom of the contact channel and contacted with a lightly-doped N-type epitaxial layer to form a Schottky junction, so that low resistance of the ohm junction and good rectification characteristic of the Schottky junction required by realizing the performance of the power MOSFET device are respectively guaranteed. Meanwhile, P-type heavily-doped silicon encloses the corners of the bottom of the contact channel to form an N-P-M structure, so that gathered leakage currents in the corners of the contact channel are effectively reduced. The invention also provides a process method for implementing the power MOSFET device. The method comprises the following steps of: by using a process for constructing a side spacing layer of the contact channel, preparing different types of metal at the bottom and sidewall of the contact channel; and optimizing the space distribution of doped ions.
Description
Technical field
The present invention relates to a kind of power MOSFET device and manufacture method thereof, particularly in same contact raceway groove, by different qualities metal, construct respectively power MOSFET device and the manufacture method thereof of drain schottky knot and tagma ohm knot.
Background technology
As shown in Figure 1, it is the structural representation of existing power MOSFET (mos field effect transistor) device, the MOSFET of n raceway groove of take is example, it comprises and one is created on n-epitaxial loayer 200 in n+ base substrate 100, in n-epitaxial loayer 200, offers some trench-gates 310, along sidewall and the bottom of this trench-gate 310, is provided with gate insulator 320 and the 200 insulation isolation of n-epitaxial loayer.At the top section of n-epitaxial loayer 200, be also formed with 400He source region, p-type tagma 450 around this trench-gate 310.Top surface in said n-epitaxial loayer 200, trench-gate 310 and source region 450 also deposits the dielectric layer 500 containing low temperature oxide and boron-phosphorosilicate glass.
By etching, form some contact raceway grooves 600 that run through dielectric layer 500,450He tagma, source region 400, its bottom extends in epitaxial loayer 200 always.The top surface of above-mentioned dielectric layer 500 with contact the sidewall of raceway groove 600 and lower surface on the interface potential barrier conductive layer 700 that formed by metal material of deposition.On interface potential barrier conductive layer 700, also deposit connection metal layer 800, this connection metal layer 800 fills up and extends to described dielectric layer 500 top face by contact raceway groove 600.The follow-up electrode pattern that forms semiconductor device by photoetching, the above-mentioned connection metal layer 800 of etching and interface potential barrier conductive layer 700.
Between the side of above-mentioned interface potential barrier conductive layer 700 and the tagma of high-concentration dopant 400, because metal-semiconductor contact forms ohm knot; Between the bottom of interface potential barrier conductive layer 700 and the epitaxial loayer of low concentration doping 200, form schottky junction.Wherein, ohm knot has that resistance is little, the feature of I-V (current-voltage) curve linear symmetry, if generally use the metal material that work functions are higher (as the platinum Pt of work function 5.65eV etc.) to contact with semiconductor at interface potential barrier conductive layer 700, can reduce the barrier height between metal and semiconductor, make the resistance of ohm knot less.And schottky junction has the I-V curve of diode characteristic, if conventionally use the moderate metal material combined semiconductor of work function to mix change in concentration, can make the rectification effect of schottky junction better.Above-mentioned work function refers to that an electronics rises to the required least energy of metal surface inactive state (being vacuum level) from Fermi (Fermi) energy level.
Yet, for above-mentioned existing power MOSFET device, because interface potential barrier conductive layer 700 sides ohm knot forming and the schottky junction that bottom forms share same interface potential barrier conductive layer 700, although for example use the metal material of high work function can bring into play the little characteristic of ohm junction resistance at interface potential barrier conductive layer 700, but because it must, by very high forward voltage ability conducting, be brought into play and have a significant impact for the performance of schottky junction.In order to accomplish, to the taking into account of ohmic contact and Schottky contact properties, often can only to select the compromise metal material of work function to make interface potential barrier conductive layer 700, thereby can not give full play to characteristic separately.
In addition, as shown in dotted portion in Fig. 1, the bottom corner position of contact raceway groove 600 is not surrounded by tagma 400, but contact with epitaxial loayer 200, form schottky junction, angle, schottky junction edge in bottom has the concentrated phenomenon of electric field, thereby is easy to produce very large reverse leakage current in contact raceway groove 600 bottom corner.
Summary of the invention
The object of the present invention is to provide a kind of power MOSFET device and manufacture method thereof, can by tagma surround contact raceway groove bottom corner reduce reverse leakage current; Also by depositing, the metal of different work functions contacts respectively formation schottky junction with semiconductor and ohm knot is brought into play its characteristic separately.
In order to achieve the above object, technical scheme of the present invention is to provide a kind of power MOSFET device, comprises:
Be arranged on the epitaxial loayer in base substrate;
Be formed at the trench-gate in the groove in epitaxial loayer;
Be formed on the top section of epitaxial loayer, and around the tagma of trench-gate;
Be formed on the source region of tagma top section;
Be formed on the dielectric layer on trench-gate and source region top surface;
Some contact raceway grooves that run through dielectric layer, source region formation;
It is characterized in that,
Above-mentioned contact trench bottom ends at tagma, and the bottom corner of above-mentioned contact raceway groove is surrounded by above-mentioned tagma; Also comprise
The drift region that be formed in middle tagma, contact raceway groove below, is connected with epitaxial loayer;
Be formed on the schottky junction of the bottom zone line of above-mentioned contact raceway groove;
Be formed on sidewall and the lip-deep ohm knot of its bottom corner of contact raceway groove.
Above-mentioned power MOSFET device, also comprises and covers ohm knot, the lip-deep connection metal layer of schottky junction, the top face that it fills up above-mentioned contact raceway groove and extends to dielectric layer.
Above-mentioned schottky junction is contacted and forms with above-mentioned drift region by interface potential barrier electric conducting material.
Above-mentioned ohm knot is contacted and forms with above-mentioned tagma by interface potential barrier electric conducting material.
Contact the interface potential barrier electric conducting material that forms ohm knot with above-mentioned tagma, different with the interface potential barrier electric conducting material that contacts formation schottky junction from above-mentioned drift region.
In above-mentioned tagma, be also provided with the ion implanted region around above-mentioned contact trench sidewalls and bottom corner formation; The bottom corner of above-mentioned contact raceway groove is surrounded by above-mentioned ion implanted region.
A manufacture method for power MOSFET device, comprises following steps:
A. in base substrate, form epitaxial loayer;
B. in epitaxial loayer, form trench-gate;
C. at epitaxial loayer intermediate ion, inject and form tagma;
D. at epitaxial loayer top Implantation, form source region;
E. epitaxial loayer top deposition forms dielectric layer;
It is characterized in that, also comprise following steps:
F. etching dielectric layer forms the contact raceway groove that some bottoms extend to tagma;
H. deposition etching form wall;
I. in the tagma in the middle of contact raceway groove bottom, form the drift region that connects epitaxial loayer;
J. deposit the first interface potential barrier electric conducting material, and contact with drift region and form schottky junction in the middle of contact trench bottom;
1. deposit second contact surface potential barrier electric conducting material, and contact formation ohm knot with tagma in sidewall and the bottom corner thereof of contact raceway groove;
M. on ohm knot, schottky junction, deposition forms connection metal layer.
Between step f and step h, be also included in above-mentioned contact raceway groove Side wall and bottom and by angle-tilt ion, inject the step g that forms ion implanted region.
The bottom of above-mentioned contact raceway groove ends in above-mentioned tagma or ion implanted region wherein, and the bottom corner of above-mentioned contact raceway groove is surrounded by above-mentioned tagma or above-mentioned ion implanted region.
In a preferred embodiment of the present invention, above-mentioned wall is to be formed on above-mentioned contact trench sidewalls and bottom corner thereof by vertical direction anisotropic etching, and the surface of above-mentioned contact trench bottom zone line is exposed.
The step h of above-mentioned formation wall, the expendable material specifically insulating by deposition is realized.
In above-mentioned steps h, deposition forms the expendable material of wall, is the insulating material of silicon dioxide SiO2 or silicon nitride SiN.
Between above-mentioned steps i and step j, also comprise the step k of the wall of removing above-mentioned insulation.
In another preferred embodiment of the present invention, in above-mentioned steps h, specifically by deposition second contact surface potential barrier electric conducting material, and etching forms and covers the contact sidewall of raceway groove and the wall of bottom corner thereof, and above-mentioned wall contact with above-mentioned tagma form ohm to tie.
In above-mentioned steps j, above-mentioned schottky junction is to take above-mentioned wall as mask, can form that the metal of silicide realizes in the bottom of above-mentioned contact raceway groove zone line deposition; Above-mentioned metal is titanium Ti, or tantalum Ta, or nickel.
Above-mentioned steps i specifically in the tagma of centre, by Implantation and this tagma of local transoid, forms the above-mentioned drift region being connected with epitaxial loayer below contact raceway groove.
Power MOSFET device provided by the invention and manufacture method thereof, compared with prior art, its advantage is: the present invention, due to the electric conducting material of deposition high work function characteristic, contacts with heavily doped tagma with bottom corner and forms ohm knot at the sidewall that contacts raceway groove; Also by the moderate electric conducting material of deposition work function, in the middle of the bottom of contact raceway groove, contact with lightly doped epitaxial loayer and form schottky junction, thereby make the present invention can in same contact raceway groove, construct two kinds of dissimilar silicon interfaces of P/N, and and the metal of different work functions form ohmic contact and Schottky contacts, therefore can bring into play the characteristic of the little and schottky junction rectification of ohm junction resistance simultaneously.
The present invention, due to the bottom corner that contacts raceway groove is surrounded by tagma or B+ boron P-type ion implanted region wherein, can, in the contact performance while that guarantees schottky junction, effectively reduce the reverse leakage current of contact raceway groove corner location.And because schottky junction is arranged on middle this single silicon wafer face of contact raceway groove, thereby also can effectively improve the consistency of schottky junction.
Accompanying drawing explanation
Fig. 1 is the structure cutaway view of the power MOSFET device that provides of prior art;
Fig. 2 is the structure cutaway view of a kind of power MOSFET device of the present invention in embodiment 1;
Fig. 3 is the manufacture method of a kind of power MOSFET device of the present invention flow chart of steps in embodiment 1;
Fig. 4 to Fig. 7 is the manufacture method of a kind of power MOSFET device of the present invention step schematic diagram in embodiment 1;
Fig. 8 is the manufacture method of a kind of power MOSFET device of the present invention step schematic diagram in embodiment 2;
Fig. 9 to Figure 12 is the manufacture method of a kind of power MOSFET device of the present invention step schematic diagram in embodiment 2.
Embodiment
Below in conjunction with accompanying drawing explanation multinomial execution mode of the present invention.
Embodiment 1
Be the structure cutaway view of a kind of power MOSFET device of the present invention as shown in Figure 2, this power MOSFET device of n raceway groove of take is example, and it comprises the heavily doped base substrate 10 of a n+ and a n-epitaxial loayer 20 of growth in this base substrate 10; Offer some grooves 30 that extend to certain depth in epitaxial loayer 20, and fill therein such as the electric conducting material of polysilicon to form trench-gate 31; Sidewall and bottom along this trench-gate 31 are formed with thinner oxide, as gate insulator 32, trench-gate 31 and epitaxial loayer 20 insulation are isolated.
At the top of epitaxial loayer 20, around trench-gate 31, be also formed with the tagma 40 of p-type, 40 tops, tagma of p-type are also formed with the source region 45 of n++ type by Implantation; This tagma 40, source region 45 are by gate insulator 32 and trench-gate 31 insulation isolation.Top surface in epitaxial loayer 20, trench-gate 31 and source region 45 also deposits the dielectric layer 50 consisting of low temperature oxide and boron-phosphorosilicate glass, for contacting of isolated trench-gate 31 and source region 45.
Run through dielectric layer 50 and offer some contact raceway grooves 60, it extends in tagma 40 always, and the bottom corner that contacts raceway groove 60 is surrounded by the tagma 40 of p-type.In tagma 40, also by Implantation, be formed with n-drift region 25, the bottom zone line that contacts raceway groove 60 is contacted with n-epitaxial loayer 20 by this drift region 25, and the position being connected with drift region 25 in the middle of the bottom of this contact raceway groove 60 deposit the first interface potential barrier electric conducting material (being called for short the first electric conducting material) formation schottky junction 71.
On top surface, the contact sidewall of raceway groove 60 and the surface in its bottom corner region and the schottky junction 71 of dielectric layer 50, also deposit second contact surface potential barrier electric conducting material (being called for short the second electric conducting material), its sidewall at contact raceway groove 60 contacts with its YupXing tagma, bottom corner region 20 and forms ohm knot 72.On the second electric conducting material, be also provided with connection metal layer 80, the top face that it fills up contact raceway groove 60 and extends to dielectric layer 50.
The above-mentioned interface potential barrier electric conducting material that forms respectively schottky junction 71 and ohm knot 72 is two kinds of metals that work function is different.In contact raceway groove 60 sides and bottom corner position, the deposition metal of high work function and the tagma 40 of heavy doping p-type contact and form ohm knot 72; In the present embodiment, for example, can use the platinum Pt of work function 5.65eV, or the nickel of work function 5.15eV, or tungsten silicide WSi
2on metal, make described ohm knot 72, make ohm knot 72 resistance of formation less.
And in the centre position, bottom of contact raceway groove 60, use the metal that work function is moderate to contact formation schottky junction 71 with the drift region 25 of light dope n-type; In the present embodiment, for example, can use the titanium Ti of work function 4.33eV, or the metals such as tantalum Ta of work function 4.25eV make this schottky junction 71, make the rectification effect of the schottky junction 71 that forms better.
As shown in Figure 7, in some better embodiment, the B+ boron p-type ion implanted region 41 forming around above-mentioned ohm knot 72 can also be set in the tagma 40 of p-type, the bottom corner that contacts raceway groove 60 is surrounded by B+ boron p-type ion implanted region 41.
The manufacture method that the power MOSFET device of the above-mentioned B+ of being provided with boron p-type ion implanted region 41 is described below in conjunction with Fig. 3 to Fig. 7, wherein Fig. 3 is the flow chart of steps of this manufacture method.
First in step a, in the heavily doped base substrate 10 of n+, growth forms a n-epitaxial loayer 20; Step b, on the surface of n-epitaxial loayer 20, form the groove being formed by silicon dioxide 30 masks, and be etched in through n-epitaxial loayer 20 being etched to predetermined depth after this groove 30 masks with anisotropic (anis-tropically), form some grooves 30; Along sidewall and the bottom of groove 30, sacrificial oxide layer growth and etching work procedure by standard, form the gate insulator 32 conventionally consisting of oxide; In remaining space in groove 30 and on silicon dioxide groove 30 masks, deposit n+ doped polycrystalline silicon to form trench-gate 31; Again the n+ doped polycrystalline silicon on silicon dioxide groove 30 masks is carried out to etch-back, and peel off this groove 30 masks.
Step c, to steps d, by p-Implantation with diffuse to form p-tagma 40, afterwards by n Implantation, forms the source region 45 of n++ at the top section of described n-epitaxial loayer 20 in p-tagma 40 around the gate insulator 32 of groove 30.Step e also deposits the dielectric layer 50 of low temperature oxide and boron-phosphorosilicate glass on trench-gate 31, n-epitaxial loayer 20 and n++ source region 45, for the insulation isolation with trench-gate 31.In step f, by etching, run through dielectric layer 50 and generate some raceway grooves 60 that contact with source region 45, make to contact raceway groove 60 bottoms and extend in p-type tagma 40.
As shown in Figure 4, step g forms around the B+ boron P-type ion implanted region 41 of contact raceway groove 60 sidewalls and bottom by inclination p-type Implantation mode in p-type tagma 40, characteristic with strengthening p-type, is positively enclosed in contact raceway groove 60 bottoms in B+ boron P-type ion implanted region 41.
As shown in Figure 5, in step h, by the method for chemical vapour deposition (CVD) (CVD), deposition is as SiO
2or the insulating material such as SiN forms wall 90, and by anisotropic, do after quarter in the vertical direction, make remaining wall 90 cover the sidewall of dielectric layer 50 and contact raceway groove 60, the bottom corner position of contact raceway groove 60, but expose on the surface that makes to contact the bottom zone line of raceway groove 60.
Subsequently in step I, using above-mentioned wall 90 as mask, below contact raceway groove 60, in the tagma 40 in centre position, by phosphonium ion, inject and local transoid, by 40 blocking-up of the 41HepXing tagma, B+ boron P-type ion implanted region of contact raceway groove 60 bottoms, form the n-drift region 25 that connects n-epitaxial loayer 20.As seen from Figure 5, now these contact raceway groove 60 bottom zone lines directly contact with n-drift region 25, and the bottom corner of contact raceway groove 60 is surrounded by the B+ boron p-type ion implanted region 41 in p-type tagma 40.
As shown in Figure 6, utilize equally wall 90 to make mask in step j, the position being connected with n-drift region 25 in the middle of bottoms at this contact raceway groove 60, deposits the first electric conducting material and contacts with n-drift region 25 and form schottky junction 71.As mentioned above, the first electric conducting material of deposition is the metal that work function is moderate, in the present embodiment, can use titanium Ti, or the metal such as tantalum Ta with come drift region 25 to contact to form this schottky junction 71, make the rectification effect of this schottky junction 71 better.
As shown in Figure 7, in step k, by wet clean process, remove the wall 90 of insulation.In step 1 afterwards, on top surface, the contact sidewall of raceway groove 60 and the surface in its bottom corner region and the schottky junction 71 of dielectric layer 50, deposition the second electric conducting material contacts with p-type tagma 40 and forms ohm knot 72.As mentioned above, the second electric conducting material of deposition is the metal of high work function, in the present embodiment, can use platinum Pt, or nickel, or tungsten silicide WSi
2on metal, form this ohm of knot 72, make this ohm of knot 72 resistance less.
In step m, on the second electric conducting material, deposition forms connection metal layer 80, the top face that it fills up contact raceway groove 60 and extends to dielectric layer 50.All the other can complete by standardization program the manufacture of the power MOSFET device of the whole B+ of being provided with boron p-type ion implanted region 41.
If only remove above-mentioned formation in p-type tagma 40 by Implantation around the step g of the B+ boron p-type ion implanted region 41 in contact raceway groove 60 sidewalls and its bottom corner region, the technological process of this step a to step f, step h to step m can be equally applicable to manufacture the power MOSFET device that B+ boron p-type ion implanted region 41 is not set as shown in Figure 2.
Embodiment 2
As shown in figure 12, structural similarity in power MOSFET device and embodiment 1,2 in the present embodiment, in the power MOSFET device of n raceway groove, the base substrate 10 that comprises a n+ and the n-epitaxial loayer 20 in this base substrate 10; Some grooves 30 extend in epitaxial loayer 20, form trench-gate 31 after filled conductive material, and gate insulator 32 and epitaxial loayer 20 insulation isolation are set.At the top of epitaxial loayer 20, around trench-gate 31, be formed with the tagma 40 of p-type; 40 tops, tagma of p-type are also formed with the source region 45 of n++ type by Implantation; Top surface in epitaxial loayer 20, trench-gate 31 and source region 45 also deposits the dielectric layer 50 of low temperature oxide and boron-phosphorosilicate glass.In dielectric layer 50, run through and offer some contact raceway grooves 60, the bottom corner that contacts raceway groove 60 is surrounded by the tagma 40 of p-type; And be formed with n-drift region 25 in the middle of below contact raceway groove 60, be connected with epitaxial loayer 20, the bottom zone line that contacts raceway groove 60 is contacted with this n-drift region 25.
Unique difference is, the wall comprising in the present embodiment specifically deposits and etching is formed on the second electric conducting material on above-mentioned contact raceway groove 60 sidewalls and its bottom corner region.The wall of this conduction, in contact raceway groove 60 sides and bottom corner position, contacts ohm knot 72 forming with the tagma 40 of heavy doping p-type.Described the second electric conducting material is the WSi with high work function characteristic
2(tungsten silicide), p+ polysilicon etc. material, so its ohm knot 72 resistance that contact formation with the tagma 40 of heavy doping p-type are less.
Between the second electric conducting material of contact raceway groove 60 bottoms, the position that is connected with n-drift region 25 deposits the first conductor material.Same as the previously described embodiments, this first conductor material is the metals such as titanium Ti, tantalum Ta that work function is moderate, makes it contact schottky junction 71 rectification characteristics that form with the drift region 25 of light dope n-type better.
Cover on the second electric conducting material of contact raceway groove 60 sidewalls and the first electric conducting material of contact raceway groove 60 bottom zone lines, be also provided with connection metal layer 80, the top face that it fills up contact raceway groove 60 and extends to dielectric layer 50.
In some better embodiment, the B+ boron P-type ion implanted region 41 forming around above-mentioned ohm knot 72 can also be set in the tagma 40 of p-type, the bottom corner region that contacts raceway groove 60 is surrounded by B+ boron P-type ion implanted region 41.
The manufacture method that the power MOSFET device of the above-mentioned B+ of being provided with boron P-type ion implanted region 41 is described below in conjunction with Fig. 8 to Figure 12, wherein Fig. 8 is the flow chart of steps of this manufacture method.
With similar in embodiment 1, first, in step a, in the heavily doped base substrate 10 of n+, growth forms a n-epitaxial loayer 20; During step b, on the surface of n-epitaxial loayer 20, form the groove being formed by silicon dioxide 30 masks, and be etched in through n-epitaxial loayer 20 being etched to predetermined depth after this groove 30 masks with anisotropic (anis-tropically), form some grooves 30; Along sidewall and the bottom of groove 30, sacrificial oxide layer growth and etching work procedure by standard, form the gate insulator 32 conventionally consisting of oxide; In remaining space in groove 30 and on silicon dioxide groove 30 masks, deposit n+ doped polycrystalline silicon to form trench-gate 31; Again the n+ doped polycrystalline silicon on silicon dioxide groove 30 masks is carried out to etch-back, and peel off this groove 30 masks.
Step c, to steps d, by p-Implantation with diffuse to form p-tagma 40, afterwards by n Implantation, forms the source region 45 of n++ at the top section of described n-epitaxial loayer 20 in p-tagma 40 around the gate insulator 32 of groove 30.Step e also deposits the dielectric layer 50 of low temperature oxide and boron-phosphorosilicate glass on trench-gate 31, n-epitaxial loayer 20 and n++ source region 45, for the insulation isolation with trench-gate 31.In step f, by etching, run through dielectric layer 50 and generate some raceway grooves 60 that contact with source region 45, make to contact raceway groove 60 bottoms and extend in p-type tagma 40.
As shown in Figure 9, step g forms around the B+ boron p-type ion implanted region 41 of contact raceway groove 60 sidewalls and bottom by inclination p-type Implantation mode in p-type tagma 40, characteristic with strengthening p-type, is positively enclosed in contact raceway groove 60 bottoms in B+ boron p-type ion implanted region 41.
From step h, start different from above-described embodiment, as shown in figure 10, deposition as WSi
2the second electric conducting material of (tungsten silicide) or p+ polysilicon is as wall, carry out anisotropic after dry quarter, make the bottom corner position of its sidewall that covers dielectric layer 50 and contact raceway groove 60, contact raceway groove 60, expose on the surface that simultaneously makes to contact the bottom zone line of raceway groove 60.This second electric conducting material has high work function characteristic, and contacts with the tagma 40 of heavy doping p-type with bottom corner position and form ohm knot 72 in contact raceway groove 60 sides.
Subsequently in step I, using above-mentioned the second electric conducting material as mask, below contact raceway groove 60, in the tagma 40 in centre position, by phosphonium ion, inject and local transoid, by 40 blocking-up of the 41HepXing tagma, B+ boron p-type ion implanted region of contact raceway groove 60 bottoms, form the n-drift region 25 that connects n-epitaxial loayer 20.As seen from Figure 10, now these contact raceway groove 60 bottom zone lines directly contact with n-drift region 25, and the bottom corner that now contacts raceway groove 60 is surrounded by B+ boron p-type ion implanted region 41.
As shown in figure 11, utilize equally the second electric conducting material to make mask in step j, the position being connected with n-drift region 25 in the middle of bottoms at this contact raceway groove 60, deposits the first electric conducting material and contacts with n-drift region 25 and form schottky junction 71.As mentioned above, the first electric conducting material of deposition is the metal that work function is moderate, in the present embodiment, can use titanium Ti, or the metal such as tantalum Ta with come drift region 25 to contact to form this schottky junction 71, make the rectification effect of this schottky junction 71 better.
As shown in figure 12, in step m afterwards, deposition forms connection metal layer 80, it is covered on ohm knot 72 of contact raceway groove 60 sidewalls and the schottky junction 71 of contact raceway groove 60 bottoms, the top face that it fills up contact raceway groove 60 and extends to dielectric layer 50.All the other can complete by standardization program the manufacture of the power MOSFET device of the whole B+ of being provided with boron p-type ion implanted region 41.
If only remove above-mentioned formation in p-type tagma 40 by Implantation around the step g of the B+ boron p-type ion implanted region 41 in contact raceway groove 60 sidewalls and its bottom corner region, above-mentioned technological process can be equally applicable to manufacture the power MOSFET device that B+ boron p-type ion implanted region 41 is not set.
After the manufacture method providing in the present invention needs only the semiconductor layer and alloy of opposite polarity in employing and embodiment, equally applicable to P channel power MOS FET device.
Described in comprehensive above-described embodiment 1,2, power MOSFET device provided by the invention and manufacture method thereof, by the electric conducting material of deposition high work function characteristic, make its sidewall at contact raceway groove 60 contact with heavily doped tagma 40 with bottom corner and form ohm knot 72; Also, by the moderate conductivity of deposition work function, its bottom zone line at contact raceway groove 60 is contacted with lightly doped epitaxial loayer 20 and form schottky junction 71.Thereby the present invention in same contact raceway groove 60 by structure P/N two kinds of dissimilar silicon interfaces, and and the metal of different work functions form ohmic contact and Schottky contacts, can bring into play the characteristic of little and schottky junction 71 rectifications of ohm knot 72 resistance simultaneously.
In addition, the bottom corner of contact raceway groove 60, owing to being surrounded by tagma 40 or B+ boron p-type ion implanted region wherein 41, can, in the contact performance while that guarantees schottky junction 71, effectively reduce the reverse leakage current of contact raceway groove 60 corner location.And because schottky junction 71 is arranged on middle this single silicon wafer face of contact raceway groove 60, thereby also can effectively improve the consistency of schottky junction 71.
Although content of the present invention has been done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.Those skilled in the art, read after foregoing, for multiple modification of the present invention with to substitute will be all apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (13)
1. a power MOSFET device, comprises:
Be arranged on the epitaxial loayer (20) in base substrate (10);
Be formed at the trench-gate (31) in the groove (30) in epitaxial loayer (20);
Be formed on the top section of epitaxial loayer (20), and around the tagma (40) of trench-gate (31);
Be formed on the source region (45) of tagma (40) top section;
Be formed on the dielectric layer (50) on trench-gate (31) and source region (45) top surface;
Some contact raceway grooves (60) that run through dielectric layer (50), source region (45) formation;
It is characterized in that,
Described contact raceway groove (60) bottom ends at tagma (40), and the bottom corner of described contact raceway groove (60) is surrounded by described tagma (40); Also comprise
The drift region (25) that be formed in middle tagma (40), contact raceway groove (60) below, is connected with epitaxial loayer (20);
By the first interface potential barrier electric conducting material, contacted with described drift region (25) and be formed on the schottky junction (71) of the bottom zone line of described contact raceway groove (60);
By second contact surface potential barrier electric conducting material, contacted with described tagma (40) and be formed on sidewall and the lip-deep ohm knot of its bottom corner (72) of contact raceway groove (60); Wherein, described the first interface potential barrier electric conducting material is different from described second contact surface potential barrier electric conducting material.
2. power MOSFET device as claimed in claim 1, it is characterized in that, also comprise and cover ohm knot (72), the lip-deep connection metal layer of schottky junction (71) (80), the top face that it fills up described contact raceway groove (60) and extends to dielectric layer (50).
3. power MOSFET device as claimed in claim 1, is characterized in that, is also provided with the ion implanted region (41) around described contact raceway groove (60) sidewall and bottom corner formation in described tagma (40); The bottom corner of described contact raceway groove (60) is surrounded by described ion implanted region (41).
4. a manufacture method for power MOSFET device, comprises following steps:
A. at the upper epitaxial loayer (20) that forms of base substrate (10);
B. in epitaxial loayer (20), form trench-gate (31);
C. at epitaxial loayer (20) intermediate ion, inject and form tagma (40);
D. at epitaxial loayer (20) top Implantation, form source region (45);
E. epitaxial loayer (20) top deposition forms dielectric layer (50);
It is characterized in that, also comprise following steps:
F. etching dielectric layer (50) forms the contact raceway groove (60) that some bottoms extend to tagma (40);
H. deposition etching form wall (90);
I. in the tagma (40) in the middle of contact raceway groove (60) bottom, form the drift region (25) that connects epitaxial loayer (20);
J. deposit the first interface potential barrier electric conducting material, and contact with drift region (25) and form schottky junction (71) in the middle of contact raceway groove (60) bottom;
L. deposit second contact surface potential barrier electric conducting material, and contact formation ohm knot (72) with tagma (40) in sidewall and the bottom corner thereof of contact raceway groove (60);
M. ohm knot (72), the upper deposition of schottky junction (71) form connection metal layer (80).
5. the manufacture method of power MOSFET device as claimed in claim 4, it is characterized in that, between step f and step h, be also included in described contact raceway groove (60) sidewall and bottom and by angle-tilt ion, inject the step g that forms ion implanted region (41).
6. the manufacture method of power MOSFET device as claimed in claim 5, it is characterized in that, the bottom of described contact raceway groove (60) ends in described tagma (40) or ion implanted region wherein (41), and the bottom corner of described contact raceway groove (60) is surrounded by described tagma (40) or described ion implanted region (41).
7. the manufacture method of power MOSFET device as claimed in claim 4, it is characterized in that, described wall (90) is to be formed on described contact raceway groove (60) sidewall and bottom corner thereof by vertical direction anisotropic etching, and the surface of described contact raceway groove (60) bottom zone line is exposed.
8. the manufacture method of power MOSFET device as claimed in claim 4, is characterized in that, the step h of described formation wall (90), and the expendable material specifically insulating by deposition is realized.
9. the manufacture method of power MOSFET device as claimed in claim 8, is characterized in that, in described step h, deposition forms the expendable material of wall (90), is silicon dioxide SiO
2or the insulating material of silicon nitride SiN.
10. the manufacture method of power MOSFET device as claimed in claim 8, is characterized in that, between described step I and step j, also comprises the step k of the wall (90) of removing described insulation.
The manufacture method of 11. power MOSFET devices as claimed in claim 4, it is characterized in that, in described step h, specifically by deposition second contact surface potential barrier electric conducting material, and etching forms and to cover the sidewall of contact raceway groove (60) and the wall (90) of bottom corner thereof, described wall (90) contact with described tagma (40) form ohm to tie (72).
The manufacture method of 12. power MOSFET devices as claimed in claim 4, it is characterized in that, in described step j, described schottky junction (71) is that to take described wall (90) be mask, can form that the metal of silicide realizes in the bottom of described contact raceway groove (60) zone line deposition; Described metal is titanium Ti, or tantalum Ta, or nickel.
The manufacture method of 13. power MOSFET devices as claimed in claim 4, it is characterized in that, in the tagma (40) of described step I in the middle of specifically below contact raceway groove (60), by Implantation and this tagma of local transoid (40), the drift region (25) being connected with epitaxial loayer (20) described in forming.
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| CN101107718A (en) * | 2005-02-11 | 2008-01-16 | 万国半导体股份有限公司 | Power metal oxide semiconductor assembly |
| CN101454882A (en) * | 2006-03-24 | 2009-06-10 | 飞兆半导体公司 | High density trench fet with integrated schottky diode and method of manufacture |
| US7646058B2 (en) * | 2007-06-05 | 2010-01-12 | Force-Mos Technology Corporation | Device configuration and method to manufacture trench MOSFET with solderable front metal |
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| US20080246082A1 (en) * | 2007-04-04 | 2008-10-09 | Force-Mos Technology Corporation | Trenched mosfets with embedded schottky in the same cell |
| US7626231B1 (en) * | 2008-06-23 | 2009-12-01 | Force Mos Technology Co., Ltd. | Integrated trench MOSFET and junction barrier schottky rectifier with trench contact structures |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101107718A (en) * | 2005-02-11 | 2008-01-16 | 万国半导体股份有限公司 | Power metal oxide semiconductor assembly |
| CN101454882A (en) * | 2006-03-24 | 2009-06-10 | 飞兆半导体公司 | High density trench fet with integrated schottky diode and method of manufacture |
| US7646058B2 (en) * | 2007-06-05 | 2010-01-12 | Force-Mos Technology Corporation | Device configuration and method to manufacture trench MOSFET with solderable front metal |
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