CN102147568A - Photolithography method and double patterning strategy - Google Patents
Photolithography method and double patterning strategy Download PDFInfo
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- CN102147568A CN102147568A CN2010102466900A CN201010246690A CN102147568A CN 102147568 A CN102147568 A CN 102147568A CN 2010102466900 A CN2010102466900 A CN 2010102466900A CN 201010246690 A CN201010246690 A CN 201010246690A CN 102147568 A CN102147568 A CN 102147568A
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Abstract
The invention discloses a photolithography method and a double patterning strategy. A method of lithography patterning includes forming a first resist pattern on a substrate, wherein the first resist pattern including a plurality of openings. A second resist pattern is formed on the substrate and within the plurality of openings of the first resist pattern, wherein the second resist pattern includes at least one opening therein on the substrate. The first resist pattern is removed to uncover the substrate underlying the first resist pattern. The invention could improve the manufacturing productivity and the product quality as well as reduce the manufacturing cost.
Description
Technical field
The present invention relates to a kind of semiconductor technology, the method for particularly a kind of lithographic patterning and a kind of double patterning.
Background technology
Semiconductor technology constantly develops towards the direction of down feature sizes (feature size), and for instance, characteristic dimension is to dropping to 65 nanometers or 45 nanometers or following.Usually has high-aspect-ratio (aspect ratio) in order to resistance agent (resist) patterned layer that forms above-mentioned small-feature-size, and to keep required critical size (critical dimension, CD) quite difficult, particularly for blocking layer with high-aspect-ratio.Double patterning technology has reduced size with formation various features have now been proposed.Yet, known double patterning arts demand multiple etching technology and have the shortcoming of high manufacturing cost and low production capacity.
Summary of the invention
For overcoming defective of the prior art, one embodiment of the invention discloses a kind of lithographic patterning method, comprising: form one first resistance agent pattern in a substrate, have a plurality of openings in the first resistance agent pattern and be positioned in the substrate; The first resistance agent pattern is toasted, to form a resistance agent pattern that toasted; And in substrate and a plurality of openings that are positioned at the resistance agent pattern that toasted form one second blocking layers, the resistance agent pattern that wherein toasted is insoluble to second blocking layer.
Another embodiment of the present invention discloses a kind of lithographic patterning method, comprising: form one first resistance agent pattern in a substrate, have a plurality of openings in the first resistance agent pattern and be positioned in the substrate; The first resistance agent pattern is toasted, to form a resistance agent pattern that toasted; In substrate and a plurality of openings that are positioned at the resistance agent pattern that toasted form one second blocking layers; Second blocking layer is exposed, with feature and at least one the unexposed feature that forms at least one exposure; And, hinder the agent pattern to form one second by removing resistance agent pattern toast and the feature of exposure.
One embodiment of the invention discloses a kind of double patterning method, comprise: in a substrate, form one first eurymeric resistance agent pattern, first eurymeric resistance agent pattern is made of one first eurymeric blocking layer with a plurality of openings, and the first eurymeric blocking layer comprises thermal acid generator, cross linking agent or high cosolvent; First eurymeric resistance agent pattern is toasted, to form a resistance agent pattern that toasted; In substrate and a plurality of openings that are positioned at the resistance agent pattern that toasted form one second eurymeric blocking layers; The second eurymeric blocking layer is exposed, in substrate, to form resistance agent feature and a plurality of unexposed resistance agent feature of a plurality of exposures; And the resistance agent feature by the resistance agent pattern that provides a solvent to remove to toast and exposure and stay unexposed resistance agent feature, to form one second eurymeric resistance agent pattern.
The present invention can improve manufacturing production capacity and product quality, and reduces manufacturing cost.
Description of drawings
Fig. 1 to Fig. 9 illustrates the semiconductor device diagrammatic cross-section during each manufacturing step according to an embodiment.
Figure 10 illustrates the lithographic patterning method flow diagram according to an embodiment.
Wherein, description of reference numerals is as follows:
100～semiconductor device;
110～substrate;
112～material layer;
114～mask layer;
116～anti-reflecting layer;
118～the first resistance agent patterns/eurymeric resistance agent pattern;
The 118 '～resistance agent pattern that toasted;
120～the second blocking layers;
120 '～unexposed resistance agent feature;
121～opening;
200～method;
202,204,206,208,210,212,214,216,218～step;
P～spacing.
Embodiment
Scrutable is that the following disclosure of this instructions provides many different embodiment or example, to implement different characteristic of the present invention.And the following disclosure of this instructions is the particular example of each member of narration and arrangement mode thereof, in the hope of simplifying the explanation of invention.Certainly, these specific examples are not in order to limit the present invention.For example, be formed on one first feature one first feature or the top if the following disclosure of this instructions has been narrated, represent that promptly it has comprised formed above-mentioned first feature is the embodiment that directly contacts with above-mentioned second feature, also comprised still and additional feature can be formed between above-mentioned first feature and above-mentioned second feature, and the embodiment that above-mentioned first feature and above-mentioned second feature may directly not contacted.In addition, can in each example, use label and/or the symbol that repeats in this instructions.Its purpose is to reach purpose clearly in order to reach to simplify, and is not to concern each other in order to limit described each embodiment and/or each structural arrangements.
Please refer to Fig. 1 and Figure 10, in one embodiment, carry out the initial step 202 of method 200, in a substrate 110, form one or more base material (underlying material) layer (being also referred to as substrate layer).Substrate 110 can be made of following material: silicon or other suitable elemental semiconductors (elementary semiconductor), for example diamond or germanium; Suitable compound semiconductor (compound semiconductor), for example silit, indium arsenide or indium phosphide; Or suitable alloy semiconductor, for example carbon SiGe, gallium arsenide phosphide or phosphorus indium gallium.In addition, in other embodiments, substrate 110 comprises the non-semiconductor material, for example be used for tft liquid crystal and show (thin-film-transistor liquid crystal display, TFT-LCD) device or fused quartz (fused quartz) or be used for the calcium fluoride of photomask (photomask/mask).Moreover in other embodiments, substrate 110 can comprise various doped region, dielectric characterization parts and multiple layer inner connection line (interconnect).In one embodiment, substrate 110 comprises various doping features, it is used for various microelectronics member, for example CMOS transistor (complementary metal-oxide-semiconductor filed-effect transistor, CMOSFET), imageing sensor, storage unit and/or capacity cell.In another embodiment, substrate 110 comprises the configuration of conductive material feature and dielectric material feature, in order to couple respectively or to isolate various microelectronics member.In another embodiment, substrate 110 comprises one or more material layer formed thereon.
In certain embodiments, substrate layer can be homogenous material layer or different multilayer material layers.In the embodiment shown in Fig. 1 to Fig. 9, a material layer 112 is formed in the substrate 110.In at least one embodiment, material layer 112 is a dielectric material, for example monox and/or low-k (low-k) material layer.In other embodiments, material layer 112 comprises silicon, polysilicon, dielectric material, conductive material or its combination.In certain embodiments, the thickness of material layer 112 is in the scope of 100 dust to 9000 dusts.For instance, at least one embodiment, the thickness of material layer 112 exists
Extremely
Scope.In one embodiment, material layer 112 is as internal layer dielectric (interlayer dielectric, ILD) layer or metal interlevel dielectric (inter-metal dielectric, IMD) layer.The dielectric material that is used for ILD layer or IMD layer comprises that monox and specific inductive capacity are less than 4 advanced low-k materials.The advanced low-k materials that is fit to comprise the fluorine silex glass (fluorinated silica glass, FSG), the monox of doping carbon, black diamond (Black
) (Applied Materials that the holy Plutarch in California draws), xerogel (Xerogel), air glue (Aerogel), noncrystalline fluorocarbons (amorphous fluorinated carbon), Parylene (parylene), benzocyclobutene (bis-benzocyclobutenes, BCB), SiLK (Dow Chemical of the close Derain of Michigan), polyimide (polyimide) and/or other poriness macromolecular materials that is fit to.Dielectric material can utilize rotary coating (spin-on coating) method, chemical vapor deposition (chemical vapor deposition, CVD) or other suitable technologies manufacture, but be not limited to this.
In at least one embodiment, a mask layer 114 can be formed on the material layer 112.In the present embodiment, mask layer 114 comprises silicon nitride, silicon oxynitride or other suitable material layers, and it forms by suitable technology, for example the CVD depositing operation.In certain embodiments, the thickness of mask layer 114 exists
Extremely
Scope, and as follow-up hard mask layer of carrying out patterned material layer 112 during the etch process and/or substrate 110.
In addition, in at least one embodiment, one anti-reflecting layer (anti-reflective coating, ARC) layer 116 is formed on the mask layer 114, with the reflection during the reduction photolithographic exposure technology, its be also referred to as the top anti-reflective layer (top ARC, TARC) or bottom anti-reflection layer (bottom ARC, BARC).In an example, the thickness of anti-reflecting layer 116 exists
Extremely
Scope.In other embodiments, when mask layer 114 can be simultaneously as mask layer and anti-reflecting layer, can save anti-reflecting layer 116.In each different embodiment, the various combination of the material layer that provides or next set (subset) can be used for the substrate layer in the various different application.
Please refer to Fig. 1 and Figure 10, carry out the step 204 of method 200, on anti-reflecting layer 116, form one first resistance agent pattern 118.In one embodiment, the first resistance agent pattern 118 forms for eurymeric resistance agent pattern and by the first eurymeric blocking layer is exposed and develops.In another embodiment, the first resistance agent pattern 118 forms for minus resistance agent pattern and by the first minus blocking layer is exposed and develops.The first resistance agent pattern 118 is preferably eurymeric resistance agent pattern.The characteristic of eurymeric resistance agent is that developing solution will remove the exposure area.In one embodiment, eurymeric resistance agent pattern 118 comprises chemical amplifying type (chemical amplifier, CA) resistance agent.CA resistance agent comprises the light acid producing agent, and (photoacid generator, PAG), it can be decomposed during photolithographic exposure technology and form acid.And the carrying out of catalytic reaction can produce more acid.
Make in the example one, the first eurymeric blocking layer is formed on the semiconductor device 100, and then carries out patterning by first photoetching process and form the first resistance agent pattern 118, as shown in Figure 1.The characteristic of the first resistance agent pattern 118 is to carry out after rigid baking (hard baking) technology, and it is insoluble in another resistance agent material and dissolves in a developer solution.In one embodiment, the resistance agent material of the first resistance agent pattern 118 also comprises thermal acid generator (thermal-acid generator), and it can produce more acid during follow-up baking process.In another embodiment, the resistance agent material of the first resistance agent pattern 118 also comprises cross linking agent (cross-linker), and it can cause the interlinkage reaction during follow-up baking process.In another embodiment, the resistance agent material of the first resistance agent pattern 118 comprises some adjuvants, for example interfacial agent (surfactant) or high cosolvent (high-dissolution agent), it can be suppressed in another resistance agent material dissolved and can promote dissolving in developer solution or in the developing process during follow-up baking process.
The first resistance agent pattern 118 comprises a plurality of eurymeric resistance agent features and a plurality of openings that defined by eurymeric resistance agent feature, and the substrate layer that is positioned at opening is uncovered.
First photoetching process has been used an etching system and one first photomask.The opening of the first resistance agent pattern 118 forms according to integrated circuit patterns set in first photomask.In one embodiment, eurymeric photoresistance feature comprises a spacing P, and it is defined as the distance of a feature of the first resistance agent pattern 118 to adjacent feature.In certain embodiments, spacing P is in the scope of 50 nanometers (nm) to 200 nanometers.In one embodiment, spacing P is about 100nm.The thickness of the first resistance agent pattern 118 exists
Extremely
Scope, but be not limited to this.In each different embodiment, the thickness of the first resistance agent pattern 118 exists
Extremely
Scope or
Extremely
Scope.In certain embodiments, first photoetching process that is used to form the first resistance agent pattern 118 comprises: resistance agent coating, exposure, after expose to the sun roasting (post-exposure baking) and develop.In addition, according to other embodiment, first photoetching process comprises in addition: soft roasting (soft baking), photomask are aimed at (mask aligning) and/or hard roasting (hard baking).For instance, at least one embodiment, the exposure technology of being carried out is that semiconductor device 100 is exposed under the light beam via first photomask.
Please refer to Fig. 2 and Figure 10, carry out the step 206 of method 200, before forming second blocking layer 120, hinder roasting (or the resistance agent baking) technology of exposing to the sun after agent pattern 118 carries out first.This baking process is in order to the first resistance agent pattern 118 that hardens, and prevents that it from deforming because of photoetching process that the follow-up formation second resistance agent pattern is carried out.In one embodiment, baking process comprises heat curing (thermal curing).In other embodiments, curing process comprises that one or more ultraviolet light (UV) solidifies, ion injects bombardment and electron beam treatment.After carrying out baking process, the first resistance agent pattern 118 changes into a resistance agent pattern 118 ' that toasted.In one embodiment, stoving time was 20 seconds to 200 seconds scope.Baking temperature needs the resistance agent pattern 118 ' that toasted is dissolved in the developer, is insoluble to simultaneously in second blocking layer.In one embodiment, baking temperature is about 100 ℃ to 250 ℃ scope.In another embodiment, baking temperature is about 150 ℃ to 250 ℃ scope.
Please refer to Fig. 3 and Figure 10, carry out the step 208 of method 200, on semiconductor device 100, form one second blocking layer 120.In one embodiment, second blocking layer 120 is the eurymeric blocking layer.In another embodiment, second blocking layer 120 is the minus blocking layer.In at least one embodiment, second blocking layer 120 is the eurymeric blocking layer.In an example, second blocking layer 120 is formed on the substrate layer of substrate 110 tops and is positioned at the opening that is defined by the resistance agent pattern 118 ' that toasted.Second blocking layer 120 is coated on the semiconductor device 100, make the upper surface of second blocking layer 120 be lower than the upper surface of the resistance agent pattern 118 ' that toasted, and the resistance agent pattern 118 ' that toasted is not covered by second blocking layer 120.In one embodiment, adjust the second resistance agent to be coated, make the upper surface of second blocking layer can not be formed at the upper surface of the resistance agent pattern 118 ' that toasted to sufficiently high surface tension.In another embodiment, the speed of adjusting rotary coating is not covered the upper surface of the resistance agent pattern 118 ' that toasted to sufficiently high speed by second blocking layer 120.
Please refer to Fig. 4 and Figure 10, carry out the step 210 and 212 of method 200, come patterning second blocking layer 120 with one second photoetching process.In second photoetching process, use second mask and an etching system to come second blocking layer 120 is exposed with one second predefine pattern.Form the resistance agent feature and the unexposed resistance agent feature (not shown) of a plurality of exposures by second exposure technology.If second blocking layer 120 is the eurymeric blocking layer, then remove the resistance agent feature of exposure by follow-up developing process.In one embodiment, developing process can not removed the resistance agent pattern 118 ' that toasted.
Fig. 4 illustrates second blocking layer, 120 parts that stay after the development step, and it is the unexposed resistance agent in anti-reflecting layer 116 tops feature 120 ' and the resistance agent pattern 118 ' that toasted.In another embodiment, the resistance agent pattern that toasted 118 ' is removed by developing process, only stays the unexposed resistance agent feature 120 ' (as shown in Figure 5) that is positioned at anti-reflecting layer 116 tops.
In an example, unexposed resistance agent feature has periodically configuration and the spacing scope about 50nm to 200nm.In one embodiment, the resistance agent feature of each exposure is positioned over a feature that flatly centers on the resistance agent pattern 118 ' that toasted.In certain embodiments, expose to the sun after second photoetching process also comprises curing process, development and hard curing process, wherein after second blocking layer 120 being exposed and develop, local anti-reflecting layer 116 is not capped.
Please refer to Fig. 5 and Figure 10, carry out the step 214 of method 200,, then remove the resistance agent pattern 118 ' that toasted therebetween if the resistance agent pattern 118 ' that toasted is not removed in developing process.In one embodiment, can select the solvent that is fit to, the resistance agent pattern 118 ' that toasted is dissolved in the solvent, unexposed resistance agent feature 120 ' then is insoluble in the solvent.Therefore, can remove the resistance agent pattern 118 ' that toasted by above-mentioned solvent and stay unexposed resistance agent feature 120 '.In an example, an organic solvent is used for semiconductor device 100, the resistance agent pattern 118 ' that toasted with selective removal.In another example, the resistance agent pattern 118 ' that toasted is removed by the developing process that step 212 is carried out in fact.In this example, can carry out step 214, but when carrying out step 212, remove the resistance agent pattern 118 ' that toasted.Therefore the removal of the resistance agent pattern 118 ' that toasted and the patterning of the second eurymeric blocking layer are to finish in one step.Removing the resistance agent pattern 118 ' toasted afterwards, a plurality of openings 121 are formed in the unexposed resistance agent feature 120 ', as shown in Figure 5.Opening 121 is defined jointly by first photomask and second photomask, and forms by above-mentioned each different process.The configuration of unexposed resistance agent feature 120 ' and the resistance agent pattern that toasted 118 ' are relevant and constitute the double patterning structure.In one embodiment, the spacing that configuration marked off of formed opening 121 is that first eurymeric or minus hinder half of agent pattern in the unexposed resistance agent feature 120 '.The spacing that opening 121 is defined reduces by half, thereby has dwindled minimum feature size.Therefore opening 121 can be in order to form various contact holes or groove in different application.
Please refer to Fig. 6 and Figure 10, carry out the step 216 of method 200, the etching substrate layer.The mask layer 114 that is positioned at opening 121 is not covered by unexposed resistance agent feature 120 ', and is removed in etch process, is transferred to mask layer 114 with the opening 121 that second blocking layer 120 is defined.Selected etch process need make the rate of etch of mask layer 114 be higher than the rate of etch of second blocking layer 120.Therefore, the mask layer 114 in the opening 121 is removed during etch process.In an example, remove the anti-reflecting layer 116 in the opening 121 during the etch process that in this step, is carried out.In another example, the anti-reflecting layer 116 in the opening 121 is removed when carrying out step 214 by the solvent of removing the resistance agent pattern 118 ' that toasted.
Please refer to Fig. 7 and Figure 10, carry out the step 218 of method 200, wherein after etching is positioned at the substrate layer of the opening 121 that is defined by second blocking layer 120, remove unexposed resistance agent feature 120 '.In one embodiment, step 218 is carried out known wet type and is divested or plasma ashing, to remove unexposed resistance agent feature 120 '.For instance, in one embodiment, carry out the oxygen plasma ashing, to remove unexposed resistance agent feature 120 '.In addition, at least one embodiment, can be by identical plasma ashing technology, to remove anti-reflecting layer 116 and unexposed resistance agent feature 120 ' simultaneously.
In at least one embodiment, utilize the mask layer 114 of patterning to come etched material layer 112 as hard mask, be transferred to material layer 112 with the opening that will be defined in mask layer 114, as shown in Figure 8.Material layer 112 is a plurality of grooves or contact hole because of patterning forms.In certain embodiments, etch process comprises the combination of dry ecthing, wet etching or wet etching and dry ecthing.Mask layer 114 is as hard mask in this step, so its etch-resistance is higher than the etch-resistance of material layer 112.In certain embodiments, the etching gas that is fit to, for example HBr, Cl are adopted in dry ecthing
2, SF
6, O
2, Ar and/or He.Mask layer 114 may have partially spent during etch process.Remove remaining mask layer 114 afterwards, as shown in Figure 9.
The described method of Fig. 1 to Figure 10 is to provide a kind of double patterning technology according to the various kenels of this instructions.The method is implemented double exposure and substrate layer or substrate is implemented single etch process, thereby reduces manufacturing cost, and the CD variable is minimized.Can present other advantages at different embodiment and/or in using.For instance, can get rid of the problem that overlay error in the existing double patterning technology (overlay error) causes the size change of IC feature (for example, contact hole or metal wire).In another example, come the etching substrate layer owing to only adopt single etch process, therefore can reduce manufacturing cost.Compared to known double patterning and dual engraving method, can improve and make production capacity and product quality.In another example, because the mask layer 114 that can select to have higher etch-resistance, so method 200 can the thicker rete of etching.
The various embodiment of lithographic patterning method 200 more than has been described.Other embodiment comprise retouching, change, the newly-increased and extension of having done without departing from the spirit and scope of the present invention.In one embodiment, for example, go out a plurality of contact holes and be formed in the material layer 112 by first eurymeric and second eurymeric resistance agent pattern definition.In addition, in other embodiments, go out a plurality of grooves and be formed in the material layer 112 by first eurymeric and second eurymeric resistance agent pattern definition.In another embodiment, do not use bottom anti-reflection layer 116 and/or mask layer 114.In another example, eurymeric and minus resistance agent pattern directly are formed in the substrate 110.
In certain embodiments, the light beam that is used for that first and second blocking layer is exposed is ultraviolet light or extreme ultraviolet light (extreme ultraviolet, EUV), for example take from KrF (KrF) excimer laser the 248nm light beam, take from the 193nm light beam of argon fluoride (ArF) excimer laser.In other embodiments, photoetching process adopts other exposure modes or technology, for example coaxial (on-axis), off-axis (off-axis), the four coupling utmost points (quadripole) or quadripole (dipole) exposure technique.In addition, can utilize other methods that are fit to carry out or replace exposure technology, for example not have that photomask (maskless) photoetching, electron beam write, ion beam writes and molecular template (molecular imprint) technology.In another example, first and second photomask that is used for method 200 can adopt other photomask technologies.For instance, first pattern (or second optical mask pattern) can be formed at a phase-shift photomask (phase shift mask, PSM) in, its image that is printed off in some cases is better than binary (binary) photomask.
In one embodiment, eurymeric resistance agent pattern comprises chemical amplifying type (CA) resistance agent.In another embodiment, the minus blocking layer comprises to acid being the minus resistance agent of inertia.Among the another embodiment, the minus blocking layer comprises cyclisation synthetic rubber resin (cyclized synthetic rubber resin), two propylene azide (bis-acrylazide), aromatic hydrocarbon solvent (aromatic solvent).In another embodiment, eurymeric resistance agent comprises in addition as Photoactive compounds (photoactive compound, PAC) phenolics (novolac resin), dinitrogen base elder brother at the tenth of the twelve Earthly Branches (diazonaphthoquinone, DNQ) and as propylene glycol monomethyl ether (the propylene glycol methyl ether of solvent, PGME) (or propylene glycol monomethyl ether (propylene glycol monomethyl ether acetate, PGMEA) or ethyl lactate (ethyl lactate)).In another example, minus resistance agent comprises material, makes the etch-resistance of the etch-resistance of minus resistance agent greater than eurymeric resistance agent.
As described in an embodiment before, removal first eurymeric resistance agent that step 214 is carried out can be incorporated into step 212.For instance, the developing solution that develops with second blocking layer can adjust or be designed to remove simultaneously first eurymeric resistance agent pattern.
In an example, coating that can be extra to the first resistance agent pattern 118 is with protection and strengthen eurymeric resistance agent feature.For instance, in one embodiment, on the first resistance agent pattern 118, be coated with macromolecular material.In the another example, the BARC material can be used for the coating of the first resistance agent pattern 118, and wherein the thickness of Tu Bu BARC layer exists
Extremely
Scope.
The invention provides a kind of lithographic patterning method.The method is included in and forms one first resistance agent pattern in the substrate, is positioned in the substrate and have a plurality of openings in the first resistance agent pattern; The first resistance agent pattern is toasted, to form a resistance agent pattern that toasted; And in substrate and a plurality of openings that are positioned at the resistance agent pattern that toasted form one second blocking layers, the resistance agent pattern that wherein toasted is insoluble to second blocking layer.
In one embodiment, the first resistance agent pattern comprises that the eurymeric resistance agent material and second blocking layer comprise eurymeric resistance agent material.In at least one embodiment, the second resistance agent pattern is same as the first resistance agent pattern.In other embodiments, second eurymeric resistance agent material is different from first eurymeric resistance agent material.In certain embodiments, the rate of etch of the first resistance agent pattern is higher than the rate of etch of the second resistance agent pattern in an etch process, and the removal of the first resistance agent pattern comprises and carry out an etch process, with respect to the second resistance agent pattern and the selective removal first resistance agent pattern.In certain embodiments, the removal of the first resistance agent pattern comprises with the dissolution with solvents first resistance agent pattern, and comprises and apply a solvent, its solubilized first resistance agent pattern and can not dissolve the second resistance agent pattern.In certain embodiments, the method also is included in and removes after the first resistance agent pattern substrate in the opening of the etching second resistance agent pattern.In certain embodiments, substrate etching comprises the etching substrate, to form the wherein at least a of a plurality of contact holes and a plurality of grooves in substrate.
This instructions also provides the double patterning method of another embodiment.The method is included in and forms one first eurymeric resistance agent pattern in the substrate, and first eurymeric resistance agent pattern is made of the first eurymeric blocking layer with a plurality of openings, and the first eurymeric blocking layer comprises thermal acid generator, cross linking agent or high cosolvent; First eurymeric resistance agent pattern is toasted, to form a resistance agent pattern that toasted; In substrate and a plurality of openings that are positioned at the resistance agent pattern that toasted form one second eurymeric blocking layers; The second eurymeric blocking layer is exposed, in substrate, to form resistance agent feature and a plurality of unexposed resistance agent feature of a plurality of exposures; And the resistance agent feature by the resistance agent pattern that provides a developer solution to remove to toast and exposure and stay unexposed resistance agent feature, to form the second resistance agent pattern.
In the method, remove the resistance agent pattern that toasted and the resistance agent feature of exposure by developer solution.In certain embodiments, form second blocking layer and comprise and be rotated coating process, it comprises the adjustment rotational speed, makes the minus blocking layer be thinner than the first resistance agent pattern.In at least one embodiment, spin coating process comprises coating one minus blocking layer, and adjusts its surface tension, makes second blocking layer be thinner than the first resistance agent pattern.
In various different embodiment, substrate comprises the semiconductor material layer, and it comprises that also a dielectric materials layer is formed on the semiconductor material layer.In certain embodiments, the method comprises that also a plurality of openings that defined via minus resistance agent pattern come the etching substrate.
Above diagrammatic illustration the feature of a plurality of embodiment of the present invention, the those of ordinary skill under making in the technical field can be understood more easily for follow-up detailed description of the present invention.Those of ordinary skill under any in the technical field should be appreciated that this instructions can be easily as the change or the design basis of other structure or technology, with the purpose that is same as the embodiment of the invention and/or obtain identical advantage.Those of ordinary skill under any in the technical field also can be understood with above-mentioned equivalent configurations or technology and not break away from spirit of the present invention and the protection domain, and can be without departing from the spirit and scope of the present invention, when doing to change, substitute and retouch.
Claims (12)
1. lithographic patterning method comprises:
In a substrate, form one first resistance agent pattern, have a plurality of openings in this first resistance agent pattern and be positioned in this substrate;
This first resistance agent pattern is toasted, to form a resistance agent pattern that toasted; And
In this substrate and a plurality of openings that are positioned at the resistance agent pattern of this baking form one second blocking layers, wherein the resistance agent pattern of this baking is insoluble to this second blocking layer.
2. lithographic patterning method as claimed in claim 1, wherein this first resistance agent pattern is made of one first eurymeric blocking layer with thermal acid generator, cross linking agent, interfacial agent or high cosolvent.
3. lithographic patterning method as claimed in claim 1 also comprises:
This second blocking layer is exposed, in this second blocking layer, to define at least one opening; And
Apply a chemical agent, to remove the resistance agent pattern of this baking.
4. lithographic patterning method as claimed in claim 1 also comprises:
This second blocking layer is exposed, in this substrate, to define a plurality of exposures and unexposed feature; And
Apply a chemical agent,, and in this substrate, stay described a plurality of unexposed feature with the resistance agent pattern of removing this baking and the feature of described a plurality of exposures.
5. lithographic patterning method as claimed in claim 1 also comprises:
This second blocking layer is exposed, in this substrate, to define a plurality of exposures and unexposed feature;
Apply a developer solution, removing the feature of described a plurality of exposures, and in this substrate, stay described a plurality of unexposed feature; And
Implement an etch process, with the resistance agent pattern that should toast with respect to described a plurality of unexposed feature selective removals.
6. lithographic patterning method comprises:
In a substrate, form one first resistance agent pattern, have a plurality of openings in this first resistance agent pattern and be positioned in this substrate;
This first resistance agent pattern is toasted, to form a resistance agent pattern that toasted;
In this substrate and a plurality of openings that are positioned at the resistance agent pattern of this baking form one second blocking layers;
This second blocking layer is exposed, with feature and at least one the unexposed feature that forms at least one exposure; And
The resistance agent pattern by removing this baking and the feature of this exposure are to form one second resistance agent pattern.
7. lithographic patterning method as claimed in claim 6, wherein this first resistance agent pattern is made of one first eurymeric blocking layer with thermal acid generator, cross linking agent or high cosolvent.
8. lithographic patterning method as claimed in claim 6, wherein the resistance agent pattern of this baking is insoluble to this second blocking layer, and is dissolved in a developer solution.
9. lithographic patterning method as claimed in claim 6 is wherein removed the resistance agent pattern of this baking and the feature of this exposure by a developer solution.
10. double patterning method comprises:
Form one first eurymeric resistance agent pattern in a substrate, this first eurymeric resistance agent pattern is made of one first eurymeric blocking layer with a plurality of openings, and this first eurymeric blocking layer comprises thermal acid generator, cross linking agent or high cosolvent;
This first eurymeric resistance agent pattern is toasted, to form a resistance agent pattern that toasted;
In this substrate and a plurality of openings that are positioned at the resistance agent pattern of this baking form one second eurymeric blocking layers;
This second eurymeric blocking layer is exposed, in this substrate, to form resistance agent feature and a plurality of unexposed resistance agent feature of a plurality of exposures; And
Resistance agent feature by resistance agent pattern that a solvent removes this baking and described a plurality of exposures are provided also stays described a plurality of unexposed resistance agent feature, to form one second eurymeric resistance agent pattern.
11. double patterning method as claimed in claim 10, wherein form this second eurymeric blocking layer and comprise enforcement one spin coating process, and wherein this spin coating process comprises the adjustment rotational speed, makes this second eurymeric blocking layer be thinner than this first eurymeric blocking layer, and
Comprise the surface tension of adjusting this second eurymeric blocking layer, make this second eurymeric blocking layer be thinner than this first eurymeric blocking layer.
12. double patterning method as claimed in claim 10, wherein this solvent is a developer solution.
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|---|---|---|---|
| US12/702,737 | 2010-02-09 | ||
| US12/702,737 US8741552B2 (en) | 2009-02-11 | 2010-02-09 | Double patterning strategy for contact hole and trench in photolithography |
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| CN102147568A true CN102147568A (en) | 2011-08-10 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103474337A (en) * | 2013-09-22 | 2013-12-25 | 上海华力微电子有限公司 | Method for manufacturing high-evenness grid electrode lines |
| CN105118780A (en) * | 2015-07-30 | 2015-12-02 | 中国电子科技集团公司第五十五研究所 | Method of reducing GaN HEMT device ohm contact resistance |
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| CN105556657A (en) * | 2013-09-13 | 2016-05-04 | 高通股份有限公司 | Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device |
| CN105556657B (en) * | 2013-09-13 | 2018-11-20 | 高通股份有限公司 | The reversed self-aligned double patterning case chemical industry skill of manufacture is made in back segment for semiconductor devices |
| CN103474337A (en) * | 2013-09-22 | 2013-12-25 | 上海华力微电子有限公司 | Method for manufacturing high-evenness grid electrode lines |
| CN103474337B (en) * | 2013-09-22 | 2016-02-03 | 上海华力微电子有限公司 | Make the method for grid lines |
| CN105118780A (en) * | 2015-07-30 | 2015-12-02 | 中国电子科技集团公司第五十五研究所 | Method of reducing GaN HEMT device ohm contact resistance |
| CN105118780B (en) * | 2015-07-30 | 2018-08-14 | 中国电子科技集团公司第五十五研究所 | A method of reducing GaN HEMT device ohmic contact resistances |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201128683A (en) | 2011-08-16 |
| TWI515768B (en) | 2016-01-01 |
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