CN100516912C - Circuit connection state detection system and method - Google Patents
Circuit connection state detection system and method Download PDFInfo
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- CN100516912C CN100516912C CNB2007101059680A CN200710105968A CN100516912C CN 100516912 C CN100516912 C CN 100516912C CN B2007101059680 A CNB2007101059680 A CN B2007101059680A CN 200710105968 A CN200710105968 A CN 200710105968A CN 100516912 C CN100516912 C CN 100516912C
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- down resistor
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- 239000003990 capacitor Substances 0.000 claims description 54
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Abstract
The invention provides a system for detecting circuit connection state, including a transmitter, a receiver and a driving device, the transmitter and the driving device, the driving device and the receiver are connected via AC coupling difference circuit, also including a PCIe (Peripheral Component Interconnect Express) load for forming a grounding current loop when detecting circuit connection state. The invention provides a method for detecting circuit connection state, which is capable of using general SerDes driving chips in PCIe link and avoiding the problem of non-passing Receiver Detector by adding PCIe load to receiving part of difference circuit driving chip.
Description
Technical field
The present invention relates to communication technical field, relate in particular to a kind of circuit connection state detection system and method.
Background technology
Now a lot of electronic equipments rely between SerDes (Serializer and Deserializer, serializer and deserializer) the link realization equipment, the interconnection between the device interior device.PCIe (Peripheral ComponentInterconnect Express, the external devices interconnect extended) belongs to a kind of in the SerDes technology, be a kind of serial, between the point-to-point chip or the interconnection technique between the equipment, the normalized definition of PCIe a kind of device design architecture of layering, comprise processing layer, data link layer, Physical layer.Whether equipment all will detect opposite equip. and connect on the throne on the PCIe link by the testing circuit of its transmitter inside, to be operated in normal condition still be electric holding state thereby control this serial SerDes link, and this process is called as receiver and detects (Receiver Detect).
The receiving circuit detection-phase is the inlet of the various state exchanges of whole PCIe link initialization, can operate as normal most important for the PCIe link, if the PCIe link can not pass through this step of receiver in-place detection, transmitter can think that link the other side does not have connection device, will can not enter follow-up duty.
The ultimate principle of receiver in-place detection utilizes RC (resistance capacitance) the network time that discharges and recharges to realize.A cover testing circuit module is all contained in the transmitter inside of each PCIe equipment, and the testing circuit module sends the pulse of common mode on differential link, judge by the impulse electricity waveform of common mode pulse on the link whether opposite end PCIe equipment exists then.Fig. 1 a and Fig. 1 b are the synoptic diagram of PCIe link receiver in-place detection, and link passes through capacitor C
TXCarry out AC coupling, C
TXValue is 75nF～200nF; The receiver electric attribute is for passing through 50 Ohmage Z
RXSingle-ended over the ground, 100 ohm of differential resistor, do not have cross-over connection resistance between two input ends of receiver.Concrete testing process is as follows: the PCIe chip reset or power up after, the differential signal transmitter drives a stable voltage on transmit port D+ and D-terminal, as shown in Figure 2, this voltage can be Vdd, (Ground), or any common mode voltage between Vdd and the ground.Transmitter change common mode voltage, differential lines detects pulse to last transmission homophase common mode.If initial common mode voltage is Vdd, so can be to the ground driving voltage; If initial common mode voltage is ground, so can be to the Vdd driving voltage; If initial common mode voltage is between Vdd and ground, transmitter can be with opposite direction driving voltage.
Wherein, Fig. 1 a is a receiver situation not on the throne, and charging rate is:
Z
TX×(C
pad+C
interconnect)；(1)
Fig. 1 b is that receiver situation charging rate on the throne is:
Z
TX×(C
TX+C
pad+C
interconnect)；(2)
Wherein, C
PadBe stray capacitance, C
InterconnectFor connecting electric capacity in the transmitter.
Transmitter is by judging that common mode detection pulse charge time constant size detects receiver and whether exists.If charging rate is big, then receiver exists, and the charge waveforms of detection pulse as shown in Figure 4; If charging rate is little, then receiver does not exist, and the charge waveforms of detection pulse as shown in Figure 3.
When using the PCIe bus, usually need to use the SerDes chip for driving or Mux/Demux (multiplex/demultiplex) chip drives the PCIe link signal.For example oversize when link, PCIe device drives ability is not enough, and need adopt the SerDes chip for driving that the PCIe link signal is driven once more in the middle of link this moment.In addition, since systemic-function need can to adopt the Mux/Demux chip when professional up and down.When selecting these SerDes chip for driving for use, may select general SerDes chip for driving for use, adopt the 8B/10B coding, can use AC coupling.
As shown in Figure 5, for the use synoptic diagram of general SerDes chip for driving in the PCIe link, all use AC coupling between the transmitter of SerDes chip for driving and PCIe equipment and the receiver.These general SerDes chip for driving receiving port inside do not have single-ended direct current 50 Ohmage ground connection.In general, the receiving port synoptic diagram of general SerDes chip for driving is shown in Fig. 6 a or Fig. 6 b.
Because the receiver in-place detection is by detecting pulse discharging and recharging time constant and judge whether receiver is arranged on the link on the link.The current return that these general SerDes chip for driving receiving ports are not connected with ground.So, send at transmitter under the situation of homophase detection pulse, even receiving port normally has been connected to after the ac coupling capacitor of transmitter, two in-phase pulse signals in the differential link can not form current return over the ground, the large time constant charge waveforms that still can not occur wishing in transmitter inside, thus erroneous judgement does not connect normally for SerDes chip for driving receiving port.
Summary of the invention
The embodiment of the invention provides a kind of circuit connection state detection system and method, when solving that common SerDes chip for driving is used for the PCIe link in the prior art, can not detect by SerDes chip for driving receiving port connection status, thus the problem that causes link normally not use.
A kind of circuit connection state detection system provided by the invention, comprise transmitter, receiver and driving arrangement, between described transmitter and the described driving arrangement, be connected by AC coupling differential circuit between described driving arrangement and the described receiver, described driving arrangement receiving port also comprises the PCIe load, when being used for the circuit connection state detection, constitute current return over the ground, described PCIe load comprises ac coupling capacitor and pull down resistor, described pull down resistor is used for difference transmission lines is connected with ground, and described ac coupling capacitor is between the pull down resistor and described driving arrangement receiving port of described PCIe load.
Described pull down resistor comprises first pull down resistor and second pull down resistor, respectively difference transmission lines is connected with ground.
The described ac coupling capacitor of described PCIe load comprises first ac coupling capacitor and second ac coupling capacitor, described first ac coupling capacitor is between described first pull down resistor and described driving arrangement receiving port, and described second ac coupling capacitor is between described second pull down resistor and described driving arrangement receiving port.
The present invention also provides a kind of receiver detection method, be applied to comprise in the system of transmitter, receiver and driving arrangement, wherein, between described transmitter and the described driving arrangement, be connected by AC coupling differential circuit between described driving arrangement and the described receiver, may further comprise the steps:
At described driving arrangement receiving port the PCIe load is set, comprise ac coupling capacitor and pull down resistor, described pull down resistor is used for difference transmission lines is connected with ground, and described ac coupling capacitor is between the pull down resistor and described driving arrangement receiving port of described PCIe load;
Described transmitter generates the detection pulse and is linked into two difference transmission lines respectively;
Described transmitter is determined described driving arrangement receiving port connection status by detecting described pulse waveform charging rate.
Described pull down resistor comprises first pull down resistor and second pull down resistor, respectively difference transmission lines is connected to ground.
The described ac coupling capacitor of described PCIe load comprises first ac coupling capacitor and second ac coupling capacitor, described first ac coupling capacitor is between described first pull down resistor and described driving arrangement receiving port, and described second ac coupling capacitor is between described second pull down resistor and described driving arrangement receiving port.
Described transmitter determines that by detecting described pulse waveform charging rate driving arrangement receiving port connection status is specially: by determine the connection status of driving arrangement receiving port and transmitter in the time of detected pulse voltage value of Preset Time or arrival predetermined pulse magnitude of voltage.
Compared with prior art, the embodiment of the invention has the following advantages:
In the embodiments of the invention,, form the current return on transmitter and ground, the problem of avoiding the receiver in-place detection not pass through by increasing the PCIe matched load at receiver-side.For example, increase the PCIe matched load, can in the PCIe link, use general SerDes chip for driving, the problem of avoiding the receiver in-place detection not pass through normally at SerDes chip for driving receiving end.
Description of drawings
Fig. 1 a is synoptic diagram when receiver is not on the throne in the prior art;
Fig. 1 b is synoptic diagram when receiver is on the throne in the prior art;
Fig. 2 is a receiver in-place detection pulse synoptic diagram in the prior art;
Fig. 3 detects pulse to discharge and recharge the waveform synoptic diagram when receiver is not on the throne in the prior art;
Fig. 4 detects pulse to discharge and recharge the waveform synoptic diagram when receiver is on the throne in the prior art;
Fig. 5 is that the SerDes chip for driving is used synoptic diagram in the prior art;
Fig. 6 a is a SerDes chip for driving receiving port synoptic diagram in the prior art;
Fig. 6 b is an another kind of SerDes chip for driving receiving port synoptic diagram in the prior art;
Fig. 7 is a kind of circuit connection state detection system structural drawing of the present invention;
Fig. 8 is the used SerDes chip for driving of an one embodiment of the invention structural drawing.
Embodiment
The invention provides a kind of detection system of circuit connection state, comprise transmitter, receiver and driving arrangement, between described transmitter and the described driving arrangement, be connected by AC coupling differential circuit between described driving arrangement and the described receiver, comprise the PCIe load at the driving arrangement receiving port, be used for the difference transmission lines of driving arrangement receiving port is connected with ground by build-out resistor, constitute ground circuit with transmitter and driving arrangement receiving port, generate large time constant and discharge and recharge waveform.
The PCIe load comprises first pull down resistor and second pull down resistor, respectively difference transmission lines is connected to ground.The PCIe load also comprises first ac coupling capacitor and second ac coupling capacitor, first ac coupling capacitor is between first pull down resistor and driving arrangement receiving port, and second ac coupling capacitor is between second pull down resistor and driving arrangement receiving port.The pull-up resistor of first ac coupling capacitor, second ac coupling capacitor and driving arrangement receiving port constitutes Hi-pass filter, plays the blocking-up direct current signal, the effect of conducting AC signal.Wherein, first pull down resistor and second pull down resistor can be single resistance, also can be resistor networks in parallel by a plurality of resistance or that be composed in series.
The present invention is described in detail below in conjunction with specific embodiment, as shown in Figure 7, and for the present invention uses the situation of SerDes chip for driving as driving arrangement.
As shown in Figure 7, the SerDes chip for driving is between transmitter and receiver, and connect by AC coupling, therefore, according to technical solution of the present invention, can increase a resistance-capacitance network at the differential signal receiving port of general SerDes chip for driving, construct ground circuit, this resistance-capacitance network is made up of R1 and C3, R2 and C4 respectively, and R1 and R2 are resistance to earth, and C3 and C4 are second level ac coupling capacitor.
After adding PCIe loads such as resistance-capacitance network, accomplish not influence substantially the quality of PCIe link SerDes chip for driving received signal, with reference to figure 7, it is back level at the ac coupling capacitor C1 and the C2 of PCIe link, increase drop-down 50 Ohmage R1 and R2, back level at pull down resistor also needs an ac coupling capacitor C3 and C4, plays the effect of DC-isolation.In addition, should be noted that (PrintCirciut Board at design PCB, printed circuit board (PCB)) time, the ac coupling capacitor C3 of R1 and R2 and pico farad level and C4 require the receiving port near the SerDes chip for driving among Fig. 7, otherwise influence the impedance matching of signal routing, and the selection of ac coupling capacitor C3 and C4 to be considered the input capacitance parameter of receiving port.
Among Fig. 7, the effect of ac coupling capacitor C3 and C4 is to form a Hi-pass filter with the pull-up resistor of rear end.Outside ac coupling capacitor C3 and the position of C4 before terminating resistor, so its cutoff frequency is F=1/ (2*PI*C*Rt), Rt=50 ohm.As shown in Figure 8, the Rin of certain SerDes chip for driving inside is hundreds of K ohm, and inner ac coupling capacitor is the pico farad rank, and its cutoff frequency is F=1/ (2*PI*Cin*Rin), much smaller than C3 and C4 form by frequency.Therefore, this chip is no problem by the SerDes signal of PCIe link.
In order to reach a better effect, first order ac coupling capacitor C1, when C2 selects 0.1uF, wanting of the resistance to earth R1 that adds and R2 choosing is big, for example be 100～300 ohm, so can satisfy Receiver Detect requirement, AC impedance can not change too big yet simultaneously yet.The AC differential impedance is 2 * (100～300 ohm) and 100 ohm of parallel connections of chip for driving inside, back.Ac coupling capacitor can not selected the 75nF～200nF (100nF usually) of PCIe code requirement.So ac coupling capacitor is eligible littler when using, as 10nF commonly used, direct current resistance over the ground just can be elected 500 ohm as like this, and the AC differential impedance is exactly the parallel connection of 1000 ohm and 100 ohm, general 90 ohm, so just can satisfy the requirement of signal quality.
Whether the serial connection electric capacity of level needs behind the resistance, and the selection of appearance value need be seen the electrical structure of input port of the SerDes chip for driving of back.If electrical structure shown in Figure 8, SerDes chip for driving receiving port inside has ac coupling capacitor C5 and C6, does not just need externally increase exchanges coupling capacitance C3 and C4, because direct current biasing is 0V.The SerDes chip for driving is generally repeater chip, and it has the bidirectional transmit-receive function, therefore, has two receiving ends, and its circuit principle of compositionality is identical.In addition, the present invention is not only applicable to the SerDes chip for driving, is applicable to MUX/DEMUX chip and general PHY chip etc. too.
The present invention also provides a kind of circuit connection state detection method, be applied to comprise in the system of transmitter, receiver and driving arrangement, wherein, between described transmitter and the described driving arrangement, be connected by AC coupling differential circuit between described driving arrangement and the described receiver, may further comprise the steps:
Step s101 is being provided with the PCIe load near the driving arrangement receiving port.The PCIe load comprises first pull down resistor and second pull down resistor, respectively difference transmission lines is connected to ground.The PCIe load also comprises first ac coupling capacitor and second ac coupling capacitor, first ac coupling capacitor is between first pull down resistor and driving arrangement receiving port, and second ac coupling capacitor is between second pull down resistor and driving arrangement receiving port.The pull-up resistor of first ac coupling capacitor, second ac coupling capacitor and driving arrangement receiving port constitutes Hi-pass filter, plays the blocking-up direct current signal, the effect of conducting AC signal.Wherein, first pull down resistor and second pull down resistor can be single resistance, also can be resistor networks in parallel by a plurality of resistance or that be composed in series.
Step s102, transmitter generate the detection pulse and are linked into two difference transmission lines respectively.
Step s103, transmitter is determined driving arrangement receiving port connection status by detecting the pulse waveform charging rate.The connection status of determining driving arrangement receiving port and transmitter according to detected pulse waveform is specially: in the pulse term of validity, by determine the connection status of driving arrangement receiving port and transmitter in the time of detected pulse voltage value of Preset Time or arrival predetermined pulse magnitude of voltage.
Time by arrival predetermined pulse magnitude of voltage determines that the connection status of driving arrangement receiving port and transmitter is specially: in the pulse term of validity, do not exceed Preset Time if reach the time of predetermined pulse magnitude of voltage, then the driving arrangement receiving port correctly is not connected with transmitter; In the pulse term of validity, exceed Preset Time if reach the time of predetermined pulse magnitude of voltage, then the driving arrangement receiving port correctly is connected with transmitter.
By determining that in the detected pulse voltage value of Preset Time the connection status of driving arrangement receiving port and transmitter specifically comprises: in the pulse term of validity, if pulse waveform reaches the predetermined pulse magnitude of voltage at Preset Time, then the driving arrangement receiving port correctly is not connected with transmitter; In the pulse term of validity, if pulse waveform does not reach the predetermined pulse magnitude of voltage at Preset Time, then the driving arrangement receiving port correctly is connected with transmitter.Pulse waveform reaches the predetermined pulse magnitude of voltage at Preset Time, then judges the duration that reaches the predetermined pulse magnitude of voltage again; If pulse waveform reaches the duration of predetermined pulse magnitude of voltage and exceeds Preset Time, then the driving arrangement receiving port correctly is not connected with transmitter; If pulse waveform reaches not enough Preset Time of the duration of predetermined pulse magnitude of voltage, then the driving arrangement receiving port correctly is connected with transmitter.
More than disclosed only be several specific embodiment of the present invention, still, the present invention is not limited thereto, any those skilled in the art can think variation all should fall into protection scope of the present invention.
Claims (7)
1, a kind of circuit connection state detection system, comprise transmitter, receiver and driving arrangement, between described transmitter and the described driving arrangement, be connected by AC coupling differential circuit between described driving arrangement and the described receiver, it is characterized in that, described driving arrangement receiving port also comprises the PCIe load, when being used for the circuit connection state detection, constitute current return over the ground, described PCIe load comprises ac coupling capacitor and pull down resistor, described pull down resistor is used for difference transmission lines is connected with ground, and described ac coupling capacitor is between the pull down resistor and described driving arrangement receiving port of described PCIe load.
2, circuit connection state detection system according to claim 1 is characterized in that described pull down resistor comprises first pull down resistor and second pull down resistor, respectively difference transmission lines is connected with ground.
3, as circuit connection state detection system as described in the claim 2, it is characterized in that, the described ac coupling capacitor of described PCIe load comprises first ac coupling capacitor and second ac coupling capacitor, described first ac coupling capacitor is between described first pull down resistor and described driving arrangement receiving port, and described second ac coupling capacitor is between described second pull down resistor and described driving arrangement receiving port.
4, a kind of circuit connection state detection method, be applied to comprise in the system of transmitter, receiver and driving arrangement, wherein, between described transmitter and the described driving arrangement, be connected by AC coupling differential circuit between described driving arrangement and the described receiver; It is characterized in that, said method comprising the steps of:
At described driving arrangement receiving port the PCIe load is set, comprise ac coupling capacitor and pull down resistor, described pull down resistor is used for difference transmission lines is connected with ground, and described ac coupling capacitor is between the pull down resistor and described driving arrangement receiving port of described PCIe load;
Described transmitter generates the detection pulse and is linked into two difference transmission lines respectively;
Described transmitter is determined described driving arrangement receiving port connection status by detecting described pulse waveform charging rate.
5, as circuit connection state detection method as described in the claim 4, it is characterized in that described pull down resistor comprises first pull down resistor and second pull down resistor, respectively difference transmission lines is connected to ground.
6, as circuit connection state detection method as described in the claim 5, it is characterized in that, the described ac coupling capacitor of described PCIe load comprises first ac coupling capacitor and second ac coupling capacitor, described first ac coupling capacitor is between described first pull down resistor and described driving arrangement receiving port, and described second ac coupling capacitor is between described second pull down resistor and described driving arrangement receiving port.
7, as circuit connection state detection method as described in each in the claim 4 to 6, it is characterized in that described transmitter determines that by detecting described pulse waveform charging rate driving arrangement receiving port connection status is specially: by determine the connection status of driving arrangement receiving port and transmitter in the time of detected pulse voltage value of Preset Time or arrival predetermined pulse magnitude of voltage.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007101059680A CN100516912C (en) | 2007-06-04 | 2007-06-04 | Circuit connection state detection system and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007101059680A CN100516912C (en) | 2007-06-04 | 2007-06-04 | Circuit connection state detection system and method |
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| Publication Number | Publication Date |
|---|---|
| CN101055304A CN101055304A (en) | 2007-10-17 |
| CN100516912C true CN100516912C (en) | 2009-07-22 |
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| CNB2007101059680A Expired - Fee Related CN100516912C (en) | 2007-06-04 | 2007-06-04 | Circuit connection state detection system and method |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103797732B (en) * | 2013-11-05 | 2016-01-20 | 华为技术有限公司 | Communication means, peripheral component interconnection PCIE chip and PCIE device |
| CN104102606A (en) * | 2014-07-16 | 2014-10-15 | 山东超越数控电子有限公司 | Method for transmitting PCI (peripheral component interconnect)-EXPRESS signals over long distances |
| CN105510804B (en) * | 2015-12-31 | 2018-03-20 | 珠海市一微半导体有限公司 | A kind of signal loop detection circuit and method |
| JP6744605B2 (en) * | 2016-07-29 | 2020-08-19 | ザインエレクトロニクス株式会社 | Transmission device and transmission/reception system |
| CN106411136A (en) * | 2016-08-25 | 2017-02-15 | 浙江大学 | High-voltage capacitance coupling based control chip of isolated type power converter |
| CN106597198A (en) * | 2016-12-07 | 2017-04-26 | 英业达科技有限公司 | Detection device, method and electronic device |
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Address after: 310052 Binjiang District Changhe Road, Zhejiang, China, No. 466, No. Patentee after: NEW H3C TECHNOLOGIES Co.,Ltd. Address before: 310053 Hangzhou hi tech Industrial Development Zone, Zhejiang province science and Technology Industrial Park, No. 310 and No. six road, HUAWEI, Hangzhou production base Patentee before: HANGZHOU H3C TECHNOLOGIES Co.,Ltd. |
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