CN108933147A - Method for manufacturing active element substrate - Google Patents

Abstract

A method for manufacturing an active element substrate comprises the following steps: forming a source electrode on a display area of a substrate; forming an auxiliary insulating layer on the source electrode; forming an opening in the auxiliary insulating layer to expose the source electrode; forming a semiconductor layer on the auxiliary insulating layer, wherein the semiconductor layer is electrically connected with the source electrode through the opening; forming a gate insulating layer on the opening, the semiconductor layer, and the auxiliary insulating layer; and forming a gate electrode on the opening, the semiconductor layer, and the gate insulating layer.

Description

Active device substrate manufacturing method

technical field

The present invention relates to a manufacturing method of an active component substrate, and in particular to a manufacturing method of an active component substrate in which a semiconductor layer is formed on an auxiliary insulating layer.

Background technique

At present, vertical thin film transistors (vertical thin film transistors, vertical TFTs) are gradually being valued by many companies. Vertical thin film transistors have higher carrier mobility and can be applied to devices with higher frequency and lower operating bias.

However, in the manufacturing process of the vertical thin film transistor, the active layer needs to cover multiple film layers at the same time, so multiple coating processes and patterning processes are required, and multiple masks need to be used. As a result, not only the complexity of the process is high, but also the manufacturing cost is difficult to reduce. In addition, the edges of the multiple film layers formed by the multi-pass coating process will be stepped, so that when the active layer covers the stepped structure, the active layer is likely to have poor film quality due to uneven edges, which will affect the vertical thin film transistor. electron transport within. Therefore, there is an urgent need for a method that can solve the aforementioned problems.

Contents of the invention

An embodiment of the present invention provides a method for manufacturing an active device substrate, which can increase the start-up current of the active device.

A method for manufacturing an active device substrate according to an embodiment of the present invention includes: forming a source on a display area of the substrate; forming an auxiliary insulating layer on the source; forming an opening in the auxiliary insulating layer to expose the source; Forming a semiconductor layer on the auxiliary insulating layer, the semiconductor layer is electrically connected to the source through the opening; forming a gate insulating layer on the opening, the semiconductor layer and the auxiliary insulating layer; and forming a gate on the opening, the semiconductor layer and the gate insulating layer pole.

One of the objectives of the present invention is to reduce the processing difficulty of the active device substrate.

One of the objectives of the present invention is to increase the start-up current of the active device.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Description of drawings

FIG. 1 is a schematic top view of an active device substrate according to an embodiment of the present invention.

2A to 2M are schematic partial cross-sectional views of a method for manufacturing an active device substrate according to an embodiment of the present invention.

3A-3I are schematic partial top views of a method for manufacturing an active device substrate according to an embodiment of the present invention.

4A-4K are schematic partial cross-sectional views of a method for manufacturing an active device substrate according to an embodiment of the present invention.

5A to 5I are schematic partial top views of a method for manufacturing an active device substrate according to an embodiment of the present invention.

6A to 6H are schematic partial cross-sectional views of a method for manufacturing an active device substrate according to an embodiment of the present invention.

7A to 7H are schematic partial top views of a method for manufacturing an active device substrate according to an embodiment of the present invention.

FIG. 8 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention.

List of reference signs

10, 20, 30: active component substrate

100: Substrate

102: Fan-out line

104: flexible circuit board

110: Auxiliary insulating layer

120, 210, 330: the first patterned photoresist layer

130, 130', 220, 340: semiconductor layer

140, 230, 350: second patterned photoresist layer

150: interlayer insulating layer

310, 320, 320’, 320”: ohmic contact layer

360: third patterned photoresist layer

370: Through hole

400: conduction structure

AA', BB', CC': lines

AR: display area

BR: Surrounding area

C1, C2, C3: contact window

CH: semiconductor channel

COM: common electrode

D: Drain

DL: data line

G: grid

GI: Gate insulating layer

L: Length

M1: first wire layer

M2: Second wire layer

N: normal direction

OP, OP1: opening

PE, PE1, PE2: pixel electrodes

PEM: pixel electrode material layer

PEM1: Part I

PEM2: Part Two

PEM3: Part Three

S: source

SL: scan line

SLI: Slit

SM: layer of semiconductor material

T, T’, T”: active components

W: horizontal distance

Detailed ways

FIG. 1 is a schematic top view of an active device substrate according to an embodiment of the present invention. 2A to 2M are schematic partial cross-sectional views of a method for manufacturing an active device substrate according to an embodiment of the present invention. 3A-3I are schematic partial top views of a method for manufacturing an active device substrate according to an embodiment of the present invention. It must be noted here that Figure 2C to Figure 2I are schematic cross-sectional views along the line AA' of Figure 3A to Figure 3G respectively; Figure 2K is a schematic cross-sectional view along the line AA' of Figure 3H; Figure 2M is a schematic cross-sectional view along the line AA' of Figure 3I; A schematic cross-sectional view of AA', wherein the same or similar symbols (reference numerals) are used to denote the same or similar elements, and descriptions of the same technical contents are omitted. For the convenience of illustration, the drawing of the insulating layer is omitted in FIGS. 3A-3I , and the position of the opening OP is indicated by a dotted line.

Please refer to FIG. 1 , the substrate 100 of the active device substrate 10 includes a display area AR and a peripheral area BR. The peripheral area BR is located on one side of the display area AR, or the peripheral area BR surrounds the display area AR. In other words, the peripheral area BR can be located on one side of the display area AR, and can be adjusted according to different demands. For example, when applied to a rectangular display area, the peripheral area BR surrounds the display area AR or can be located on one side, two sides or three sides of the display area AR; when applied to a non-rectangular display area or a circular display area , the peripheral area BR may be adjacent to the display area AR, for example, adjacent to a part of or the entire circumference of the display area AR. In this embodiment, the active device substrate 10 further includes a fan-out line 102 and a flexible circuit board 104 . The fan-out line 102 and the flexible circuit board 104 are located on the peripheral area BR, and the fan-out line 102 extends from the peripheral area BR into the display area AR. For example, the fan-out line 102 is electrically connected to the flexible circuit board 104 on the peripheral area BR and the active components on the display area AR.

FIGS. 2A-2I and FIGS. 3A-3I are, for example, partially enlarged schematic diagrams of a manufacturing method of the display region AR of the active device substrate 10 .

Referring to FIG. 2A and FIG. 3A , the source S and the data line DL are formed on the display area AR of the substrate 100 , and the data line DL is electrically connected to the source S. Referring to FIG.

Next, referring to FIG. 2B , an auxiliary insulating layer 110 is formed on the source S. In this embodiment, the material of the auxiliary insulating layer 110 may include siloxane, polyimide, silicon nitride, other suitable materials, or A stacked layer of at least two of the above materials. In some embodiments, the auxiliary insulating layer 110 is also formed on the data line DL.

Please refer to FIG. 2C and FIG. 3A at the same time, an opening OP is formed in the auxiliary insulating layer 110 to expose the source S. Referring to FIG.

Referring to FIG. 2D and FIG. 3B , a semiconductor material layer SM is formed on the upper surface of the auxiliary insulating layer 110 . A layer of semiconductor material SM covers the opening OP. The material of the semiconductor material layer SM includes, for example, indium gallium zinc oxide, indium zinc tin oxide or indium gallium tin oxide.

Referring to FIG. 2E and FIG. 3C, a first patterned photoresist layer 120 is formed on the semiconductor material layer SM and the opening OP. The method for forming the first patterned photoresist layer 120 includes, for example, coating a photoresist material on the semiconductor material layer SM and in the opening OP, and then performing a lithography process on the photoresist material.

2F and 3D, using the first patterned photoresist layer 120 as a mask, part of the semiconductor material layer SM is removed to form a semiconductor layer 130, the semiconductor layer 130 is electrically connected to the source S through the opening OP , the semiconductor layer 130 and the first patterned photoresist layer 120 expose part of the upper surface of the auxiliary insulating layer 110 . In this embodiment, the material of the semiconductor layer 130 includes, for example, InGaZnO, IZnTO or InGaTnO.

Referring to FIG. 2G and FIG. 3E at the same time, a second patterned photoresist layer 140 is formed. For example, an ashing process is performed on the first patterned photoresist layer 120 to remove the portion of the first patterned photoresist layer 120 that is not (not) located on the opening OP to form a second patterned photoresist layer. Adhesive layer 140. In this embodiment, the second patterned photoresist layer 140 is located in the opening OP, and substantially exposes the portion of the semiconductor layer 130 not located in the opening OP. Wherein, the step of performing the ashing process includes, for example, applying carbon tetrafluoride or oxygen, but the present invention is not limited thereto.

Please refer to FIG. 2H and FIG. 3F at the same time, conducting a conductorization process on a part of the semiconductor layer 130 to define the semiconductor channel CH, the drain D and the pixel electrode PE, wherein the semiconductor channel CH is a part of the semiconductor layer 130'. The conductivity of the drain D and the pixel electrode PE is higher than that of the semiconductor channel CH. The drain D is connected to the semiconductor channel CH, and the pixel electrode PE is electrically connected to the drain D. For example, the pixel electrode PE is in contact with the drain D but not in contact with the semiconductor channel CH.

The step of performing the conductorization process includes, for example, using the second patterned photoresist layer 140 as a mask to apply hydrogen gas to the semiconductor layer 130 , but the invention is not limited thereto. In this embodiment, by using the second patterned photoresist layer 140 as a mask, the edge position of the semiconductor channel CH can be precisely controlled during the conductorization process. In this embodiment, part of the semiconductor channel CH substantially surrounds the sidewall of the opening OP. In this embodiment, the length L of the semiconductor channel CH is about the length of the sidewall of the opening OP, and the length L of the semiconductor channel CH refers to the effective length of the semiconductor channel CH. Through the setting of the auxiliary insulating layer 110, the length L can be accurately controlled. In this embodiment, the length L of the semiconductor channel CH is about 0.5 microns to 4 microns, preferably 1 microns to 2 microns. In this embodiment, the pixel electrode PE is not located in the opening OP, and viewed along the normal direction N of the substrate 100, a part of the drain D is located between the semiconductor channel CH and the pixel electrode PE, and the drain D is, for example, ring-shaped. And located on the upper surface of the auxiliary insulating layer 110 .

Referring to FIG. 2I and FIG. 3G at the same time, the second patterned photoresist layer 140 is removed to expose the semiconductor layer 130' in the opening OP. A method for removing the second patterned photoresist layer 140 is, for example, performing a photoresist stripping process or an ashing process, but the invention is not limited thereto. If viewed along the normal direction N of the substrate 100, the pattern of the semiconductor layer 130' in the opening OP is, for example, circular or elliptical, but the present invention is not limited thereto.

Referring to FIG. 2J , a gate insulating layer GI is formed on the opening OP, the semiconductor layer 130 ′, the drain D, the pixel electrode PE and the auxiliary insulating layer 110 . The gate insulating layer GI covers the drain D and the pixel electrode PE.

Referring to FIG. 2K and FIG. 3H at the same time, the gate G is formed on the opening OP, the semiconductor layer 130' and the gate insulating layer GI. In this embodiment, the gate G overlaps the drain D and the source S respectively along the normal direction N of the substrate 100 . In some embodiments, the gate G and the scan line SL are formed in the same patterning process. The gate G is electrically connected to the scan line SL. At this time, the fabrication of the active device T has been completed, and the active device T is a top-gate thin film transistor.

Referring to FIG. 2L , an interlayer insulating layer 150 is formed on the gate G. Referring to FIG. In some embodiments, the insulating layer 150 is also formed on the scan line SL.

Referring to FIG. 2M and FIG. 3I , the common electrode COM is formed on the interlayer insulating layer 150 , so far, the fabrication of the active device substrate 10 has been substantially completed. In this embodiment, the common electrode COM overlaps the pixel electrode PE and part of the drain D and the gate G along the normal direction N of the substrate 100 . In this embodiment, the common electrode COM includes, for example, a plurality of slits SLI. The slit SLI of the common electrode COM overlaps the pixel electrode PE in the normal direction N along the substrate 100. In a preferred embodiment, the common electrode has an opening OP1 to expose the opening OP and part of the gate insulating layer GI. The opening OP1 of the common electrode COM overlaps the gate G in the normal direction N along the substrate 100 . Furthermore, the common electrode COM passes through the opening OP1 to reduce the coupling capacitance between the common electrode COM and the gate G.

In this embodiment, by using the first patterned photoresist layer 120 and the second patterned photoresist layer 140 as masks, the semiconductor layer 130, the semiconductor channel CH, the drain D, the pixel electrode PE, and the gate G can be more accurately set at the position of the process design, and can save the number of masks required for the process, and in the manufacturing process of the active device substrate 10, the length L of the semiconductor channel CH can be controlled by setting the auxiliary insulating layer 110 The starting current of the active element T is increased, and the area of the active element T is further reduced to increase the aperture ratio of the display area AR.

4A-4K are schematic partial cross-sectional views of a method for manufacturing an active device substrate according to an embodiment of the present invention. 5A to 5I are schematic partial top views of a method for manufacturing an active device substrate according to an embodiment of the present invention. It must be noted here that FIGS. 4A to 4G are schematic cross-sectional views along the line BB' of FIGS. 5A to 5G respectively; FIG. 4I is a schematic cross-sectional view along the line BB' of FIG. 5H; A schematic cross-sectional view of BB', in which the same or similar symbols (reference numerals) are used to denote the same or similar components, and descriptions of the same technical contents are omitted. For convenience of description, the drawing of the insulating layer is omitted in FIGS. 5A-5I , and the position of the opening OP is indicated by a dotted line.

FIGS. 4A-4K and FIGS. 5A-5I are partially enlarged schematic diagrams of, for example, a manufacturing method of the display region AR of the active device substrate 20 . It must be noted here that the embodiments in FIGS. 4A to 4K and FIGS. 5A to 5I follow the component numbers and parts of the embodiments in FIGS. 2A to 2I and FIGS. The same or similar elements, and the description of the same technical content is omitted. For the description of omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

4A and FIG. 5A are for example a continuation of the steps in FIG. 2D and FIG. 3B. Please refer to FIG. 4A and FIG. A part of the semiconductor material layer SM outside the opening OP is exposed, and another part of the semiconductor material layer SM outside the opening OP is exposed. For example, viewed along the normal direction N of the substrate 100 , the first patterned photoresist layer 210 is, for example, circular. It can be understood that the first patterned photoresist layer 210 can be patterned into different shapes according to the requirement of process design, but the present invention is not limited thereto. In this embodiment, the material of the semiconductor material layer SM includes, for example, amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor materials, oxide semiconductor materials (for example: indium zinc oxide, indium germanium zinc oxide, or other suitable materials, or combinations of the above), or other suitable materials, or containing dopant in the above materials, or the combination of the above.

Referring to FIG. 4B and FIG. 5B , using the first patterned photoresist layer 210 as a mask, part of the semiconductor material layer SM is removed to form a semiconductor layer 220 . The semiconductor layer 220 is electrically connected to the source S through the opening OP.

Referring to FIG. 4C and FIG. 5C , the first patterned photoresist layer 210 is removed.

Referring to FIG. 4D and FIG. 5D , a pixel electrode material layer PEM is formed on the opening OP, the semiconductor layer 220 and the auxiliary insulating layer 110 , and is electrically connected to the semiconductor layer 220 .

Referring to FIG. 4E and FIG. 5E , a second patterned photoresist layer 230 is formed. In this embodiment, the second patterned photoresist layer 230 is located on the semiconductor layer 220 , the pixel electrode material layer PEM and the auxiliary insulating layer 110 . In this embodiment, viewed along the normal direction N of the substrate 100, the second patterned photoresist layer 230 is separated from the opening OP by a horizontal distance W, wherein the horizontal distance W is, for example, greater than 0 micrometers and less than or equal to 3 micrometers , so that the second patterned photoresist layer 230 does not overlap the opening OP, but not limited thereto.

Please refer to FIG. 4F and FIG. 5F , using the second patterned photoresist layer 230 as a mask, part of the pixel electrode material layer PEM is removed to simultaneously form the drain electrode D and the pixel electrode PE1, wherein the drain electrode D and the semiconductor layer 220, the drain D is electrically connected to the pixel electrode PE1, for example, the drain D is directly connected to the pixel electrode PE1 and has the same material.

Referring to FIG. 4G and FIG. 5G , the second patterned photoresist layer 230 is removed to expose the drain electrode D and the pixel electrode PE1 . The method for removing the second patterned photoresist layer 230 is, for example, performing a photoresist stripping process or an ashing process, but the invention is not limited thereto.

Referring to FIG. 4H , a gate insulating layer GI is formed on the opening OP, the semiconductor layer 220 and the auxiliary insulating layer 110 . The gate insulating layer GI covers the pixel electrode PE1.

Referring to FIG. 4I and FIG. 5H , the gate G is formed on the opening OP, the semiconductor layer 220 and the gate insulating layer GI. In some embodiments, the gate G and the scan line SL are formed in the same patterning process. The gate G is electrically connected to the scan line SL. At this time, the fabrication of the active element T' has been completed, and the active element T' is a top-gate thin film transistor.

Referring to FIG. 4J , an interlayer insulating layer 150 is formed on the gate G. Referring to FIG. In some embodiments, the insulating interlayer 150 is also formed on the scan line SL.

Referring to FIG. 4K and FIG. 5I , the common electrode COM is formed on the interlayer insulating layer 150 , so far, the manufacturing process of the active device substrate 20 has been substantially completed. In this embodiment, the common electrode COM overlaps the pixel electrode PE1 along the normal direction N of the substrate 100 . The main difference between the active device substrate 20 and the active device substrate 10 is that the pixel electrode PE1 of the active device substrate 20 is formed by patterning the pixel electrode material layer PEM, and covers part of the semiconductor layer 220 .

In this embodiment, the start-up current of the active device can be increased by controlling the length L of the semiconductor channel CH through the arrangement of the auxiliary insulating layer 110 and the horizontal distance W, and the area of the active device can be further reduced to increase the aperture ratio of the display region AR, thereby obtaining a higher A good active device substrate 20.

6A to 6H are schematic partial cross-sectional views of a method for manufacturing an active device substrate according to an embodiment of the present invention. 7A to 7H are schematic partial top views of a method for manufacturing an active device substrate according to an embodiment of the present invention. It must be noted here that FIGS. 6A to 6H are schematic cross-sectional views along line CC' of FIGS. 7A to 7H , wherein the same or similar symbols are used to indicate the same or similar components, and the same technical contents are omitted. illustrate. For the convenience of illustration, the drawing of the insulating layer is omitted in FIGS. 7A-7H , and the position of the opening OP is indicated by a dotted line.

FIGS. 6A-6H and FIGS. 7A-7H are, for example, partially enlarged schematic diagrams of a manufacturing method of the display region AR of the active device substrate 30 . It must be noted here that the embodiments of FIGS. 6A to 6H and FIGS. 7A to 7H continue to use the component numbers and parts of the embodiments of FIGS. 4A to 4K and FIGS. ) to indicate the same or similar elements, and the description of the same technical content is omitted. For the description of omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

Referring to FIG. 6A and FIG. 7A , in this embodiment, the source S further has an ohmic contact layer 310 , and the semiconductor material layer SM further has an ohmic contact layer 320 . For example, before forming the first patterned photoresist layer 330 , an ion doping process is performed on the semiconductor material layer SM to form the ohmic contact layer 320 on the surface of the semiconductor material layer SM.

Referring to FIG. 6B and FIG. 7B, using the first patterned photoresist layer 330 as a mask, part of the semiconductor material layer SM and the ohmic contact layer 320 are removed to form the semiconductor layer 340 and the ohmic contact layer 320'. The semiconductor layer 340 is electrically connected to the source S through the opening OP. In this embodiment, the material of the semiconductor layer 340 includes, for example, amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor materials, oxide semiconductor materials (for example: indium zinc oxide, indium germanium zinc oxide, or is other suitable materials, or the above-mentioned combination), or other suitable materials, or contains dopant in the above-mentioned materials, or the above-mentioned combination.

Referring to FIG. 6C and FIG. 7C , an ashing process is performed on the first patterned photoresist layer 330 to form a second patterned photoresist layer 350 . In this embodiment, the second patterned photoresist layer 350 is located in the opening OP, and substantially exposes a part of the semiconductor layer 340 and a part of the ohmic contact layer 320' not located in the opening OP.

Referring to FIG. 6D and FIG. 7D , a pixel electrode material layer PEM is formed on the semiconductor layer 340 , the second patterned photoresist layer 350 and the auxiliary insulating layer 110 . A third patterned photoresist layer 360 is formed on the semiconductor layer 340 , the pixel electrode material layer PEM and the auxiliary insulating layer 110 , and exposes the first portion PEM1 of the pixel electrode material layer PEM. The second portion PEM2 of the pixel electrode material layer PEM is located between the third patterned photoresist layer 360 and the second patterned photoresist layer 350 . The third portion PEM3 of the pixel electrode material layer PEM is located between the first portion PEM1 and the second portion PEM2. In other words, in the normal direction N along the substrate 100 , the first portion PEM1 of the pixel electrode material layer PEM does not overlap the third patterned photoresist layer 360 . In this embodiment, the third patterned photoresist layer 360 has a through hole 370, and overlaps the opening OP along the normal direction N of the substrate 100, so as to expose part of the first part PEM1 of the pixel electrode material layer PEM. .

Please refer to FIG. 6E and FIG. 7E, using the third patterned photoresist layer 360 as a mask, remove the first part PEM1 of the pixel electrode material layer PEM to expose a part of the second patterned photoresist layer 350 and the auxiliary Part of the insulating layer 110.

Referring to FIG. 6F and FIG. 7F , the second patterned photoresist layer 350 and the third patterned photoresist layer 360 are removed to form the pixel electrode PE2 . In this embodiment, the second part PEM2 of the pixel electrode material layer PEM will be removed together with the photoresist stripping process of the second patterned photoresist layer 350 and the third patterned photoresist layer 360, The pixel electrode PE2 is approximately equal to the third portion PEM3 of the pixel electrode material layer PEM. In this embodiment, a part of the pixel electrode PE2 is used as the drain D, and the material of the pixel electrode PE2 is, for example, metal or transparent metal oxide, but not limited thereto. In this embodiment, please refer to FIG. 6E and FIG. 6F at the same time. The width of the through hole 370 is smaller than the width of the opening OP, so as to facilitate the removal of the second patterned photoresist layer 350. The boundary of the electrode PE2 is disposed on the edge of the opening OP. Next, use the auxiliary insulating layer 110 and the pixel electrode PE2 as a mask, and remove the unmasked ohmic contact layer 320 ′ by, for example, an etching process, leaving the ohmic contact layer 320 ″. The semiconductor channel CH is, for example, a semiconductor layer 340 covering the opening Part of the OP sidewall.

Referring to FIG. 6G and FIG. 7G , a gate insulating layer GI is formed on the opening OP, the semiconductor layer 340 and the auxiliary insulating layer 110 . The gate insulating layer GI covers the pixel electrode PE2. The gate G is formed on the opening OP, the semiconductor layer 340 and the gate insulating layer GI. In some embodiments, the gate G and the scan line SL are formed in the same patterning process. The gate G is electrically connected to the scan line SL. At this time, the fabrication of the active element T" has been completed, and the active element T" is a top-gate thin film transistor.

Referring to FIG. 6H and FIG. 7H , an interlayer insulating layer 150 is formed on the gate G. Referring to FIG. In some embodiments, the insulating interlayer 150 is also formed on the scan line SL. The common electrode COM is formed on the interlayer insulating layer 150 , so far, the manufacturing process of the active device substrate 30 has been substantially completed. In this embodiment, the common electrode COM overlaps the pixel electrode PE2 along the normal direction N of the substrate 100 .

The main difference between the active element substrate 30 and the active element substrate 20 is that the pixel electrode PE2 of the active element substrate 30 is patterned and removed through the third patterned photoresist layer 360 to remove the first part PEM1 of the pixel electrode material layer PEM, and by removing The second patterned photoresist layer 350 and the third patterned photoresist layer 360 are formed by removing the second part PEM2 of the pixel electrode material layer PEM at the same time, and part of the pixel electrode PE2 covers the semiconductor layer 340 Ohmic contact layer 320".

In this embodiment, through the first patterned photoresist layer 330, the second patterned photoresist layer 350 and the third patterned photoresist layer 360, the semiconductor layer 340, the semiconductor channel CH, and the pixel electrode PE2 And the gate G can be more accurately arranged on the position of the process design, and the number of masks required by the process can be saved, and in the manufacturing process of the active device substrate 30, the setting of the auxiliary insulating layer 110 controls the semiconductor channel CH The length L is used to increase the start-up current of the active device, and the area of the active device is further reduced to increase the aperture ratio of the display region AR, so as to obtain a better active device substrate 30 .

FIG. 8 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 8 follows the component numbers and part of the content of the embodiment of FIG. 2A to FIG. A description of the technical content. For the description of omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

Referring to FIG. 8 , a first wiring layer M1 is formed on the peripheral region BR of the substrate 100 . In this embodiment, the first wire layer M1 and the source S can be formed by patterning the same film layer. In other alternative embodiments, the first wiring layer M1 and the source S may be formed by patterning different film layers, but the present invention is not limited thereto.

A second wire layer M2 is formed on the gate insulating layer GI. The second wire layer M2 is located on the peripheral region BR of the substrate 100 . In this embodiment, the second wire layer M2 and the gate G can be formed by patterning the same film layer. In other alternative embodiments, the second wire layer M2 and the gate G may be formed by patterning different film layers, but the present invention is not limited thereto.

The conduction structure 400 is formed in the contact window C1 of the gate insulating layer GI, and the contact window C1 overlaps the first wiring layer M1 and does not overlap the second wiring layer M2. The conductive structure 400 is electrically connected to the first wire layer M1 and the second wire layer M2.

In this embodiment, the interlayer insulating layer 150 is formed on the second wire layer M2, the interlayer insulating layer 150 has a connection window C2 and a connection window C3, and the connection window C2 overlaps the connection window C1 to expose the first A wire layer M1, the connection window C3 exposes the second wire layer M2. The conduction structure 400 is also formed in the connection window C2 and the connection window C3 to electrically connect the first wire layer M1 and the second wire layer M2. The first wire layer M1 and the second wire layer M2 are stacked to form the fan-out line 102 , thereby reducing the impedance of the fan-out line 102 .

In this embodiment, the conduction structure 400 and the common electrode COM can be formed by patterning the same film layer. In other alternative embodiments, the conduction structure 400 and the common electrode COM may be formed by patterning different film layers, but the present invention is not limited thereto. In addition, the above-mentioned fan-out wire 102 is illustrated by taking the double-layer wire structure as an example, but the present invention is not limited thereto. In other embodiments, the above-mentioned fan-out wire 102 may also be a single-layer wire structure.

To sum up, the active component substrate of the present invention forms openings in the auxiliary insulating layer, so that the semiconductor layer, the gate insulating layer, and the gate can be more accurately arranged on the positions of the process design, and can save process requirements. The number of masks, and through the setting of the auxiliary insulating layer 110 to control the length L of the semiconductor channel CH to increase the start-up current of the active device, further reduce the area of the active device to increase the aperture ratio of the display area AR, and obtain an active device with a better aperture ratio. component substrate.

Although the present invention has been disclosed above with embodiments, it is not intended to limit the present invention, and any ordinary skilled person in the technical field should be able to make some changes without departing from the spirit and scope of the present invention and retouching, so the scope of protection of the present invention should be defined by the appended claims.

Claims (20)

1. A method for manufacturing an active component substrate, comprising: forming a source electrode on a display area of a substrate; forming an auxiliary insulating layer on the source; forming an opening in the auxiliary insulating layer to expose the source; forming a semiconductor layer on the auxiliary insulating layer, the semiconductor layer is electrically connected to the source through the opening; forming a gate insulating layer on the opening, the semiconductor layer, and the auxiliary insulating layer; and A gate is formed on the opening, the semiconductor layer and the gate insulating layer. 2. The manufacturing method according to claim 1, further comprising: performing a conductorization process on a portion of the semiconductor layer to define a semiconductor channel, a drain and a pixel electrode, wherein a portion of the semiconductor channel substantially surrounds the sidewall of the opening such that the length of the semiconductor channel is about 0.5 microns to 3 microns, and the pixel electrode is not located in the opening. 3. The manufacturing method according to claim 2, wherein the material of the semiconductor layer comprises indium gallium zinc oxide, indium zinc tin oxide or indium gallium tin oxide, and viewed along the normal direction of the substrate, the drain A portion of the pole is located between the semiconductor channel and the pixel electrode. 4. The manufacturing method according to claim 2, wherein the step of forming the semiconductor layer on the auxiliary insulating layer comprises: forming a semiconductor material layer to cover the opening and the upper surface of the auxiliary insulating layer; forming a first patterned photoresist layer on the semiconductor material layer and the opening; and Using the first patterned photoresist layer as a mask, part of the semiconductor material layer is removed to form the semiconductor layer. 5. The manufacturing method according to claim 4, wherein before the step of performing the conductorization process on the portion of the semiconductor layer, the method further comprises: performing an ashing process on the first patterned photoresist layer to form a second patterned photoresist layer, wherein the second patterned photoresist layer is located in the opening and substantially exposes within the portion of the semiconductor layer. 6. The manufacturing method as claimed in claim 5, wherein the step of performing the ashing process comprises applying carbon tetrafluoride or oxygen. 7. The manufacturing method according to claim 5, wherein the step of carrying out the conductorization process to the part of the semiconductor layer comprises: Using the second patterned photoresist layer as a mask, hydrogen gas is applied to the semiconductor layer. 8. The manufacturing method according to claim 7, wherein after the step of performing the conductorization process on the portion of the semiconductor layer and before the step of forming the gate insulating layer, the method further comprises removing the second Pattern the photoresist layer. 9. The manufacturing method according to claim 8, wherein after the step of forming the gate, the method further comprises: forming an interlayer insulating layer on the gate; and A common electrode is formed on the interlayer insulating layer, and the common electrode overlaps the pixel electrode. 10. The manufacturing method according to claim 1, wherein after the step of forming the semiconductor layer, the method further comprises: A pixel electrode material layer is formed in the opening, on the semiconductor layer and the auxiliary insulating layer, and the pixel electrode material layer is electrically connected to the semiconductor layer; A second patterned photoresist layer is formed on the semiconductor layer, the pixel electrode material layer and the auxiliary insulating layer, wherein the second patterned photoresist layer is separated from the opening by a horizontal distance, and the horizontal distance is greater than 0 micron and less than or equal to 3 microns so that the second patterned photoresist layer does not overlap the opening; Using the second patterned photoresist layer as a mask, removing part of the pixel electrode material layer to form a pixel electrode; and The second patterned photoresist layer is removed. 11. The manufacturing method according to claim 10, wherein the material of the semiconductor layer comprises amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor material or oxide semiconductor material. 12. The manufacturing method according to claim 11, wherein after the step of forming the gate, the method further comprises: forming an interlayer insulating layer on the gate; and A common electrode is formed on the interlayer insulating layer, and the common electrode overlaps the pixel electrode. 13. The manufacturing method according to claim 1, wherein the step of forming the semiconductor layer on the auxiliary insulating layer comprises: forming a semiconductor material layer in the opening and on the auxiliary insulating layer; forming a first patterned photoresist layer on the upper surface of the semiconductor material layer and in the opening; and Using the first patterned photoresist layer as a mask, part of the semiconductor material layer is removed to form the semiconductor layer. 14. The manufacturing method according to claim 13, wherein after the step of forming the semiconductor layer on the auxiliary insulating layer and before the step of forming the gate insulating layer, the method further comprises: performing an ashing process on the first patterned photoresist layer to form a second patterned photoresist layer, wherein the second patterned photoresist layer is located in the opening and substantially exposes part of the semiconducting layer within; forming a pixel electrode material layer on the semiconductor layer, the second patterned photoresist layer and the auxiliary insulating layer; A third patterned photoresist layer is formed on the semiconductor layer, the pixel electrode material layer and the auxiliary insulating layer, wherein the third patterned photoresist layer has a through hole overlapping the opening, and the width of the through hole is is less than the width of the opening; using the third patterned photoresist layer as a mask, removing a first portion of the pixel electrode material layer; and A second portion of the second patterned photoresist layer, the third patterned photoresist layer and the pixel electrode material layer is removed to form a pixel electrode. 15. The manufacturing method according to claim 14, wherein before the step of forming the first patterned photoresist layer, the method further comprises performing an ion doping process on the semiconductor material layer to form An ohmic contact layer is formed on the surface. 16. The manufacturing method according to claim 15, wherein after removing the second patterned photoresist layer, the third patterned photoresist layer and the second part of the pixel electrode material layer, the method It also includes removing the part of the ohmic contact layer not covered by the pixel electrode to form a semiconductor channel. 17. The manufacturing method according to claim 16, wherein the material of the semiconductor layer comprises amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor material or oxide semiconductor material. 18. The manufacturing method according to claim 17, wherein after the step of forming the gate, the method further comprises: forming an interlayer insulating layer on the gate; and A common electrode is formed on the interlayer insulating layer, and the common electrode overlaps the pixel electrode. 19. The manufacturing method of claim 1, further comprising: forming a first wiring layer on a peripheral area of the substrate, wherein the peripheral area is located at least one side of the display area, wherein the first wiring layer and the source are formed by patterning the same film layer; and forming a second wiring layer on the gate insulating layer, the second wiring layer is located on the peripheral region of the substrate, wherein the second wiring layer and the gate are formed by patterning the same film layer; and A conduction structure is formed, the conduction structure is electrically connected to the first wiring layer and the second wiring layer through a contact window of the gate insulating layer, and the contact window does not overlap the second wiring layer. 20. The manufacturing method according to claim 19, wherein after the step of forming the gate, the method further comprises: forming an interlayer insulating layer on the gate; and A common electrode is formed on the interlayer insulating layer, and the common electrode overlaps the pixel electrode, wherein the conduction structure and the common electrode are formed by patterning the same film layer.