CN108667453B - A low-power driver circuit with adjustable slew rate - Google Patents
A low-power driver circuit with adjustable slew rate Download PDFInfo
- Publication number
- CN108667453B CN108667453B CN201810320688.XA CN201810320688A CN108667453B CN 108667453 B CN108667453 B CN 108667453B CN 201810320688 A CN201810320688 A CN 201810320688A CN 108667453 B CN108667453 B CN 108667453B
- Authority
- CN
- China
- Prior art keywords
- signal
- circuit
- rising edge
- falling edge
- edge pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000000630 rising effect Effects 0.000 claims abstract description 74
- 239000003990 capacitor Substances 0.000 claims abstract description 18
- 238000011084 recovery Methods 0.000 claims description 15
- 230000002596 correlated effect Effects 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 7
- 229910044991 metal oxide Inorganic materials 0.000 claims description 6
- 150000004706 metal oxides Chemical class 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Electronic Switches (AREA)
- Pulse Circuits (AREA)
Abstract
本发明公开了一种压摆率可调的低功耗驱动器电路，包括延迟控制模块、边沿脉冲发生器模块和驱动器模块，所述驱动器模块包括第一驱动器单元和第二驱动器单元；其中，输入信号连接到所述延迟控制模块并输出DSR信号，所述DSR信号和反向的输入信号一起输入到所述边沿脉冲发生器模块中，经逻辑处理后产生上升沿脉冲信号和下降沿脉冲信号，所述反向的输入信号控制第一驱动单元，所述上升沿脉冲信号和下降沿脉冲信号控制所述第二驱动单元。本发明提供的一种压摆率可调的低功耗驱动器电路，在不改变电路直流特性参数的条件下调节输出信号的压摆率，同时通过调节延迟电容的充放电电流大小可以得到比RC低通滤波电路更好的延迟时间控制。
The invention discloses a low power consumption driver circuit with adjustable slew rate, comprising a delay control module, an edge pulse generator module and a driver module, the driver module includes a first driver unit and a second driver unit; wherein, an input The signal is connected to the delay control module and outputs a DSR signal, the DSR signal and the reversed input signal are input into the edge pulse generator module together, and after logical processing, a rising edge pulse signal and a falling edge pulse signal are generated, The inverted input signal controls the first driving unit, and the rising edge pulse signal and the falling edge pulse signal control the second driving unit. The invention provides a low power consumption driver circuit with adjustable slew rate, which can adjust the slew rate of the output signal without changing the DC characteristic parameters of the circuit, and at the same time, by adjusting the charge and discharge current of the delay capacitor, the ratio RC can be obtained. Low-pass filter circuit for better delay time control.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuits, in particular to a low-power-consumption driver circuit with adjustable slew rate.
Background
The MIPI interface protocol is a mobile device interface that transmits signals including two modes: a high speed mode and a low power mode. In the low power consumption mode, in order to reduce the EMI effect and achieve the system time sequence constraint, the slew rate of signals under different loads is specified in detail. If a simple CMOS inverter circuit is adopted as a sending end driving circuit, the slew rate requirement in a protocol can be hardly met under the condition that the load is variable, so that a driver circuit with adjustable slew rate needs to be designed.
There are many ways to adjust the slew rate, however, in order to adjust the slew rate without affecting other performance of the driver, such as equivalent output impedance, a better way to adjust the slew rate alone would be to turn on the slew rate adjustment circuit only during signal level logic transitions. In addition, the turn-on time of the slew rate control circuit needs to be controlled by a delay circuit. The delay circuit constructed by using the conventional RC low-pass filtering unit has large process deviation, and it is difficult to accurately control the switching time of the output signal.
Disclosure of Invention
The invention aims to provide a low-power-consumption driver circuit with adjustable slew rate, which can adjust the slew rate of an output signal under the condition of not changing the direct-current characteristic parameter of the circuit and can obtain better delay time control than an RC low-pass filter circuit by adjusting the charging and discharging current of a delay capacitor.
In order to achieve the purpose, the invention adopts the following technical scheme: a low-power-consumption driver circuit with adjustable slew rate comprises a delay control module, an edge pulse generator module and a driver module, wherein the driver module comprises a first driver unit and a second driver unit; wherein, the input signal is connected to the delay control module and outputs DSR signal, the DSR signal and the inverted input signal are input into the edge pulse generator module together, and after logic processing, a rising edge pulse signal and a falling edge pulse signal are generated, the inverted input signal controls the first driving unit, and the rising edge pulse signal and the falling edge pulse signal control the second driving unit;
the first driver unit comprises a PMOS tube MP0 and an NMOS tube MN0 which are connected in parallel, wherein the grid electrode of the PMOS tube MP0 is connected with an inverted input signal, and the source electrode is connected with a power supply voltage; the grid electrode of the NMOSMN0 tube is connected with an inverted input signal, the source electrode of the NMOSMN0 tube is grounded, and the drain electrodes of the PMOS tube MP0 and the NMOS tube MN0 are connected with an output signal together;
the second driving unit comprises a rising edge circuit and a falling edge circuit which are connected in parallel, the rising edge circuit comprises m rising edge driving branches which are connected in series, each rising edge driving branch comprises a rising edge switch and one of MP1-MPm of a PMOS (P-channel metal oxide semiconductor) tube, the grid electrode of one of MP1-MPm of the PMOS tube is connected with a rising edge pulse signal through the rising edge switch, the source electrode of the one of MP1-MPm of the PMOS tube is connected with a power supply voltage, and the drain electrode of the one of MP1-MPm of the PMOS tube is connected with an output signal; the falling edge circuit comprises m falling edge driving branches which are connected in series, each falling edge driving branch comprises a falling edge switch and one of MN1-MNm of NMOS tubes, the grid electrode of one of MN1-MNm of the NMOS tubes is connected with a falling edge pulse signal through the falling edge switch, the source electrode is grounded, the drain electrode is connected with an output signal, and m is an integer larger than 1.
Further, the source electrode and the drain electrode of the PMOS tube and the NMOS tube can be interchanged.
Furthermore, the delay control module comprises a main circuit, a delay capacitor and a duty cycle recovery circuit, wherein the main circuit comprises n +1 branches connected in parallel, each branch comprises a pull-up path and a pull-down path connected in series, the pull-up path comprises a P-type current source and a P-type switch, the source of the P-type current source is connected with the power voltage, and the drain of the P-type current source is simultaneously connected with one end of the delay capacitor and the duty cycle recovery circuit through the P-type switch; the pull-down path comprises an N-type current source and an N-type switch, wherein the source electrode of the N-type current source is simultaneously connected with the P-type switch, one end of the delay capacitor and the duty cycle recovery circuit through the N-type switch, and the source electrode is simultaneously connected with the other end of the delay capacitor and grounded; the other end of the duty ratio recovery circuit outputs a DSR signal, wherein n is an integer which is greater than or equal to 1; the P-type current source refers to a current source made of a PMOS (P-channel metal oxide semiconductor) tube, and a source electrode of the current source refers to a source electrode of the PMOS tube made of the current source; the N-type current source refers to a current source made of an NMOS tube, and a source electrode of the current source refers to a source electrode made of an NMOS tube of the current source.
Furthermore, the control circuit of the P-type switch is n +1 AND gates, wherein the input signal and the array selection signal are connected to the input end of the AND gate, and the control signal of the P-type switch is obtained after AND operation.
Further, the control circuit of the N-type switch comprises an inverter and N +1 and gates, wherein the input signal is subjected to the inverter to obtain an inverted input signal, the inverted input signal and the array selection signal are connected to the input end of the N-type and gate, and the control signal of the N-type switch is obtained after the operation of the N-type and gate.
Further, the edge pulse generator module comprises a rising edge pulse circuit and a falling edge pulse circuit, wherein the rising edge pulse circuit is used for outputting a rising edge pulse signal, and the falling edge pulse circuit is used for outputting a falling edge pulse signal.
Further, the rising edge pulse circuit comprises a rising edge exclusive-or gate, a rising edge and gate and a rising edge inverter, wherein the input signal and the DSR signal are compared through the rising edge exclusive-or gate to obtain an edge pulse signal, the edge pulse signal and the input signal are jointly input into the rising edge and gate to perform logic operation, then a negative pulse signal positively correlated with the rising edge pulse is obtained, and then the rising edge pulse signal positively correlated with the rising edge delay is obtained through the rising edge inverter.
Further, the falling edge pulse circuit comprises a falling edge inverter, a falling edge AND gate and a falling edge drive; the input signal is processed by a falling edge inverter to obtain an inverted input signal, the inverted input signal and the edge pulse signal are jointly input into a falling edge AND gate to be subjected to logic operation to obtain a positive pulse signal positively correlated with the falling edge delay, and the falling edge pulse signal is obtained by the falling edge primary driver.
Further, the pulse width of the edge pulse signal is a delay between the DSR signal and the input signal.
Further, the potential logic of the output signal is consistent with the input signal.
The invention has the beneficial effects that: the invention adopts a circuit structure that a current source in the delay module charges and discharges a delay capacitor as a slew rate adjusting unit and is matched with a duty ratio recovery circuit, thereby realizing accurate signal output conversion time control. The slew rate of the output signal is adjusted under the condition of not changing the direct current characteristic parameter of the circuit, and meanwhile, better delay time control than an RC low-pass filter circuit can be obtained by adjusting the charging and discharging current of the delay capacitor.
Drawings
Fig. 1 is a structural frame diagram of a low power consumption driver circuit with adjustable slew rate according to the present invention.
Fig. 2 is a schematic structural diagram of a delay control module according to the present invention.
Fig. 3 is a schematic structural diagram of an edge pulse generator module according to the present invention.
FIG. 4 is a timing diagram of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in detail below with reference to the accompanying drawings.
As shown in fig. 1, the low power consumption driver circuit with adjustable slew rate provided by the present invention includes a delay control module 2, an edge pulse generator module 1 and a driver module 3, where the driver module 3 includes a first driver unit and a second driver unit; the input signal is connected to the delay control module 2 and outputs a DSR signal, the DSR signal and the reverse input signal are input into the edge pulse generator module 1 together, logic processing is carried out on the DSR signal and the reverse input signal to generate a rising edge pulse signal SR _ H and a falling edge pulse signal SR _ L, the reverse input signal-D controls the first driving unit, and the rising edge pulse signal SR _ H and the falling edge pulse signal SR _ L control the second driving unit.
As shown in fig. 1, the first driver unit of the present invention includes a PMOS transistor MP0 and an NMOS transistor MN0 connected in parallel, wherein the gate of the PMOS transistor MP0 is connected to the inverted input signal, and the source is connected to the power voltage; the grid electrode of the NMOS transistor MN0 is connected with an inverted input signal, the source electrode is grounded, and the drain electrodes of the PMOS transistor and the NMOS transistor are connected with an output signal together.
As shown in FIG. 1, the second driving unit comprises a rising edge circuit and a falling edge circuit which are connected in parallel, the rising edge circuit comprises m rising edge driving branches which are connected in series, each rising edge driving branch comprises a rising edge switch and a PMOS (P-channel metal oxide semiconductor) tube, as shown in FIG. 1, the rising edge driving branches are connected in series with MP1 and MP2 … … MPm from left to right, wherein the grid of the PMOS tube MP1 is connected with a rising edge pulse signal through the rising edge switch-SR <0>, the source of the PMOS tube MP1 is connected with a power supply voltage, the drain is connected with an output signal, and the connection mode of the MP2 … … MPm is the same as that of the PMOS tube MP 1. As shown in fig. 1, the falling edge circuit includes N falling edge driving branches connected in series, each falling edge driving branch includes a falling edge switch and an NMOS transistor, as shown in fig. 1, the falling edge driving branches are connected in series from left to right with MN1 and MN2 … … MNm, wherein the gate of the NMOS transistor MN1 is connected to a falling edge pulse signal SR _ L through the falling edge switch SR <0>, the source of the NMOS transistor MN1 is grounded, the drain is connected to an output signal, and MN2 … … MNm is connected in the same manner as the NMOS transistor MN 1. Wherein m is an integer greater than 1.
It should be noted that the source and the drain of the PMOS transistor and the NMOS transistor in the present invention can be interchanged.
According to the invention, the opening of the rising edge driving branch is controlled by SR <0> -SR < m-1>, the opening of the falling edge driving branch is controlled by SR <0> SR < m-1>, the more the driving branches are opened, the larger the driving current to the output node during the level conversion period is, the higher the signal slew rate of the output node is. Conversely, the more drive legs that are closed, the lower the signal slew rate at the output node. The two groups of driving circuits are connected in parallel, and signal addition at the output node is realized.
As shown in FIG. 2, the delay control module 2 of the present invention includes a main circuit 24, a delay capacitor C0 and a duty cycle recovery circuit 25, the main circuit 24 includes n +1 branches connected in parallel, each branch includes a pull-up path and a pull-down path connected in series, the pull-up path includes a P-type current source and a P-type switch, as shown in FIG. 2, the pull-up path sequentially includes a P-type current source IP <0>, a P-type current source IP <1> … … P-type current source IP < n >, wherein a source of the P-type current source IP <0> is connected to a power supply voltage, a drain of the P-type current source IP <0> is simultaneously connected to one end of the delay capacitor C0 and the duty cycle recovery circuit 25 through the P-type switch DP <0>, and a connection manner of the P-type current source IP <1> … … P-type current source IP < n > is the same as that of the P-type current source IP <0 >. The pull-down path comprises an N-type current source and an N-type switch, as shown IN FIG. 2, the pull-down path sequentially comprises an N-type current source IN <0>, an N-type current source IN <1> … … and an N-type current source IN < N >, wherein the source of the N-type current source IN <0> is simultaneously connected with the P-type switch DP <0>, one end of the delay capacitor C0 and the duty ratio recovery circuit 25 through the N-type switch DN <0>, and the drain of the N-type current source IN <0> is simultaneously connected with the other end of the delay capacitor C0 and grounded; the other end of the duty recovery circuit 25 outputs a DSR signal, and the connection mode of the N-type current source IN <1> … … N-type current source IN < N > is the same as the connection mode of the N-type current source IN <0>, where N is an integer greater than or equal to 1. The P-type current source refers to a current source made of a PMOS (P-channel metal oxide semiconductor) tube, and the source electrode of the current source refers to a source electrode made of a PMOS tube of the current source.
Meanwhile, as shown in fig. 2, the control circuit of the P-type switch of the present invention includes a P-type and gate 21, wherein the input signal D and the array selection signal DLY _ TRIM < n:0> are connected to the input end of the P-type and gate 21, and the control signal DP < n:0> of the P-type switch is obtained after the operation of the P-type and gate 21. The control circuit of the N-type switch comprises an inverter 22 and an N-type AND gate 23, wherein an input signal D is subjected to the inverter 22 to obtain an inverted input signal D, the inverted input signal D and an array selection signal DLY _ TRIM < N:0> are connected to the input end of the N-type AND gate 23, and a control signal DN < N:0> of the N-type switch is obtained after the operation of the N-type AND gate 23.
The working principle of the delay control module circuit in the invention is as follows: in the rising process of the signal D, the pull-up path in the main circuit 24 is opened to charge the delay capacitor C0, the potential of the output signal is slowly increased, and the output signal is adjusted by the duty recovery circuit 25 and then output, so that the rising edge delay of the D signal is realized. In the falling process of the signal D, the pull-down path in the main circuit 24 is opened to discharge the delay capacitor C0, the potential of the output signal is slowly reduced, and the output signal is adjusted by the duty recovery circuit 25 and then output, so that the falling edge delay of the D signal is realized. The above-described delay time adjustment can be adjusted by the selection signal DLY _ TRIM < n:0> of the main circuit 24 and the main circuit 24, respectively.
As shown in fig. 3, the edge pulse generator module of the present invention includes a rising edge pulse circuit for outputting a rising edge pulse signal SR _ H and a falling edge pulse circuit for outputting a falling edge pulse signal SR _ L. The rising edge pulse circuit comprises a rising edge exclusive-or gate 11, a rising edge and gate 12 and a rising edge inverter 13, wherein the input signals D and DSR are compared through the rising edge exclusive-or gate 11 to obtain an edge pulse signal edge _ pulse, and the pulse width of the edge pulse signal is the delay between the DSR signal and the input signal. The edge pulse signal edge _ pulse and the input signal D are input together into the rising edge and gate 12 for logic operation, and then a negative pulse signal positively correlated to the rising edge pulse is obtained, and then a rising edge pulse signal SR _ H positively correlated to the rising edge delay is obtained through the rising edge inverter 13.
The falling edge pulse circuit comprises a falling edge inverter 14, a falling edge AND gate 15 and a falling edge driver 16; the input signal D is subjected to falling edge phase inverter 14 to obtain an inverted input signal D, the inverted input signal D and the edge pulse signal edge _ pulse are jointly input into a falling edge AND gate 15 to perform logic operation, then a positive pulse signal positively correlated with falling edge delay is obtained, and then a falling edge pulse signal SR _ L is obtained through a falling edge primary driver 16, wherein the edge pulse signal edge _ pulse adopted in the falling edge pulse circuit is the same as the edge pulse signal generated in the rising edge pulse circuit.
Fig. 4 is a schematic diagram of the operation timing of the driver circuit according to the present invention. D is an inverse signal of the input signal D, the DSR signal is an output signal of the D signal passing through the delay control module 2, and the rising delay of the DSR signal and the D signal is TrlpWith a falling delay of Tflp. Each rising edge of the input signal D correspondingly generates an SR _ H pulse, and each falling edge correspondingly generates an SR _ L pulse. The width of the two pulse signals is determined by the delay between the D signal and the DSR signal, namely, the delay control module 2 is used for adjusting the width, and the design of the delay time can directly correspond to the electrical requirements in the MIPI DPHY protocol during design. And finally, the potential logic of the output signal Z is consistent with that of the input signal D, and the slew rate of the output signal Z is adjusted by the slew rate control array 3.
Claims (10)
1. The low-power-consumption driver circuit with the adjustable slew rate is characterized by comprising a delay control module, an edge pulse generator module and a driver module, wherein the driver module comprises a first driver unit and a second driver unit; wherein, the input signal is connected to the delay control module and outputs DSR signal, the DSR signal and the inverted input signal are input into the edge pulse generator module together, and after logic processing, a rising edge pulse signal and a falling edge pulse signal are generated, the inverted input signal controls the first driving unit, and the rising edge pulse signal and the falling edge pulse signal control the second driving unit;
the first driver unit comprises a PMOS tube MP0 and an NMOS tube MN0, wherein the gate of the PMOS tube MP0 is connected with an inverted input signal, and the source is connected with a power supply voltage; the grid electrode of the NMOS transistor MN0 is connected with an inverted input signal, the source electrode of the NMOS transistor MN0 is grounded, and the drain electrodes of the PMOS transistor MP0 and the NMOS transistor MN0 are connected with an output signal together;
the second driving unit comprises a rising edge circuit and a falling edge circuit which are connected in parallel, the rising edge circuit comprises m rising edge driving branches which are connected in series, each rising edge driving branch comprises a rising edge switch and one of MP1-MPm of a PMOS (P-channel metal oxide semiconductor) tube, the grid electrode of one of MP1-MPm of the PMOS tube is connected with a rising edge pulse signal through the rising edge switch, the source electrode of the one of MP1-MPm of the PMOS tube is connected with a power supply voltage, and the drain electrode of the one of MP1-MPm of the PMOS tube is connected with an output signal; the falling edge circuit comprises m falling edge driving branches which are connected in series, each falling edge driving branch comprises a falling edge switch and one of MN1-MNm of NMOS tubes, the grid electrode of one of MN1-MNm of the NMOS tubes is connected with a falling edge pulse signal through the falling edge switch, the source electrode is grounded, the drain electrode is connected with an output signal, and m is an integer larger than 1.
2. The adjustable slew rate low power driver circuit of claim 1, where the source and drain of the PMOS and NMOS transistors are interchangeable.
3. The low-power-consumption driver circuit with the adjustable slew rate of claim 1, wherein the delay control module comprises a main circuit, a delay capacitor and a duty cycle recovery circuit, the main circuit comprises n +1 branches connected in parallel, each branch comprises a pull-up path and a pull-down path connected in series, the pull-up path comprises a P-type current source and a P-type switch, the source of the P-type current source is connected with a power voltage, and the drain of the P-type current source is simultaneously connected with one end of the delay capacitor and the duty cycle recovery circuit through the P-type switch; the pull-down path comprises an N-type current source and an N-type switch, wherein the source electrode of the N-type current source is simultaneously connected with the P-type switch, one end of the delay capacitor and the duty cycle recovery circuit through the N-type switch, and the source electrode is simultaneously connected with the other end of the delay capacitor and grounded; the other end of the duty ratio recovery circuit outputs a DSR signal, wherein n is an integer which is greater than or equal to 1; the P-type current source refers to a current source made of a PMOS (P-channel metal oxide semiconductor) tube, and a source electrode of the current source refers to a source electrode of the PMOS tube made of the current source; the N-type current source refers to a current source made of an NMOS tube, and a source electrode of the current source refers to a source electrode made of an NMOS tube of the current source.
4. The slew rate adjustable low power driver circuit of claim 3, where the control circuit of the P-type switch comprises a P-type AND gate, where the input signal and the array selection signal are connected to an input of the P-type AND gate, and the control signal of the P-type switch is obtained after operation of the P-type AND gate.
5. The low-power-consumption driver circuit with the adjustable slew rate of claim 3, wherein the control circuit of the N-type switch comprises an inverter and an N-type AND gate, wherein the input signal passes through the inverter to obtain an inverted input signal, the inverted input signal and the array selection signal are connected to the input end of the N-type AND gate, and the control signal of the N-type switch is obtained after the operation of the N-type AND gate.
6. The adjustable slew rate low power driver circuit of claim 1, where the edge pulse generator module comprises a rising edge pulse circuit and a falling edge pulse circuit, the rising edge pulse circuit configured to output a rising edge pulse signal, and the falling edge pulse circuit configured to output a falling edge pulse signal.
7. The adjustable slew rate low power driver circuit of claim 6, where the rising edge pulse circuit comprises a rising edge exclusive-or gate, a rising edge and gate, and a rising edge inverter, where the input signal and the DSR signal are compared by the rising edge exclusive-or gate to obtain an edge pulse signal, the edge pulse signal and the input signal are input together into the rising edge and gate to perform logic operation to obtain a negative pulse signal positively correlated to the rising edge pulse, and the rising edge pulse signal positively correlated to the rising edge delay is obtained by the rising edge inverter.
8. The adjustable slew rate low power driver circuit of claim 6 where the falling edge pulse circuit comprises a falling edge inverter, a falling edge AND gate and a falling edge drive; the input signal is processed by a falling edge inverter to obtain an inverted input signal, the inverted input signal and the edge pulse signal are jointly input into a falling edge AND gate to be subjected to logic operation to obtain a positive pulse signal positively correlated with the falling edge delay, and the falling edge pulse signal is obtained by the falling edge primary driver.
9. The adjustable slew rate low power driver circuit of claim 6, where the edge pulse signal has a pulse width that is the delay between the DSR signal and the input signal.
10. The adjustable slew rate low power driver circuit of any of claims 1-9 where the output signal has a potential logic that is consistent with the input signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810320688.XA CN108667453B (en) | 2018-04-09 | 2018-04-09 | A low-power driver circuit with adjustable slew rate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810320688.XA CN108667453B (en) | 2018-04-09 | 2018-04-09 | A low-power driver circuit with adjustable slew rate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108667453A CN108667453A (en) | 2018-10-16 |
| CN108667453B true CN108667453B (en) | 2021-08-31 |
Family
ID=63782324
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810320688.XA Active CN108667453B (en) | 2018-04-09 | 2018-04-09 | A low-power driver circuit with adjustable slew rate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108667453B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111030726B (en) * | 2019-12-13 | 2022-02-25 | 展讯通信（上海）有限公司 | Radio frequency front end control circuit and control method thereof, radio frequency front end control chip, system, storage medium and terminal |
| CN113381774B (en) * | 2020-03-09 | 2022-07-19 | 瑞昱半导体股份有限公司 | Transmitting circuit and working method thereof |
| CN111555737B (en) * | 2020-05-21 | 2022-05-20 | 广东省大湾区集成电路与系统应用研究院 | A controllable slew rate N-type MOS high-side driver circuit |
| CN111654267B (en) * | 2020-05-28 | 2024-02-13 | 广东浪潮大数据研究有限公司 | Adjustable pulse generator |
| CN114204919B (en) * | 2020-09-18 | 2025-02-21 | 长鑫存储技术有限公司 | Delay circuits and delay structures |
| CN115800993B (en) * | 2023-02-07 | 2023-05-05 | 珠海巨晟科技股份有限公司 | Slew rate control IO circuit and chip |
| CN119071118B (en) * | 2024-11-05 | 2025-01-21 | 成都电科星拓科技有限公司 | Circuit for improving high-speed communication signal quality |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102916666A (en) * | 2011-08-02 | 2013-02-06 | 中国科学院微电子研究所 | Broadband programmable gain amplifier |
| CN103916098A (en) * | 2014-03-28 | 2014-07-09 | 南京邮电大学 | Programmable gain amplifier with high gain precision |
| CN104584425A (en) * | 2012-05-10 | 2015-04-29 | 塔特公司 | Programmable-gain amplifier |
| CN105743454A (en) * | 2016-01-31 | 2016-07-06 | 天津大学 | Binary weighted linear-in-dB switch resistor type CMOS programmable gain amplifier |
| CN107370465A (en) * | 2017-06-20 | 2017-11-21 | 和芯星通（上海）科技有限公司 | High-precision broadband programmable gain amplifier |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20060058841A (en) * | 2004-11-26 | 2006-06-01 | 삼성전자주식회사 | Output driver to adjust the slew rate in the predetermined section of the output signal |
| KR100815177B1 (en) * | 2006-07-20 | 2008-03-19 | 주식회사 하이닉스반도체 | Semiconductor devices |
| JP2008098920A (en) * | 2006-10-11 | 2008-04-24 | Rohm Co Ltd | Driver circuit |
| US7432730B2 (en) * | 2007-01-09 | 2008-10-07 | International Business Machines Corporation | Time based driver output transition (slew) rate compensation |
| EP2693640B1 (en) * | 2011-03-31 | 2017-09-13 | Renesas Electronics Corporation | Serial communication device |
| CN102158207B (en) * | 2011-04-12 | 2013-04-24 | 广州金升阳科技有限公司 | Impulse modulation method and circuit for switch transistor drive signals |
| JP6349897B2 (en) * | 2014-04-11 | 2018-07-04 | 株式会社デンソー | Timing adjustment method for drive circuit and timing adjustment circuit for drive circuit |
| CN104299640B (en) * | 2014-09-29 | 2017-02-22 | 灿芯半导体(上海)有限公司 | Slew rate adaptive adjustment output circuit |
| CN105589827B (en) * | 2016-03-09 | 2018-09-04 | 无锡新硅微电子有限公司 | Adaptive slew rate for RS-485 interface circuits adjusts circuit |
-
2018
- 2018-04-09 CN CN201810320688.XA patent/CN108667453B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102916666A (en) * | 2011-08-02 | 2013-02-06 | 中国科学院微电子研究所 | Broadband programmable gain amplifier |
| CN104584425A (en) * | 2012-05-10 | 2015-04-29 | 塔特公司 | Programmable-gain amplifier |
| CN103916098A (en) * | 2014-03-28 | 2014-07-09 | 南京邮电大学 | Programmable gain amplifier with high gain precision |
| CN105743454A (en) * | 2016-01-31 | 2016-07-06 | 天津大学 | Binary weighted linear-in-dB switch resistor type CMOS programmable gain amplifier |
| CN107370465A (en) * | 2017-06-20 | 2017-11-21 | 和芯星通（上海）科技有限公司 | High-precision broadband programmable gain amplifier |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108667453A (en) | 2018-10-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108667453B (en) | A low-power driver circuit with adjustable slew rate | |
| US8519762B2 (en) | Adjusting circuit of duty cycle and its method | |
| US8362818B2 (en) | Clock adjustment circuit, shift detection circuit of duty ratio, imaging device and clock adjustment method | |
| WO2022057366A1 (en) | Negative voltage level conversion control circuit and method | |
| CN113054950B (en) | Relaxation oscillator and memory chip | |
| US8823440B2 (en) | Level shifting circuit with dynamic control | |
| CN110045372B (en) | Ultra-Wideband Pulse Signal Transmitting Device and Ultra-Wideband Pulse Radar System | |
| CN102256425B (en) | Self-adaptive dead-zone time control circuit in half-bridge driver chip of electronic ballast | |
| CN101043211A (en) | Complementary signal generating circuit | |
| CN104935162B (en) | Drive circuit, integrated circuit device, and control method of charge pump circuit | |
| CN100488036C (en) | D type amplifier and modulating method thereof | |
| CN102255497B (en) | Control circuit of charge pump circuit | |
| CN106849922A (en) | An adjustable delay circuit | |
| CN103138744A (en) | Semiconductor apparatus | |
| CN105227162A (en) | A kind of signal burr eliminates circuit | |
| CN108920779B (en) | Regeneration-based variable gain amplifier structure and control method thereof | |
| KR102034903B1 (en) | Cmos inverter circuit device | |
| US12301237B2 (en) | Voltage conversion circuit and memory | |
| CN108832896B (en) | An off-chip adjustable relaxation voltage-controlled oscillator circuit | |
| JP2010028244A (en) | Hysteresis comparator circuit and delay circuit using the same | |
| US20110012685A1 (en) | Wide-band Low-voltage IQ-generating Ring-oscillator-based CMOS VCO | |
| CN103580670B (en) | Dynamic control level shift circuit | |
| CN115514909B (en) | A three-level high-voltage drive conversion circuit for electron multiplying CCD | |
| CN115865065B (en) | Low-power-consumption high-side driving circuit and chip | |
| JP6127990B2 (en) | Inverse level shift circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |