CN108257910A - Method for manufacturing shallow trench isolation trench - Google Patents

Abstract

The present invention discloses a method for manufacturing a shallow trench isolation groove, which comprises providing a substrate, then forming a first mask to cover the substrate, the first mask comprising a plurality of sub-masks, a first groove being arranged between adjacent sub-masks, then forming a protective layer to fill the first groove, then forming a second mask to cover the first mask, the second mask comprising an opening, wherein the sub-mask arranged directly below the opening is defined as a joint shallow trench pattern, then using the second mask as a mask to remove the joint shallow trench pattern to transform the first mask into a third mask, then removing the second mask and the protective layer, and finally using the third mask as a mask to remove part of the substrate to form a plurality of shallow trench isolation grooves.

Description

Method for making shallow trench isolation trenches

technical field

The invention relates to a manufacturing method of a shallow trench isolation trench, in particular to a manufacturing method for more precisely defining the position of the shallow trench isolation trench by using a protective layer.

Background technique

In the semiconductor manufacturing process, in order to have a good isolation between the various electronic components on the chip and avoid short circuits caused by mutual interference between the components, localized oxidation isolation (LOCOS) or shallow trench isolation (shallow trench isolation) are generally used. isolation, STI) method for isolation and protection. Since the area of the chip occupied by the field oxide layer (field oxide) produced in the LOCOS manufacturing process is too large, and the generation process will be accompanied by the occurrence of the bird's beak phenomenon, therefore, it has small-size isolation line width, clear active area division, and uniform The shallow trench isolation method, which has advantages such as the depth and size of the isolation region, and the excellent flat structure of the isolation region, has gradually become the mainstream of the current semiconductor device isolation technology.

The manufacturing method of shallow trench isolation is generally to form a trench between the components on the surface of the chip, and fill it with an insulating layer to produce the effect of electrical isolation. As the volume of the semiconductor element shrinks, the layout of the shallow trench isolation is also adjusted accordingly. However, when the trench of the shallow trench isolation is fabricated, etching to a predetermined position of the active region may occur.

Contents of the invention

In view of this, the object of the present invention is to provide a method for fabricating a shallow trench isolation trench, so as to avoid etching to a predetermined position of the active region when defining the shallow trench isolation trench.

According to a preferred embodiment of the present invention, a method for manufacturing shallow trench isolation trenches includes providing a substrate, and then forming a first mask covering the substrate, the first mask including a plurality of sub-masks, wherein a first A groove is disposed between adjacent sub-masks, and then a protective layer is formed to fill the first groove, and then a second mask is formed to cover the first mask, and the second mask includes an opening, wherein the The sub-mask directly below the opening defines a joint shallow trench pattern, and then the second mask is used as a mask to remove the joint shallow trench pattern to convert the first mask into a third mask, followed by removing the second mask and removing the protection layer, and finally using the third mask as a mask to remove part of the substrate to form a plurality of shallow trench isolation trenches.

According to a preferred embodiment of the present invention, the first mask includes a first material, the protection layer includes a second material, and the first material and the second material have a high selectivity ratio compared to a predetermined etchant.

According to a preferred embodiment of the present invention, the first material includes silicon nitride, the protective layer includes silicon oxide, and the predetermined etchant includes fluorine-containing gas.

Description of drawings

1 to 9 are schematic diagrams of a method for fabricating shallow trench isolation trenches according to a preferred embodiment of the present invention;

FIG. 10 is a top view showing the positions of shallow trench isolations and active regions according to a preferred embodiment of the present invention;

Fig. 11 is a side view along the line AA' in Fig. 10 .

Description of main component symbols

10 Substrate 12 Material layer

14 Silicon oxide layer 16 Amorphous silicon layer

18 Silicon nitride layer 20 First patterned photoresist layer

22 Opening 23 Groove

24 Organic dielectric layer 26 Silicon-containing bottom anti-reflection layer

28 Silicon oxide layer 30 Organic dielectric layer

32 Second patterned photoresist layer 34 First mask

36 First trench 38 Protective layer

40 second mask 42 organic dielectric layer

44 Silicon-containing bottom anti-reflective layer 46 Photoresist

48 Opening 50 Engage Shallow Trench Pattern

52 Opening 54 Shallow groove pattern in peripheral area

58 shallow trench isolation trench 60 insulating layer

132 masks 134 masks

158 Trench 160 Shallow Trench Isolation

234 third mask 258 trench

260 Junction Shallow Trench Isolation 358 Trench

360 shallow trench isolation 362 active area

364 active area

Detailed ways

As shown in Figure 1, a base 10 is first provided, the base 10 is divided into an active array area A and a peripheral circuit area B, the base 10 is covered with a material layer 12, and the material layer 12 can be a single-layer material or a multi-layer stacked material, The material layer 12 may include materials such as silicon oxide, amorphous silicon, silicon nitride, and silicon oxynitride. According to a preferred embodiment of the present invention, the material layer 12 is a multilayer stacked material including a silicon oxide layer 14, an amorphous silicon Layer 16 and a silicon nitride layer 18 are stacked from bottom to top, the thickness of silicon oxide layer 14 is preferably about 1300 angstroms, the thickness of amorphous silicon layer 16 is preferably about 700 angstroms, and the thickness of silicon nitride layer 18 is preferably About 400 Angstroms. Next, a first patterned mask layer 20 is formed. The first patterned mask layer 20 includes a plurality of openings 22. The first patterned mask layer 20 consists of an organic dielectric layer 24 and a silicon-containing bottom anti-reflection layer. 26 (silicon-containing hard mask bottommanti-reflection coating, SHB). As shown in FIG. 2 , a silicon oxide layer 28 is formed to conformably cover the first patterned mask layer 20 . The thickness of the silicon oxide layer 28 is preferably between 20 and 23 nanometers, for example, 21.5 nanometers. Then form a sacrificial layer, for example organic dielectric layer 30 covers silicon oxide layer 28 and fills each opening 22, organic dielectric layer 30 preferably has the same etch rate as compared to the same etchant with organic dielectric layer 24, as As shown in FIG. 3 , the organic dielectric layer 30 is first etched back, and then the etchant is replaced to etch the silicon oxide layer 28 on the upper surface of the organic dielectric layer 30 and the silicon oxide layer 28 on the sidewall of the opening 22. A second patterned mask layer 32, the second patterned mask layer 32 is composed of the organic dielectric layer 24 and the remaining silicon oxide layer 28, the second patterned mask layer 32 includes a plurality of sub-masks 132, In addition, the trenches 23 are disposed between adjacent sub-masks 132 , and the width of the trenches 23 corresponds to the thickness of the silicon oxide layer 28 , preferably between 20 and 23 nanometers, such as 21.5 nanometers.

As shown in FIG. 4, the second patterned mask layer 32 is used as a mask to pattern the material layer 12, so as to transfer the pattern on the second patterned mask layer 32 to the material layer 12 in a manner of transferring Dry etching is preferred. At this time, the patterned material layer 12 becomes a first mask 34, and then the organic dielectric layer 24 in the second patterned mask layer 32 is removed, and the silicon oxide layer 28 is retained. In one embodiment, the silicon oxide layer 28 may also be removed, and the silicon oxide layer 28 is taken as an example in the subsequent manufacturing process. In addition, when the material layer 12 is a multi-layer stacked material, the first mask 34 is formed in the uppermost material layer in the material layer 12. According to a preferred embodiment of the present invention, as mentioned above, the material layer 12 includes The silicon oxide layer 14, the amorphous silicon layer 16 and the silicon nitride layer 18 are stacked from bottom to top, and the first mask 34 is only formed in the silicon nitride layer 18, and there is no mask on the silicon oxide layer 14 and the amorphous silicon layer 16. pattern. The first mask 34 includes a plurality of sub-masks 134, and a first trench 36 is disposed between adjacent sub-masks 134. The width of the first trench 36 is preferably between 20 and 23 nanometers. For example, it is 21.5 nanometers.

As shown in FIG. 5 , a protective layer 38 is formed to conformably cover each sub-mask 134 and fill each first trench 36. The protective layer 38 is preferably a single-layer material. The material of the mask 34 has a high selectivity ratio compared to a predetermined etchant, in detail, when the same etchant is used, the etching rate for the first mask 34 and the etching rate for the protective layer 38 are greatly different , the etchant that can etch the first mask 34 cannot etch the protection layer 38 . The material of the protective layer 38 includes silicon oxide, silicon nitride, amorphous silicon or silicon oxynitride, etc. According to a preferred embodiment of the present invention, the protective layer 38 is preferably silicon oxide, and the thickness of the protective layer 38 is preferably greater than that of the first One-half of the width of the trench 36, for example greater than 12 nanometers, to ensure that the first trench 36 is filled, the protective layer 38 can be produced by atomic layer deposition, chemical deposition, physical deposition or other suitable way of making.

As shown in FIG. 6, a second mask 40 is formed to cover the first mask 34. The second mask can be a single-layer material or a multi-layer stacked material. In an embodiment of the present invention, the second mask 40 is multiple Layer stacking material. The multilayer stacking material includes an organic dielectric layer 42, a silicon-containing bottom anti-reflection layer 44 and a photoresist 46 stacked from bottom to top. The second mask 40 includes at least one opening 48, the opening 48 It may be located only in the photoresist 46, that is to say, the opening 48 does not extend into the silicon-containing bottom anti-reflection layer 44 and the organic dielectric layer 42. Of course, depending on different circumstances, the opening 48 may also run through the entire second mask 40. . In addition, the position of the opening 48 is used to define the bonding area of the following two shallow trench isolations. The sub-mask 134 directly below the opening 48 is defined as a bonding shallow trench pattern 50 (marked with oblique lines), and the protective layer 38 is contacted and bonded. opposite sidewalls of the shallow trench pattern 50 . In one embodiment, the sidewalls of the opening 48 can be aligned with the sidewalls of the joint shallow trench pattern 50 , and in another embodiment, the sidewalls of the opening 48 can be aligned with the sidewalls on both sides of the joint shallow trench pattern 50 . Any position of the passivation layer 38 is taken as an example in the middle of the passivation layer 38 where the sidewalls of the opening 48 are aligned with the two sides of the shallow trench pattern 50 in the figure. The second mask may further include an opening 52. The position of the opening 52 is used to define the position of the shallow trench isolation in the peripheral circuit area B. The sub-mask 134 directly below the opening 50 defines a shallow trench pattern in the peripheral area. 54 (marked with a slash).

As shown in FIG. 7 , using the second mask 40 as a mask, the bonding shallow trench pattern 50 and the peripheral region shallow trench pattern 54 are removed. trench pattern 50, and the bonding shallow trench pattern 50 and protective layer 38 have a high selectivity ratio compared to the same etchant, and this selection ratio is preferably more than 10, so when removing the bonding shallow trench pattern 50, the protective layer 38 It may act as a stop layer so that other sub-masks 134 adjacent to the bonding shallow trench pattern 50 are not etched away. In detail, the steps used in removing the joint shallow trench pattern 50 and the peripheral area shallow trench pattern 54 include first dry etching the upper surface of the joint shallow trench pattern 50 and the peripheral area shallow trench pattern 54 with a fluorine-containing gas. The protective layer 38 on the upper surface of the case, and then use trifluoromethane (CHF ₃ ) dry etching to join the shallow trench pattern 50 and the shallow trench pattern 54 in the peripheral area. At this time, the protective layer 38 in the first trench 36 Just as a stop layer for etching with trifluoromethane. After removing the bonding shallow trench pattern 50 and the peripheral area shallow trench pattern 54 on the first mask 34, the first mask 34 is transformed into a third mask 234, and there are still The passivation layer 38 , the silicon oxide layer 28 and the second mask 40 are covered, and then the second mask 40 is removed. As shown in FIG. 8, the protective layer 38 is completely removed. In addition, since the protective layer 38 is silicon oxide in this embodiment, the silicon oxide layer 28 will also be removed at the same time, and the third mask 234 is completely exposed. The method of removing the protective layer 38 can be wet etching, and the protective layer 38 can be completely removed with a dilute hydrofluoric acid solution.

As shown in FIGS. 8 and 9 , using the third mask 234 as a mask, part of the substrate 10 is removed to form a plurality of shallow trench isolation trenches 58 in the substrate. The method of removing the substrate 10 is preferably Dry etching, when dry etching the substrate 10, the substrate 10 can be etched at an oblique angle intentionally, so that the opening width of the shallow trench isolation trench 58 formed after this will be smaller than the opening width on the third mask 234, for example That is, if the width of the first trench 36 is 21.5 nm, the opening width of the trench 158 can be reduced to 18 nm. In this embodiment, the substrate 10 is etched at a vertical angle, so the opening width of the formed STI trench 58 is the same as the opening width of the third mask 234 . In addition, as mentioned above, in this embodiment, the material layer 12 is taken as an example of a multi-layer stack material, and the third mask 234 is formed on the uppermost material layer in the multi-layer stack material, so when forming shallow trench isolation trench 58, it is necessary to use the third mask 234 as a mask to etch the middle and lower layer materials in the material layer 12 first, and then continue to etch the substrate 10. Specifically, the third mask formed in the silicon nitride layer 18 The mask 234 is a mask to etch the amorphous silicon layer 16 and the oxide layer 14, and then continue to etch the substrate 10, and when the substrate 10 is etched, the amorphous silicon layer 16 and the oxide layer 14 will be consumed and thinned, or even completely consumed . After the shallow trench isolation trench 58 is completed, if there is still the silicon oxide layer 14 remaining, wet etching can be used to completely remove the oxide layer 14 with a dilute hydrofluoric acid solution. In the shallow trench isolation trench 58, the trench 158 will become a shallow trench isolation after the subsequent filling of insulating material, and the trench 258 will become a bonding shallow trench isolation after the subsequent filling of insulating material for connecting Two adjacent shallow trenches are isolated, and the trench 358 will become the shallow trench isolation of the peripheral circuit area after being filled with insulating material. The opening width of the trench 158 is preferably between 13 and 18 nanometers, the opening width of the trench 258 is preferably between 46 and 54 nanometers, and the opening width of the trench 358 depends on the required shallow trench isolation width of the peripheral circuit area. The depths of the grooves 158 , 258 and 358 are preferably between 2500 and 3500 nanometers.

Figure 11 is a top view of the shallow trench isolation and the location of the active region. Fig. 10 is a side view along line AA' in Fig. 11 . Please refer to FIG. 10 and FIG. 11 at the same time, the insulating layer 60 is filled in the trench 158 , the trench 258 and the trench 358 to form the shallow trench isolation 160 , and connect the shallow trench isolation 260 and the shallow trench isolation 360 . At this time, the shallow trench isolation 160 and the joint shallow trench isolation 260 define an active region 362 in the active array region A of the substrate 10, and the shallow trench isolation 360 located in the peripheral circuit region B is defined in the peripheral circuit region B of the substrate 10 out of the active area 364 .

The invention utilizes the protection layer to ensure that the adjacent sub-mask will not be damaged when the bonding shallow trench pattern is removed, so as to prevent the subsequently formed shallow trench isolation from encroaching on the position of the active region.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (7)

1. A method of manufacturing a shallow trench isolation trench, comprising: provide a base; forming a first mask covering the substrate, the first mask comprising a plurality of sub-masks, wherein a first groove is disposed between adjacent sub-masks; forming a protection layer to fill the first trench; forming a second mask covering the first mask, the second mask including an opening, wherein the sub-mask disposed directly below the opening defines a bonding shallow trench pattern; using the second mask as a mask, removing the bonding shallow trench pattern to convert the first mask into a third mask; removing the second mask; remove that protective layer; and Using the third mask as a mask, part of the substrate is removed to form a plurality of shallow trench isolation trenches. 2. The method for fabricating shallow trench isolation trenches as claimed in claim 1, wherein the first mask comprises a first material, the protective layer comprises a second material, and the first material is the same as the second material The predetermined etchant has a high selectivity. 3. The method for fabricating shallow trench isolation trenches as claimed in claim 2, wherein the first material comprises silicon nitride, the protection layer comprises silicon oxide, and the predetermined etchant comprises fluorine-containing gas. 4. The method for fabricating STI trenches according to claim 1, further comprising removing the bonding shallow trench pattern while partially removing the bonding shallow trench pattern using the second mask as a mask. The protection layer is adjacent to the groove pattern. 5. The method for fabricating STI trenches as claimed in claim 1, wherein the opening is aligned with the joint shallow trench pattern. 6 . The method for fabricating STI trenches as claimed in claim 1 , wherein sidewalls of the opening are flush with the passivation layer adjacent to the bonding shallow trench pattern. 7 . 7. The method for fabricating a shallow trench isolation trench as claimed in claim 1, further comprising: removing the third mask after forming the plurality of shallow trench isolation trenches; and An insulating layer is formed to fill the plurality of shallow trench isolation trenches.