CN105958987A - Clock dynamic calibration method and circuit based on UHF RFID chip - Google Patents
Clock dynamic calibration method and circuit based on UHF RFID chip Download PDFInfo
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- CN105958987A CN105958987A CN201610422539.5A CN201610422539A CN105958987A CN 105958987 A CN105958987 A CN 105958987A CN 201610422539 A CN201610422539 A CN 201610422539A CN 105958987 A CN105958987 A CN 105958987A
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- 238000007493 shaping process Methods 0.000 claims description 7
- 238000004422 calculation algorithm Methods 0.000 claims description 5
- 238000007599 discharging Methods 0.000 claims description 5
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- 230000001276 controlling effect Effects 0.000 claims description 2
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- 238000004891 communication Methods 0.000 abstract description 2
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/28—Modifications for introducing a time delay before switching
- H03K17/284—Modifications for introducing a time delay before switching in field effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17724—Structural details of logic blocks
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Abstract
The invention relates to a clock dynamic calibration method and circuit based on a UHF RFID chip. A control current controls the magnitude of the charge/discharge current of a capacitor in an oscillator, therefore, the duration of the charge/discharge time of the capacitor is controlled, and the frequency of an output clock is controlled. For clock calibration, a current calibration mode is employed. A baseband processor carries out dynamic calibration on the clock frequency according to signals of a reader. When the offset of the output clock exceeds a certain range, a set of data is returned by a digital baseband for changing the magnitude of the control current, thereby changing the frequency of the output clock. A reader command is received, and moreover, the clock is adjusted for many times. When reception of the command is finished, the signals are reversely transmitted to the reader through the optimum clock, and therefore, a label can be identifier precisely. According to the method and the circuit, the success rate of communication between the label chip and the reader of the clock circuit can reach 100%, and namely, each time of operation of the reader to the label chip can be responded by the label chip correctly.
Description
Technical field
The present invention relates to passive ultra-high frequency technical field of RFID, particularly relate to a kind of based on UHF RFID core
The clock dynamic calibration method of sheet and circuit.
Background technology
Current passive super high frequency radio frequency identification technology has at a distance, at high speed, low cost and advantage easily,
It is widely used to the fields such as identification, logistics management, warehousing management, and Future Information society will be become builds
If a basic technology.Wherein in UHF RFID, the effect of clock circuit is demodulation reader forward direction transmission number
According to, and provide a clock accurately, in order to accurately control backscattered number to chip modulation reflected signal
According to link frequency and the work clock that provides whole label digital circuit.
As illustrated in fig. 1 and 2, traditional clock circuit is by current mirror, ring oscillator and output driving three
Part composition.Current mirror is mainly clock circuit and provides an image current, works for clock circuit；Ring
Shape agitator mainly generates a clock signal not stopping upset according to frequency needs；Output driving circuit is main
The clock signal that ring oscillator generates is carried out a shaping, and the driving force of signal is strengthened, in order to drive
The late-class circuit of dynamic chip.
The clock of traditional clock circuit output does not feed back to prime and carries out the correction of a clock frequency, does not i.e. have
Having one loop of formation, the ring oscillator of prime cannot obtain the clock frequency actually generated and intended clock
Frequency departure has much.Such loop may be under different temperatures, different process deviation, actual clock
Frequency meeting deviation is very big, and beyond the deviation of regulation, label chip possibly cannot read card reader in this case
Instruction and correct decoding, or may be with the frequency of mistake to card reader back-scatter data, to such an extent as to label
Chip cannot communicate normally with reader.
Agitator is the nucleus module of whole clock generation circuit, and its design will directly influence the property of whole label
Energy.Due to reasons such as process deviations, cause the scope of clock output frequency deviation protocol requirement, when now needing
Clock calibration is the Frequency point of the clock alignment of deviation to needs.Prior art problem to be solved be agitator and time
Clock calibration circuit is capable of the function of clock circuit together, normally work for chip offer the most accurately time
Clock.
Summary of the invention
It is an object of the invention to: for above-mentioned technical problem present in prior art, it is provided that a kind of agitator
It is capable of the function of clock circuit together with clock calibration circuit, normally works offer for chip the most accurately
Clock.
The present invention is achieved by the following technical solutions:
A kind of clock dynamic calibration method based on UHF RFID chip, controls electric capacity in current control oscillator
The size of charging and discharging currents, thus control the length of capacitor charge and discharge time, control to export the frequency of clock；
Clock alignment uses the mode of correcting current, baseband processor carry out clock frequency according to the signal of reader
Dynamic calibration；When clock deviation exceeds certain scope when output, digital baseband returns one group of data and changes control
The size of electric current, changes the frequency of output clock, can enter clock while receiving a reader command
Row repeatedly adjusts, with optimum time clockwise reader back emitted signal when order finishes receiving so that label can
With by the most errorless identification.
Described clock dynamic calibration circuit based on UHF RFID chip, wherein, including current reference module,
Clock alignment module, oscillator module and digital baseband block；The outfan of current reference module and clock alignment
One input of module is connected, and the outfan of clock alignment module is connected with the input of oscillator module, shakes
The outfan swinging device module is connected with another input of clock alignment module by digital baseband block；Described
Oscillator module is made up of first, second and third grade of inverter circuit and clock shaping circuit；Described clock alignment mould
Block is regulated circuit by charged electrical voltage regulator circuit and charging capacitor and forms；Described digital baseband block is by digital circuit
Clock dynamically regulates logic D1 and numeral circuit clock dynamically regulates logic D2 composition.
Further, described current reference module is formed by emitter follower M0, device M1, M2, device M1,
M2, M3 constitute mirror current source, and mirror current source is charging/discharging voltage regulation circuit and first order inverter circuit
Electric current is provided；Device M0 uses NMOS tube, and device M1, M2, M3 use PMOS.
Further, described first order negative circuit is made up of device M4, M5, M6, M7, works in differential mode
Formula, it is achieved electric capacity is replaced discharge and recharge；Described device M4, M6 use PMOS, and device M5, M7 use
NMOS tube.
Further, described second and third grade of inverter circuit is made up of trigger RS1, RS2 respectively；Described
Two, the output signal of three grades of inverter circuits is as the input signal of first order negative circuit；First, second and third
Level inverter circuit constitutes annular oscillation circuit.
Further, described clock shaping circuit is made up of device M11～M16, by the output clock signal side of being shaped to
Ripple signal, and provide certain driving force to drive late-class circuit.
Further, described charged electrical voltage regulator circuit by reference current source and adjustable resistance R1, R2, R4, R8,
R16, R32, R64 are constituted, it is achieved the control to capacitor charge and discharge node voltage；Described reference current source is by device
Part M8, M9, M10 are constituted, and device M8, M9, M10 use NMOS tube.
Further, described adjustable resistance R1, R2, R4, R8, R16, R32, R64 are according to device MR1～MR7
The dynamically regulation received enables the signal of signal MR1_en～MR7_en and is combined into different resistance values, thus controls
The grid voltage of device M8, M9, M10 processed, and then control the charging voltage of capacitor charge and discharge circuit；Described device
Part MR1～MR7 uses NMOS tube.
Further, described charging capacitor regulation electricity routing capacitance C1～C8, electric capacity C1 '～C8 ', device MC1～MC4
Constitute with device MC1 '～MC4 '；Device MC1～MC4 and device MC1 '～MC4 ' uses NMOS tube；Described
Electric capacity C1, C2 connect, the drain electrode of MC1 with source electrode respectively two ends with electric capacity C2 be connected；Described electric capacity C3,
C4 connects, the drain electrode of MC2 with source electrode respectively two ends with electric capacity C4 be connected；Described electric capacity C5, C6 connect,
The drain electrode of MC3 with source electrode respectively two ends with electric capacity C6 be connected；Described electric capacity C7, C8 connect, the leakage of MC4
Pole with source electrode respectively two ends with electric capacity C8 be connected；Described electric capacity C1 ', C2 ' connect, the drain electrode of MC1 '
Two ends with electric capacity C2 ' are connected respectively with source electrode；Described electric capacity C3 ', C4 ' connect, the drain electrode of MC2 '
Two ends with electric capacity C4 ' are connected respectively with source electrode；Described electric capacity C5 ', C6 ' connect, the drain electrode of MC3 '
Two ends with electric capacity C6 ' are connected respectively with source electrode；Described electric capacity C7 ', C8 ' connect, the drain electrode of MC4 '
Two ends with electric capacity C8 ' are connected respectively with source electrode；Electric capacity C1, C3, C5, C7 intersect at the source electrode of device M9；
Electric capacity C1 ', C3 ', C5 ', C7 ' intersect at the source electrode of device M10；Device
MC1～MC4, MC1 '～MC4 ': control whether electric capacity accesses circuit or bypass as switch pipe.
The clock that resistance R1, R2, R4, R8, R16, R32, R64 in charged electrical voltage regulator circuit are corresponding is adjusted
Joint stepping is respectively 0.005MHZ, 0.01MHZ, 0.02MHZ, 0.04MHZ, 0.08MHZ, 0.16MHZ, 0.32MHZ,
0.64MHZ.Resistance R1, R2, R4, R8 is regulated by Digital Logic dynamically enabling MR1_en～MR7_en, R16,
R32, R64 access the size of the resistance value of circuit, thus have adjusted the grid voltage of device M8, M9, M10,
Thus have adjusted the frequency of clock.
Charging capacitor regulation circuit regulates electric capacity C1～C8 by Digital Logic dynamically enabling C12_en～C78_en
And the size of the capacitance of C1 '～C8 ' access circuit, thus have adjusted the frequency of clock.
Further, digital circuit clock dynamically regulates the clock that logic D1 provides according to label chip analog portion
With the order that reader is sent to label, Digital Logic content uses the algorithm that clock dynamically regulates, it is achieved to electricity
Resistance R1, the dynamically enabling regulation of R2, R4, R8, R16, R32, R64, thus have adjusted the resistance value accessing circuit,
Finally realize the regulation to clock frequency；Digital circuit clock dynamically regulates logic D2 and simulates according to label chip
The clock of part offer and reader are sent to the order of label, and Digital Logic content uses clock dynamically to regulate
Algorithm, it is achieved the dynamically enabling of electric capacity C1～C8, C1 '～C8 ' is regulated, thus have adjusted the electricity accessing circuit
Resistance, finally realizes the regulation to clock frequency；Digital circuit clock dynamically regulates logic D1 and digital circuit
Clock dynamically regulates logic D2 and output and the input of clock alignment modular circuit is connected, and defines one
Loop.What so clock circuit can be real-time knows that on this circuit, the clock frequency in a moment is how many, if
Frequency departure is beyond the scope of regulation, then digital circuit clock dynamically regulates logic D1 and numeral circuit clock
The charging current of the regulation clock circuit that dynamically regulation logic D2 can be real-time, and then clock frequency when have adjusted
Rate.So so that the clock frequency frequency below total temperature scope, all process corner of clock circuit output
Rate value deviation is the least, and clock is highly stable, shakes the least, when providing accurately for the late-class circuit of chip
Clock, improves the success rate that communicates of chip and reader.
In sum, owing to have employed technique scheme, the invention has the beneficial effects as follows:
1, the circuit ring oscillator structure of the present invention is simple, chip occupying area is little, low in energy consumption, and
Can be realized by CMOS technology, but traditional ring oscillator (odd level phase inverter can realize)
Power-supply fluctuation, variations in temperature there are not rejection ability, and output frequency deviation is bigger, it is impossible to for numeral
The reliable clock frequency of circuit with stable.
2, the agitator of the present invention, and traditional oscillators has been done the biggest improvement, weaken supply voltage
With the electric current impact on output clock frequency, reduce the shake of clock frequency so that output frequency
More stable.Relaxation osillator is a kind of agitator using capacitor charge and discharge to realize delay, defeated
The clock frequency gone out is supplied to digital baseband circuit, for demodulating the order sent in reader,
And provide a clock accurately for modulated signal.
3, the clock calibration techniques that the present invention uses so that clock circuit is at any operating temperature point, any
Under process deviation, the frequency deviation of clock of output, all within 3%, fully meets clock circuit
Design requirement.The label chip using this clock circuit is permissible with the success rate that communicates of reader
Reach 100%, i.e. reader can obtain label chip to the operation each time of label chip
Correct response.
Accompanying drawing explanation
Examples of the present invention will be described by way of reference to the accompanying drawings, wherein:
Fig. 1 is the clock circuit block diagram of prior art；
Fig. 2 is the clock circuit schematic diagram of prior art；
Fig. 3 is the clock correcting method block diagram of the present invention；
Fig. 4 is the dynamic clock calibration steps circuit diagram of the present invention.
Detailed description of the invention
All features disclosed in this specification, or disclosed all methods or during step, except mutually
Beyond the feature repelled and/or step, all can combine by any way.
Any feature disclosed in this specification (including any accessory claim, summary and accompanying drawing), unless
Especially narration, all can be by other equivalences or have the alternative features of similar purpose and replaced.That is, unless especially
Narration, each feature is an example in a series of equivalence or similar characteristics.
As it is shown on figure 3, relate to a kind of clock dynamic calibration method based on UHF RFID chip, control electric current
The size of capacitor charge and discharge electric current in control agitator, thus control the length of capacitor charge and discharge time, control
The frequency of output clock；Clock alignment uses the mode of correcting current, by baseband processor according to the letter of reader
Number clock frequency is carried out dynamic calibration；When clock deviation exceeds certain scope when output, digital baseband returns
One group of data changes the size controlling electric current, changes the frequency of output clock, receives a reader command
Clock repeatedly can be adjusted, with optimum time clockwise reader back emitted when order finishes receiving simultaneously
Signal so that label can be by the most errorless identification.
As shown in Figure 4, a kind of clock dynamic calibration circuit based on UHF RFID chip is disclosed, including electricity
Stream base modules, clock alignment module, oscillator module and digital baseband block；The output of current reference module
End is connected with an input of clock alignment module, and the outfan of clock alignment module is defeated with oscillator module
Entering end to be connected, the outfan of oscillator module is by another input of digital baseband block with clock alignment module
End is connected；Described oscillator module is made up of first, second and third grade of inverter circuit and clock shaping circuit；Institute
State clock alignment module to be made up of charged electrical voltage regulator circuit and charging capacitor regulation circuit；Described digital baseband mould
Block is dynamically regulated logic D1 by digital circuit clock and numeral circuit clock dynamically regulates logic D2 and forms.
Specifically, described current reference module is formed by emitter follower M0, device M1, M2, device M1,
M2, M3 constitute mirror current source, and mirror current source is charging/discharging voltage regulation circuit and first order inverter circuit
Electric current is provided；Device M0 uses NMOS tube, and described device M1, M2, M3 use PMOS.
Specifically, described first order negative circuit is made up of device M4, M5, M6, M7, works in differential mode
Formula, it is achieved electric capacity is replaced discharge and recharge；Described device M4, M6 use PMOS, and device M5, M7 use
NMOS tube.
Specifically, described second and third grade of inverter circuit is made up of trigger RS1, RS2 respectively；Described
Two, the output signal of three grades of inverter circuits is as the input signal of first order negative circuit；First, second and third
Level inverter circuit constitutes annular oscillation circuit.
Specifically, described clock shaping circuit is made up of device M11～M16, by the output clock signal side of being shaped to
Ripple signal, and provide certain driving force to drive late-class circuit.
Specifically, described charged electrical voltage regulator circuit by reference current source and adjustable resistance R1, R2, R4, R8,
R16, R32, R64 are constituted, it is achieved the control to capacitor charge and discharge node voltage；Described reference current source is by device
Part M8, M9, M10 are constituted, and device M8, M9, M10 use NMOS tube.
Specifically, described adjustable resistance R1, R2, R4, R8, R16, R32, R64 are according to device MR1～MR7
The dynamically regulation received enables the signal of signal MR1_en～MR7_en and is combined into different resistance values, thus controls
The grid voltage of device M8, M9, M10 processed, and then control the charging voltage of capacitor charge and discharge circuit；Described device
Part MR1～MR7 uses NMOS tube.
Specifically, described charging capacitor regulation electricity routing capacitance C1～C8, electric capacity C1 '～C8 ', device MC1～MC4
Constitute with device MC1 '～MC4 '；Device MC1～MC4 and device MC1 '～MC4 ' uses NMOS tube；Described
Electric capacity C1, C2 connect, the drain electrode of MC1 with source electrode respectively two ends with electric capacity C2 be connected；Described electric capacity C3,
C4 connects, the drain electrode of MC2 with source electrode respectively two ends with electric capacity C4 be connected；Described electric capacity C5, C6 connect,
The drain electrode of MC3 with source electrode respectively two ends with electric capacity C6 be connected；Described electric capacity C7, C8 connect, the leakage of MC4
Pole with source electrode respectively two ends with electric capacity C8 be connected；Described electric capacity C1 ', C2 ' connect, the drain electrode of MC1 '
Two ends with electric capacity C2 ' are connected respectively with source electrode；Described electric capacity C3 ', C4 ' connect, the drain electrode of MC2 '
Two ends with electric capacity C4 ' are connected respectively with source electrode；Described electric capacity C5 ', C6 ' connect, the drain electrode of MC3 '
Two ends with electric capacity C6 ' are connected respectively with source electrode；Described electric capacity C7 ', C8 ' connect, the drain electrode of MC4 '
Two ends with electric capacity C8 ' are connected respectively with source electrode；Electric capacity C1, C3, C5, C7 intersect at the source electrode of device M9；
Electric capacity C1 ', C3 ', C5 ', C7 ' intersect at the source electrode of device M10；Device
MC1～MC4, MC1 '～MC4 ': control whether electric capacity accesses circuit or bypass as switch pipe.
The clock that resistance R1, R2, R4, R8, R16, R32, R64 in charged electrical voltage regulator circuit are corresponding is adjusted
Joint stepping is respectively 0.005MHZ, 0.01MHZ, 0.02MHZ, 0.04MHZ, 0.08MHZ, 0.16MHZ, 0.32MHZ,
0.64MHZ.Resistance R1, R2, R4, R8 is regulated by Digital Logic dynamically enabling MR1_en～MR7_en, R16,
R32, R64 access the size of the resistance value of circuit, thus have adjusted the grid voltage of device M8, M9, M10,
Thus have adjusted the frequency of clock.
Charging capacitor regulation circuit regulates electric capacity C1～C8 by Digital Logic dynamically enabling C12_en～C78_en
And the size of the capacitance of C1 '～C8 ' access circuit, thus have adjusted the frequency of clock.
Specifically, digital circuit clock dynamically regulates the clock that logic D1 provides according to label chip analog portion
With the order that reader is sent to label, Digital Logic content uses the algorithm that clock dynamically regulates, it is achieved to electricity
Resistance R1, the dynamically enabling regulation of R2, R4, R8, R16, R32, R64, thus have adjusted the resistance value accessing circuit,
Finally realize the regulation to clock frequency；Digital circuit clock dynamically regulates logic D2 and simulates according to label chip
The clock of part offer and reader are sent to the order of label, and Digital Logic content uses clock dynamically to regulate
Algorithm, it is achieved the dynamically enabling of electric capacity C1～C8, C1 '～C8 ' is regulated, thus have adjusted the electricity accessing circuit
Capacitance, finally realizes the regulation to clock frequency.
Specifically, digital circuit clock dynamically regulates logic D1 and numeral circuit clock dynamically regulates logic D2 and incites somebody to action
Output and the input of clock alignment modular circuit connect, and define a loop, and such clock circuit is permissible
Real-time knows that on this circuit, the clock frequency in a moment is how many, if frequency departure is beyond the model of regulation
Enclose, then digital circuit clock dynamically regulate logic D1 and numeral circuit clock dynamically regulate logic D2 can be real
Time the charging current of regulation clock circuit, and then have adjusted clock frequency.So so that clock is electric
The clock frequency of road output frequency values deviation below total temperature scope, all process corner is the least, and clock is very
Stable, to shake the least, the late-class circuit for chip provides clock accurately, improves chip and reader
Communication success rate.
Particular embodiments described above, has carried out entering one to the purpose of the present invention, technical scheme and beneficial effect
Step describes in detail, be it should be understood that the specific embodiment that the foregoing is only the present invention, is not used to
Limit the present invention.The present invention expands to any new feature disclosed in this manual or any new combination, with
And the arbitrary new method that discloses or the step of process or any new combination.
Claims (10)
1. a clock dynamic calibration method based on UHF RFID chip, it is characterised in that: control electric current control
The size of capacitor charge and discharge electric current in agitator processed, thus control the length of capacitor charge and discharge time, control defeated
Go out the frequency of clock；Clock alignment uses the mode of correcting current, by baseband processor according to the signal of reader
Clock frequency is carried out dynamic calibration；When clock deviation exceeds certain scope when output, digital baseband returns one
Group data change the size controlling electric current, change the frequency of output clock, receive the same of a reader command
Time clock repeatedly can be adjusted, order when finishing receiving with optimum time clockwise reader back emitted letter
Number so that label can be by the most errorless identification.
2. a clock dynamic calibration circuit based on UHF RFID chip according to claim 1, its
It is characterised by, including current reference module, clock alignment module, oscillator module and digital baseband block；Electricity
The outfan of stream base modules is connected with an input of clock alignment module, the outfan of clock alignment module
Being connected with the input of oscillator module, the outfan of oscillator module passes through digital baseband block and clock alignment
Another input of module is connected；Described oscillator module is by first, second and third grade of inverter circuit and clock
Shaping circuit forms；Described clock alignment module is regulated circuit group by charged electrical voltage regulator circuit and charging capacitor
Become；Described digital baseband block is dynamically regulated logic (resistance adjustment) D1 and digital circuit by digital circuit clock
Clock dynamically regulates logic (capacitance adjustment) D2 composition.
Clock dynamic calibration circuit based on UHF RFID chip the most according to claim 2, its feature
Being, described current reference module is made up of emitter follower M0, device M1, M2, device M1, M2, M3
Constituting mirror current source, mirror current source provides electricity for charging/discharging voltage regulation circuit and first order inverter circuit
Stream；Device M0 uses NMOS tube, and device M1, M2, M3 use PMOS.
4. according to the clock dynamic calibration circuit based on UHF RFID chip described in Claims 2 or 3, its
Being characterised by, described first order negative circuit is made up of device M4, M5, M6, M7, works in difference modes,
Realize electric capacity is replaced discharge and recharge；Described device M4, M6 use PMOS, and device M5, M7 use NMOS
Pipe.
Clock dynamic calibration circuit based on UHF RFID chip the most according to claim 2, its feature
Being, described second and third grade of inverter circuit is made up of trigger RS1, RS2 respectively；Described second and third
The output signal of level inverter circuit is as the input signal of first order negative circuit；First, second and third grade anti-phase
Device circuit constitutes annular oscillation circuit.
Clock dynamic calibration circuit based on UHF RFID chip the most according to claim 2, its feature
Being, described clock shaping circuit is made up of device M11～M16, and output clock signal is shaped to square-wave signal,
And provide certain driving force to drive late-class circuit.
Clock dynamic calibration circuit based on UHF RFID chip the most according to claim 2, its feature
Be, described charging/discharging voltage regulation circuit by reference current source and adjustable resistance R1, R2, R4, R8, R16,
R32, R64 are constituted, it is achieved the control to capacitor charge and discharge node voltage；Described reference current source by device M8,
M9, M10 are constituted, and device M8, M9, M10 use NMOS tube.
Clock dynamic calibration circuit based on UHF RFID chip the most according to claim 7, its feature
Being, described adjustable resistance R1, R2, R4, R8, R16, R32, R64 receive according to device MR1～MR7
Dynamically regulation enable the signal of signal MR1_en～MR7_en and be combined into different resistance values, thus control device
The grid voltage of M8, M9, M10, and then control the charging voltage of capacitor charge and discharge circuit；Described device MR1～MR7
Use NMOS tube.
Clock dynamic calibration circuit based on UHF RFID chip the most according to claim 2, its feature
Be, described charging capacitor regulation electricity routing capacitance C1～C8, electric capacity C1 '～C8 ', device MC1～MC4 and
Device MC1 '～MC4 ' is constituted；Device MC1～MC4 and device MC1 '～MC4 ' uses NMOS tube；Described electricity
Hold C1, C2 series connection, the drain electrode of MC1 with source electrode respectively two ends with electric capacity C2 be connected；Described electric capacity C3, C4
Series connection, the drain electrode of MC2 with source electrode respectively two ends with electric capacity C4 be connected；Described electric capacity C5, C6 connect, MC3
Drain electrode with source electrode respectively two ends with electric capacity C6 be connected；Described electric capacity C7, C8 connect, the drain electrode of MC4 and
Source electrode two ends with electric capacity C8 respectively are connected；Described electric capacity C1 ', C2 ' connect, the drain electrode of MC1 ' and source
Two ends with electric capacity C2 ' respectively, pole are connected；Described electric capacity C3 ', C4 ' connect, the drain electrode of MC2 ' and source
Two ends with electric capacity C4 ' respectively, pole are connected；Described electric capacity C5 ', C6 ' connect, the drain electrode of MC3 ' and source
Two ends with electric capacity C6 ' respectively, pole are connected；Described electric capacity C7 ', C8 ' connect, the drain electrode of MC4 ' and source
Two ends with electric capacity C8 ' respectively, pole are connected；Electric capacity C1, C3, C5, C7 intersect at the source electrode of device M9；Electricity
Hold C1 ', C3 ', C5 ', C7 ' intersect at the source electrode of device M10；Device MC1～MC4, MC1 '～MC4 ':
Control whether electric capacity accesses circuit or bypass as switch pipe.
Clock dynamic calibration circuit based on UHF RFID chip the most according to claim 2, it is special
Levying and be, digital circuit clock dynamically regulates clock that logic D1 provides according to label chip analog portion and reads
Reading device and be sent to the order of label, Digital Logic content uses the algorithm that clock dynamically regulates, it is achieved to resistance
The dynamically enabling regulation of R1, R2, R4, R8, R16, R32, R64, thus have adjusted the resistance value accessing circuit,
Realize the regulation to clock frequency eventually；Digital circuit clock dynamically regulates logic D2 according to label chip simulation part
Dividing the clock provided and reader to be sent to the order of label, Digital Logic content uses the calculation that clock dynamically regulates
Method, it is achieved the dynamically enabling of electric capacity C1～C8, C1 '～C8 ' is regulated, thus have adjusted the resistance accessing circuit
Value, finally realizes the regulation to clock frequency；And described digital circuit clock dynamically regulates logic D1 and numeral
Circuit clock dynamically regulates logic D2 and output and the input of clock alignment modular circuit is connected, and defines
One loop.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610422539.5A CN105958987A (en) | 2016-06-16 | 2016-06-16 | Clock dynamic calibration method and circuit based on UHF RFID chip |
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| CN201610422539.5A CN105958987A (en) | 2016-06-16 | 2016-06-16 | Clock dynamic calibration method and circuit based on UHF RFID chip |
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| CN105958987A true CN105958987A (en) | 2016-09-21 |
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| CN112001470A (en) * | 2019-05-11 | 2020-11-27 | 紫光同芯微电子有限公司 | Frequency self-adaptive circuit of non-contact smart card chip |
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| US20130154806A1 (en) * | 2005-05-06 | 2013-06-20 | Intelleflex Corporation | Accurate Persistent Nodes |
| US9165170B1 (en) * | 2008-03-13 | 2015-10-20 | Impinj, Inc. | RFID tag dynamically adjusting clock frequency |
| CN101727601A (en) * | 2008-11-03 | 2010-06-09 | 上海复旦微电子股份有限公司 | Radio frequency identification tag and method for calibrating clock signals |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108462511A (en) * | 2017-02-16 | 2018-08-28 | 三星电子株式会社 | The operating method of near-field communication equipment and near-field communication equipment |
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Application publication date: 20160921 |