Summary of the invention
In view of this, the present invention provides a kind of shifting deposit unit and its driving method, a kind of shift-register circuit, one
Kind display device.
The present invention provides a kind of shifting deposit units, comprising: input unit, pull-up unit, flow leakage prevention unit, storage are single
Member, coupling unit and output unit;The input unit includes the first control terminal, for responding the first pulse signal, by first
Voltage signal is transmitted to first node, and second voltage signal is transmitted to second node;The pull-up unit includes second
The second voltage signal is transmitted to the first node, and described in response for responding the second pulse signal by control terminal
The first voltage signal is transmitted to the second node by the signal of first node;The flow leakage prevention unit is for responding institute
Second voltage signal is stated, the electric current of the second node is prevented to be transmitted to third node;The storage unit is for keeping described
The current potential of first node;The coupling unit is used to couple the current potential of the third node;The output unit includes input terminal
And the first voltage signal is transmitted to the output end, Huo Zheyong for responding the signal of the first node by output end
In the signal for responding the third node, by clock signal transmission to the output end.
The present invention also provides a kind of driving methods of shifting deposit unit, for driving shift LD provided by the invention
Unit, comprising: at the first moment, the first control terminal of Xiang Suoshu, the input terminal input the first level, the second control terminal of Xiang Suoshu
Input second electrical level;At the second moment, Xiang Suoshu input terminal inputs first level, the first control terminal of Xiang Suoshu, described the
Two control terminals input the second electrical level;At the third moment, the first control terminal of Xiang Suoshu, input terminal input second electricity
Flat, the second control terminal of Xiang Suoshu inputs first level;At the 4th moment, the first control terminal of Xiang Suoshu, second control
End inputs the second electrical level, and Xiang Suoshu input terminal inputs first level.
The present invention also provides a kind of shift-register circuit, including N number of cascade shifting deposit unit provided by the invention,
Wherein, N is the positive integer more than or equal to 2.
The present invention also provides a kind of display device, using shifting deposit unit provided by the invention and provided by the invention
Driving method.
The stability of shift register provided by the invention is good, transmission performance is excellent.In some embodiments of the invention,
Shifting deposit unit provided by the invention uses one species transistor npn npn, it is possible to reduce processing procedure simplifies manufacture craft, improves system
Make efficiency, reduces manufacturing cost, while stability is good, transmission performance is excellent.
Specific embodiment
To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with attached drawing and implementation
The present invention will be further described for example.
It should be noted that elaborating detail in the following description to fully understand the present invention.But this hair
Bright to be different from other way described herein with a variety of and be implemented, those skilled in the art can be without prejudice in the present invention
Similar popularization is done in the case where culvert.Therefore the present invention is not limited by following public specific embodiment.
Referring to FIG. 1, Fig. 1 is the electrical block diagram of one embodiment of shifting deposit unit provided by the invention.
Shifting deposit unit 100, including input unit 10, pull-up unit 20, flow leakage prevention unit 30, storage unit 40, coupling unit 50
With output unit 60;Input unit 10 includes the first control terminal IN, for responding the first pulse signal, by first voltage signal
VGH is transmitted to first node N1, and second voltage signal VGL is transmitted to second node N2;Pull-up unit 20 includes second
Second voltage signal VGL is transmitted to first node N1 for responding the second pulse signal by control terminal NEXT, and response the
First voltage signal VGH is transmitted to second node N2 by the signal of one node N1;Flow leakage prevention unit 30 is for responding second voltage
Signal VGL prevents the electric current of second node N2 to be transmitted to third node N3;Storage unit 40 is used to keep the electricity of first node N1
Position;Coupling unit 50 is used to couple the current potential of third node N3;Output unit 60 includes input terminal CLK and output end OUT, is used for
The signal for responding first node N1, is transmitted to output end OUT for first voltage signal VGH, or for responding third node N3
Signal, by clock signal transmission to output end OUT.
In shifting deposit unit provided in this embodiment, because of the output of the signal control output unit 60 of third node N3
Signal, flow leakage prevention unit 30 can prevent the electric current of second node N2 to be transmitted to third node N3, keep the steady of output unit 60
Fixed output;Coupling unit 50 can couple the current potential of third node N3, and further maintain output unit 60 stablizes output.Cause
The stability of this shift register provided by the invention is good, transmission performance is excellent.
Referring to FIG. 2, Fig. 2 is the circuit structure signal of another embodiment of shifting deposit unit provided by the invention
Figure.In shifting deposit unit 200, input unit 10 includes the first transistor T1 and second transistor T2, wherein the first transistor
The grid of T1 is connected to the first control terminal IN to receive the first pulse signal, and the first pole of the first transistor T1 receives first voltage
The second pole of signal VGH, the first transistor T1 are connected to first node N1;The grid of second transistor T2 is connected to the first control
End IN is to receive the first pulse signal, and the first pole of second transistor T2 receives second voltage signal VGL, second transistor T2's
Second pole is connected to second node N2.
Pull-up unit 20 includes third transistor T3 and the 4th transistor T4, wherein the grid of third transistor T3 connects
To first node N1, the first pole of third transistor T3 receives first voltage signal VGH, the second pole connection of third transistor T3
To second node N2;The grid of 4th transistor T4 is connected to the second control terminal NEXT to receive the second pulse signal, and the 4th is brilliant
The first pole of body pipe T4 receives second voltage signal VGL, and the second pole of the 4th transistor T4 is connected to first node N1.
Flow leakage prevention unit 30 includes the 5th transistor T5, and the grid of the 5th transistor T5 receives second voltage signal VGL, the
The first pole of five transistor T5 is connected to second node N2, and the second pole of the 5th transistor T5 is connected to third node N3.
Storage unit 40 includes first capacitor C1, and the first pole plate of first capacitor C1 receives first voltage signal VGH, and first
The second pole plate of capacitor C1 is connected to first node N1.
Coupling unit 50 includes the second capacitor C2, and the first pole plate of the second capacitor C2 is connected to third node N3, the second electricity
The second pole plate for holding C2 is connected to the output OUT.
Output unit 60 includes the 6th transistor T6 and the 7th transistor T7, wherein the grid of the 6th transistor T6 connects
To first node N1, the first pole of the 6th transistor T6 receives first voltage signal VGH, the second pole connection of the 6th transistor T6
To output end OUT;The grid of 7th transistor T7 is connected to third node N3, and the first pole of the 7th transistor T7 is connected to input
Hold CLK to receive clock signal, the second pole of the 7th transistor T7 is connected to the output OUT.
In shifting deposit unit provided in this embodiment, when third transistor T3 is opened, first voltage signal VGH transmission
To second node N2, the 5th transistor T5 of flow leakage prevention unit 30 can prevent the electric current of second node N2 to be transmitted to third node
N3;Because the signal of third node N3 controls the on and off of the 7th transistor T7 in output unit 60, when the 7th crystal
When pipe T7 is opened, the clock signal transmission of input terminal CLK to output end OUT;Therefore the 5th transistor T5 of flow leakage prevention unit 30
Can keep output unit 60 stablizes output;Second capacitor C2 of coupling unit 50 has coupling, can couple third
The current potential of node N3, the current potential of third node N3 is pulled to lower or higher, and further maintain output unit 60 seven are brilliant
Stablizing for body pipe T7 is on and off, so that stablizing for output unit 60 be kept to export.Therefore shift LD provided by the invention
The stability of device is good, transmission performance is excellent.
According to the difference of the doping way of the channel of transistor, the type of transistor includes P-type transistor or N-type crystal
Pipe.In some optional implementations, in the shifting deposit unit that Fig. 2 embodiment provides, the first transistor T1, the second crystal
Pipe T2, third transistor T3, the 4th transistor T4, the 5th transistor T5, the 6th transistor T6 and the 7th transistor T7 are p-type
Transistor, or be N-type transistor.It should be noted that in the shifting deposit unit that Fig. 2 embodiment provides, only with p-type crystalline substance
Shifting deposit unit provided by the invention is illustrated for body pipe.Shifting deposit unit provided in this embodiment uses same
The transistor of one type, it is possible to reduce processing procedure simplifies manufacture craft, improves producing efficiency, reduces manufacturing cost, while stability
Well, transmission performance is excellent.
In some optional implementations, the voltage of first voltage signal VGH is higher than the electricity of second voltage signal VGL
Pressure.First voltage signal VGH and second voltage signal VGL is a kind of stable direct current signal.
According to the difference for the semiconductor material that transistor uses, the type of transistor includes amorphous silicon (Amorphous
Silicon α-Si) transistor, low temperature polycrystalline silicon (Low Temperature Poly-Silicon) transistor or oxide half
Conductor (Indium Gallium Zinc Oxide) transistor.In some optional implementations, what Fig. 2 embodiment provided
In shifting deposit unit, the first transistor T1, second transistor T2, third transistor T3, the 4th transistor T4, the 5th transistor
T5, the 6th transistor T6 and the 7th transistor T7 be amorphous silicon transistor or be low-temperature polycrystalline silicon transistor or
For oxide semi conductor transistor.
The embodiment of the invention also provides a kind of shift-register circuits comprising above-mentioned shifting deposit unit, please refer to figure
3, Fig. 3 be the structural schematic diagram of one embodiment of shift-register circuit provided by the invention.In shift register 300, packet
Include N number of cascade shifting deposit unit, wherein VSR (1), VSR (2), VSR (3), VSR (4) ..., VSR (N-1), VSR (N) point
It Biao Shi not first order shifting deposit unit, second level shifting deposit unit, third level shifting deposit unit, fourth stage shift LD
Unit ..., (N-1) grade shifting deposit unit and N grades of shifting deposit units.Wherein, N is the positive integer more than or equal to 2.Often
Level-one shifting deposit unit can be the shifting deposit unit in conjunction with described in Fig. 1 or Fig. 2 above.
In some optional implementations, M grades of the second control terminal NEXT is electrically connected M+1 grades of output end OUT,
M grades of the first control terminal IN is electrically connected M-1 grades of output end OUT, and wherein M is positive integer and 2≤M≤N-1.
Referring to FIG. 4, the present invention also provides a kind of driving method of shifting deposit unit, it is provided by the invention for driving
Shifting deposit unit, wherein IN indicates that the signal of the first control terminal IN input, CLK indicate the signal of input terminal CLK input, NEXT
Indicate that the signal inputted to the second control terminal NEXT, OUT indicate the signal of output end OUT output, driving provided in this embodiment
Method includes: to input the first level to the first control terminal IN at the first moment I, defeated to the second control terminal NEXT, input terminal CLK
Enter second electrical level;At the second moment II, the first level is inputted to input terminal CLK, to the first control terminal IN, the second control terminal NEXT
Input second electrical level;At the third moment III, second electrical level is inputted to the first control terminal IN, input terminal CLK, to the second control terminal
NEXT inputs the first level;At the 4th moment IV, second electrical level is inputted to the first control terminal IN, the second control terminal NEXT, to defeated
Enter to hold CLK to input the first level.In the present embodiment, using the first level as low level, second electrical level be high level for, to this hair
The driving method of the shifting deposit unit of bright offer is illustrated;In other embodiments of the invention, the first level can be
High level, second electrical level can be low level.
It is below P-type transistor, first voltage signal VGH with the transistor in shifting deposit unit provided by the invention
For for high voltage, second voltage signal VGL is low-voltage, and the first level is low level, second electrical level is high level, to this
The driving method for inventing a kind of shifting deposit unit provided is described in detail.Incorporated by reference to reference Fig. 2 and Fig. 4:
At the first moment I, to the second control terminal NEXT input high level, the 4th transistor T4 is closed;To the first control terminal
IN input low level, the first transistor T1 and second transistor T2 are opened, and the first transistor T1 transmits first voltage signal VGH
To first node N1, the high potential control third transistor T3 and the 6th transistor T6 of first node N1 is closed at this time;Second is brilliant
Second voltage signal VGL is transmitted to second node N2 by body pipe T2;Second voltage signal VGL controls the 5th transistor T5 and opens,
The low potential of second node N2 is transmitted to third node N3, and the low potential of third node N3 controls the 7th transistor T7 and opens, defeated
The high level for entering to hold CLK to input is transmitted to output end OUT.
At the second moment II, to the first control terminal IN input high level, the first transistor T1 and second transistor T2 are closed,
To the second control terminal NEXT input high level, the 4th transistor T4 is closed;Since the holding of first capacitor C1 acts on, first node
The current potential of N1 is still high potential, and third transistor T3 and the 6th transistor T6 are remained off;At the first moment I, third section
The current potential of point N3 is low potential, and at the second moment II, since the holding of the second capacitor C2 acts on, the current potential of third node N3 is drawn
To lower, therefore the 7th transistor T7 is fully opened, and the low potential stabilization of input terminal CLK input is transmitted to output end OUT.
At the third moment III, to the first control terminal IN input high level, the first transistor T1 and second transistor T2 are closed;
To the second control terminal NEXT input low level, the 4th transistor T4 is opened, and the 4th transistor T4 transmits second voltage signal VGL
It is low potential to first node N1, this moment first node N1, third transistor T3 and the 6th transistor T6 are opened;Third crystal
First voltage signal VGH is transmitted to second node N2 by pipe T3, and second voltage signal VGL controls the 5th transistor T5 and opens, this
The high potential of moment second node N2 is transmitted to third node N3 by the 5th transistor T5, the height electricity of this moment third node N3
Position the 7th transistor T7 of control is closed;First voltage signal VGH is transmitted to output end OUT by the 6th transistor T6.
At the 4th moment IV, to the first control terminal IN input high level, the first transistor T1 and second transistor T2 are closed;
To the second control terminal NEXT input high level, the 4th transistor T4 is closed;Since the holding of first capacitor C1 acts on, first node
The current potential of N1 is still low potential, and third transistor T3 and the 6th transistor T6 are kept open;Due to the guarantor of the second capacitor C2
The effect of holding, the current potential of third node N3 is still high potential, therefore the 7th transistor T7 is closed;6th transistor T6 is by first voltage
Signal VGH is transmitted to output end OUT.
It should be noted that the integrality in order to guarantee signal, in working timing figure shown in Fig. 4, between each level signal
There are certain intervals, it can be to avoid signal input error.It is understood that the interval between each level signal is not necessary, this
It invents without limitation.In the driving method of shifting deposit unit provided in this embodiment, at the first moment I, third node
The current potential of N3 is low potential, and at the second moment II, since the holding of the second capacitor C2 acts on, the current potential of third node N3 is pulled to
It is lower, therefore the 7th transistor T7 is fully opened, the low potential of input terminal CLK input, which can be stablized, is transmitted to output end OUT.The
At two moment II, when third transistor T3 is opened, first voltage signal VGH is transmitted to second node N2, flow leakage prevention unit 30
5th transistor T5 can prevent the electric current of second node N2 to be transmitted to third node N3;Because the signal of third node N3 controls
The 7th transistor T7's in output unit 60 is on and off, when the 7th transistor T7 is opened, the clock letter of input terminal CLK
Number it is transmitted to output end OUT;Therefore the 5th transistor T5 of flow leakage prevention unit 30 can keep stablizing for output unit 60 to export.
The present invention also provides a kind of display device, using shifting deposit unit provided by the invention and provided by the invention
Driving method.Display device provided by the invention may include TV, mobile phone, computer etc..
The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be said that
Specific implementation of the invention is only limited to these instructions.For those of ordinary skill in the art to which the present invention belongs, exist
Under the premise of not departing from present inventive concept, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to of the invention
Protection scope.