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CN105810142B - Shifting deposit unit and its driving method, shift-register circuit, display device - Google Patents

Shifting deposit unit and its driving method, shift-register circuit, display device Download PDF

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Publication number
CN105810142B
CN105810142B CN201610341898.8A CN201610341898A CN105810142B CN 105810142 B CN105810142 B CN 105810142B CN 201610341898 A CN201610341898 A CN 201610341898A CN 105810142 B CN105810142 B CN 105810142B
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China
Prior art keywords
transistor
node
unit
voltage signal
shifting deposit
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CN105810142A (en
Inventor
吴桐
钱栋
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Tianma Microelectronics Co Ltd
Wuhan Tianma Microelectronics Co Ltd
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Tianma Microelectronics Co Ltd
Shanghai Tianma AM OLED Co Ltd
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Shift Register Type Memory (AREA)

Abstract

The present invention describes shifting deposit unit and its driving method, shift-register circuit, display device, and wherein shifting deposit unit includes: input unit, pull-up unit, flow leakage prevention unit, storage unit, coupling unit and output unit;First voltage signal is transmitted to first node by input unit, and second voltage signal is transmitted to second node;Second voltage signal is transmitted to first node by pull-up unit, and first voltage signal is transmitted to second node;Flow leakage prevention unit is for preventing the electric current of second node to be transmitted to third node;Storage unit is used to keep the current potential of first node;Coupling unit is used to couple the current potential of third node;First voltage signal is transmitted to output end by output unit, or by clock signal transmission to output end.Shifting deposit unit provided by the invention uses one species transistor npn npn, and processing step is few, manufacturing cost is lower, while stability is good, transmission performance is excellent.

Description

Shifting deposit unit and its driving method, shift-register circuit, display device
Technical field
The present invention relates to field of display technology, more particularly to a kind of shifting deposit unit and its driving method, Yi Zhongyi Bit register circuit and a kind of display device.
Background technique
In the display panel that the prior art provides, usually shift register is connect with grid line, shift register is to grid Polar curve exports shift signal, so that thin film transistor switch connected to the gate line is connected line by line, and then line by line by data-signal In writing pixel unit, the automatic row scanning of display panel is realized.Shift register is generally cascaded by multiple shifting deposit units It forms.The effect of shifting deposit unit is to export after the single pulse signal of input is shifted the half period.
The shifting deposit unit that the prior art provides is generally using being combined with N-type transistor (NMOS) and P-type transistor (PMOS) complementary metal oxide semiconductor (CMOS:Complementary MOS).But N-type transistor is made simultaneously Both with P-type transistor, production complementary metal oxide semiconductor (CMOS:Complementary MOS) will lead to Processing step is excessive, the higher problem of manufacturing cost.
Summary of the invention
In view of this, the present invention provides a kind of shifting deposit unit and its driving method, a kind of shift-register circuit, one Kind display device.
The present invention provides a kind of shifting deposit units, comprising: input unit, pull-up unit, flow leakage prevention unit, storage are single Member, coupling unit and output unit;The input unit includes the first control terminal, for responding the first pulse signal, by first Voltage signal is transmitted to first node, and second voltage signal is transmitted to second node;The pull-up unit includes second The second voltage signal is transmitted to the first node, and described in response for responding the second pulse signal by control terminal The first voltage signal is transmitted to the second node by the signal of first node;The flow leakage prevention unit is for responding institute Second voltage signal is stated, the electric current of the second node is prevented to be transmitted to third node;The storage unit is for keeping described The current potential of first node;The coupling unit is used to couple the current potential of the third node;The output unit includes input terminal And the first voltage signal is transmitted to the output end, Huo Zheyong for responding the signal of the first node by output end In the signal for responding the third node, by clock signal transmission to the output end.
The present invention also provides a kind of driving methods of shifting deposit unit, for driving shift LD provided by the invention Unit, comprising: at the first moment, the first control terminal of Xiang Suoshu, the input terminal input the first level, the second control terminal of Xiang Suoshu Input second electrical level;At the second moment, Xiang Suoshu input terminal inputs first level, the first control terminal of Xiang Suoshu, described the Two control terminals input the second electrical level;At the third moment, the first control terminal of Xiang Suoshu, input terminal input second electricity Flat, the second control terminal of Xiang Suoshu inputs first level;At the 4th moment, the first control terminal of Xiang Suoshu, second control End inputs the second electrical level, and Xiang Suoshu input terminal inputs first level.
The present invention also provides a kind of shift-register circuit, including N number of cascade shifting deposit unit provided by the invention, Wherein, N is the positive integer more than or equal to 2.
The present invention also provides a kind of display device, using shifting deposit unit provided by the invention and provided by the invention Driving method.
The stability of shift register provided by the invention is good, transmission performance is excellent.In some embodiments of the invention, Shifting deposit unit provided by the invention uses one species transistor npn npn, it is possible to reduce processing procedure simplifies manufacture craft, improves system Make efficiency, reduces manufacturing cost, while stability is good, transmission performance is excellent.
Detailed description of the invention
Fig. 1 is the electrical block diagram of one embodiment of shifting deposit unit provided by the invention;
Fig. 2 is the electrical block diagram of another embodiment of shifting deposit unit provided by the invention;
Fig. 3 is the structural schematic diagram of one embodiment of shift-register circuit provided by the invention;
Fig. 4 is a working timing figure of the circuit structure in embodiment illustrated in fig. 2.
Specific embodiment
To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with attached drawing and implementation The present invention will be further described for example.
It should be noted that elaborating detail in the following description to fully understand the present invention.But this hair Bright to be different from other way described herein with a variety of and be implemented, those skilled in the art can be without prejudice in the present invention Similar popularization is done in the case where culvert.Therefore the present invention is not limited by following public specific embodiment.
Referring to FIG. 1, Fig. 1 is the electrical block diagram of one embodiment of shifting deposit unit provided by the invention. Shifting deposit unit 100, including input unit 10, pull-up unit 20, flow leakage prevention unit 30, storage unit 40, coupling unit 50 With output unit 60;Input unit 10 includes the first control terminal IN, for responding the first pulse signal, by first voltage signal VGH is transmitted to first node N1, and second voltage signal VGL is transmitted to second node N2;Pull-up unit 20 includes second Second voltage signal VGL is transmitted to first node N1 for responding the second pulse signal by control terminal NEXT, and response the First voltage signal VGH is transmitted to second node N2 by the signal of one node N1;Flow leakage prevention unit 30 is for responding second voltage Signal VGL prevents the electric current of second node N2 to be transmitted to third node N3;Storage unit 40 is used to keep the electricity of first node N1 Position;Coupling unit 50 is used to couple the current potential of third node N3;Output unit 60 includes input terminal CLK and output end OUT, is used for The signal for responding first node N1, is transmitted to output end OUT for first voltage signal VGH, or for responding third node N3 Signal, by clock signal transmission to output end OUT.
In shifting deposit unit provided in this embodiment, because of the output of the signal control output unit 60 of third node N3 Signal, flow leakage prevention unit 30 can prevent the electric current of second node N2 to be transmitted to third node N3, keep the steady of output unit 60 Fixed output;Coupling unit 50 can couple the current potential of third node N3, and further maintain output unit 60 stablizes output.Cause The stability of this shift register provided by the invention is good, transmission performance is excellent.
Referring to FIG. 2, Fig. 2 is the circuit structure signal of another embodiment of shifting deposit unit provided by the invention Figure.In shifting deposit unit 200, input unit 10 includes the first transistor T1 and second transistor T2, wherein the first transistor The grid of T1 is connected to the first control terminal IN to receive the first pulse signal, and the first pole of the first transistor T1 receives first voltage The second pole of signal VGH, the first transistor T1 are connected to first node N1;The grid of second transistor T2 is connected to the first control End IN is to receive the first pulse signal, and the first pole of second transistor T2 receives second voltage signal VGL, second transistor T2's Second pole is connected to second node N2.
Pull-up unit 20 includes third transistor T3 and the 4th transistor T4, wherein the grid of third transistor T3 connects To first node N1, the first pole of third transistor T3 receives first voltage signal VGH, the second pole connection of third transistor T3 To second node N2;The grid of 4th transistor T4 is connected to the second control terminal NEXT to receive the second pulse signal, and the 4th is brilliant The first pole of body pipe T4 receives second voltage signal VGL, and the second pole of the 4th transistor T4 is connected to first node N1.
Flow leakage prevention unit 30 includes the 5th transistor T5, and the grid of the 5th transistor T5 receives second voltage signal VGL, the The first pole of five transistor T5 is connected to second node N2, and the second pole of the 5th transistor T5 is connected to third node N3.
Storage unit 40 includes first capacitor C1, and the first pole plate of first capacitor C1 receives first voltage signal VGH, and first The second pole plate of capacitor C1 is connected to first node N1.
Coupling unit 50 includes the second capacitor C2, and the first pole plate of the second capacitor C2 is connected to third node N3, the second electricity The second pole plate for holding C2 is connected to the output OUT.
Output unit 60 includes the 6th transistor T6 and the 7th transistor T7, wherein the grid of the 6th transistor T6 connects To first node N1, the first pole of the 6th transistor T6 receives first voltage signal VGH, the second pole connection of the 6th transistor T6 To output end OUT;The grid of 7th transistor T7 is connected to third node N3, and the first pole of the 7th transistor T7 is connected to input Hold CLK to receive clock signal, the second pole of the 7th transistor T7 is connected to the output OUT.
In shifting deposit unit provided in this embodiment, when third transistor T3 is opened, first voltage signal VGH transmission To second node N2, the 5th transistor T5 of flow leakage prevention unit 30 can prevent the electric current of second node N2 to be transmitted to third node N3;Because the signal of third node N3 controls the on and off of the 7th transistor T7 in output unit 60, when the 7th crystal When pipe T7 is opened, the clock signal transmission of input terminal CLK to output end OUT;Therefore the 5th transistor T5 of flow leakage prevention unit 30 Can keep output unit 60 stablizes output;Second capacitor C2 of coupling unit 50 has coupling, can couple third The current potential of node N3, the current potential of third node N3 is pulled to lower or higher, and further maintain output unit 60 seven are brilliant Stablizing for body pipe T7 is on and off, so that stablizing for output unit 60 be kept to export.Therefore shift LD provided by the invention The stability of device is good, transmission performance is excellent.
According to the difference of the doping way of the channel of transistor, the type of transistor includes P-type transistor or N-type crystal Pipe.In some optional implementations, in the shifting deposit unit that Fig. 2 embodiment provides, the first transistor T1, the second crystal Pipe T2, third transistor T3, the 4th transistor T4, the 5th transistor T5, the 6th transistor T6 and the 7th transistor T7 are p-type Transistor, or be N-type transistor.It should be noted that in the shifting deposit unit that Fig. 2 embodiment provides, only with p-type crystalline substance Shifting deposit unit provided by the invention is illustrated for body pipe.Shifting deposit unit provided in this embodiment uses same The transistor of one type, it is possible to reduce processing procedure simplifies manufacture craft, improves producing efficiency, reduces manufacturing cost, while stability Well, transmission performance is excellent.
In some optional implementations, the voltage of first voltage signal VGH is higher than the electricity of second voltage signal VGL Pressure.First voltage signal VGH and second voltage signal VGL is a kind of stable direct current signal.
According to the difference for the semiconductor material that transistor uses, the type of transistor includes amorphous silicon (Amorphous Silicon α-Si) transistor, low temperature polycrystalline silicon (Low Temperature Poly-Silicon) transistor or oxide half Conductor (Indium Gallium Zinc Oxide) transistor.In some optional implementations, what Fig. 2 embodiment provided In shifting deposit unit, the first transistor T1, second transistor T2, third transistor T3, the 4th transistor T4, the 5th transistor T5, the 6th transistor T6 and the 7th transistor T7 be amorphous silicon transistor or be low-temperature polycrystalline silicon transistor or For oxide semi conductor transistor.
The embodiment of the invention also provides a kind of shift-register circuits comprising above-mentioned shifting deposit unit, please refer to figure 3, Fig. 3 be the structural schematic diagram of one embodiment of shift-register circuit provided by the invention.In shift register 300, packet Include N number of cascade shifting deposit unit, wherein VSR (1), VSR (2), VSR (3), VSR (4) ..., VSR (N-1), VSR (N) point It Biao Shi not first order shifting deposit unit, second level shifting deposit unit, third level shifting deposit unit, fourth stage shift LD Unit ..., (N-1) grade shifting deposit unit and N grades of shifting deposit units.Wherein, N is the positive integer more than or equal to 2.Often Level-one shifting deposit unit can be the shifting deposit unit in conjunction with described in Fig. 1 or Fig. 2 above.
In some optional implementations, M grades of the second control terminal NEXT is electrically connected M+1 grades of output end OUT, M grades of the first control terminal IN is electrically connected M-1 grades of output end OUT, and wherein M is positive integer and 2≤M≤N-1.
Referring to FIG. 4, the present invention also provides a kind of driving method of shifting deposit unit, it is provided by the invention for driving Shifting deposit unit, wherein IN indicates that the signal of the first control terminal IN input, CLK indicate the signal of input terminal CLK input, NEXT Indicate that the signal inputted to the second control terminal NEXT, OUT indicate the signal of output end OUT output, driving provided in this embodiment Method includes: to input the first level to the first control terminal IN at the first moment I, defeated to the second control terminal NEXT, input terminal CLK Enter second electrical level;At the second moment II, the first level is inputted to input terminal CLK, to the first control terminal IN, the second control terminal NEXT Input second electrical level;At the third moment III, second electrical level is inputted to the first control terminal IN, input terminal CLK, to the second control terminal NEXT inputs the first level;At the 4th moment IV, second electrical level is inputted to the first control terminal IN, the second control terminal NEXT, to defeated Enter to hold CLK to input the first level.In the present embodiment, using the first level as low level, second electrical level be high level for, to this hair The driving method of the shifting deposit unit of bright offer is illustrated;In other embodiments of the invention, the first level can be High level, second electrical level can be low level.
It is below P-type transistor, first voltage signal VGH with the transistor in shifting deposit unit provided by the invention For for high voltage, second voltage signal VGL is low-voltage, and the first level is low level, second electrical level is high level, to this The driving method for inventing a kind of shifting deposit unit provided is described in detail.Incorporated by reference to reference Fig. 2 and Fig. 4:
At the first moment I, to the second control terminal NEXT input high level, the 4th transistor T4 is closed;To the first control terminal IN input low level, the first transistor T1 and second transistor T2 are opened, and the first transistor T1 transmits first voltage signal VGH To first node N1, the high potential control third transistor T3 and the 6th transistor T6 of first node N1 is closed at this time;Second is brilliant Second voltage signal VGL is transmitted to second node N2 by body pipe T2;Second voltage signal VGL controls the 5th transistor T5 and opens, The low potential of second node N2 is transmitted to third node N3, and the low potential of third node N3 controls the 7th transistor T7 and opens, defeated The high level for entering to hold CLK to input is transmitted to output end OUT.
At the second moment II, to the first control terminal IN input high level, the first transistor T1 and second transistor T2 are closed, To the second control terminal NEXT input high level, the 4th transistor T4 is closed;Since the holding of first capacitor C1 acts on, first node The current potential of N1 is still high potential, and third transistor T3 and the 6th transistor T6 are remained off;At the first moment I, third section The current potential of point N3 is low potential, and at the second moment II, since the holding of the second capacitor C2 acts on, the current potential of third node N3 is drawn To lower, therefore the 7th transistor T7 is fully opened, and the low potential stabilization of input terminal CLK input is transmitted to output end OUT.
At the third moment III, to the first control terminal IN input high level, the first transistor T1 and second transistor T2 are closed; To the second control terminal NEXT input low level, the 4th transistor T4 is opened, and the 4th transistor T4 transmits second voltage signal VGL It is low potential to first node N1, this moment first node N1, third transistor T3 and the 6th transistor T6 are opened;Third crystal First voltage signal VGH is transmitted to second node N2 by pipe T3, and second voltage signal VGL controls the 5th transistor T5 and opens, this The high potential of moment second node N2 is transmitted to third node N3 by the 5th transistor T5, the height electricity of this moment third node N3 Position the 7th transistor T7 of control is closed;First voltage signal VGH is transmitted to output end OUT by the 6th transistor T6.
At the 4th moment IV, to the first control terminal IN input high level, the first transistor T1 and second transistor T2 are closed; To the second control terminal NEXT input high level, the 4th transistor T4 is closed;Since the holding of first capacitor C1 acts on, first node The current potential of N1 is still low potential, and third transistor T3 and the 6th transistor T6 are kept open;Due to the guarantor of the second capacitor C2 The effect of holding, the current potential of third node N3 is still high potential, therefore the 7th transistor T7 is closed;6th transistor T6 is by first voltage Signal VGH is transmitted to output end OUT.
It should be noted that the integrality in order to guarantee signal, in working timing figure shown in Fig. 4, between each level signal There are certain intervals, it can be to avoid signal input error.It is understood that the interval between each level signal is not necessary, this It invents without limitation.In the driving method of shifting deposit unit provided in this embodiment, at the first moment I, third node The current potential of N3 is low potential, and at the second moment II, since the holding of the second capacitor C2 acts on, the current potential of third node N3 is pulled to It is lower, therefore the 7th transistor T7 is fully opened, the low potential of input terminal CLK input, which can be stablized, is transmitted to output end OUT.The At two moment II, when third transistor T3 is opened, first voltage signal VGH is transmitted to second node N2, flow leakage prevention unit 30 5th transistor T5 can prevent the electric current of second node N2 to be transmitted to third node N3;Because the signal of third node N3 controls The 7th transistor T7's in output unit 60 is on and off, when the 7th transistor T7 is opened, the clock letter of input terminal CLK Number it is transmitted to output end OUT;Therefore the 5th transistor T5 of flow leakage prevention unit 30 can keep stablizing for output unit 60 to export.
The present invention also provides a kind of display device, using shifting deposit unit provided by the invention and provided by the invention Driving method.Display device provided by the invention may include TV, mobile phone, computer etc..
The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be said that Specific implementation of the invention is only limited to these instructions.For those of ordinary skill in the art to which the present invention belongs, exist Under the premise of not departing from present inventive concept, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to of the invention Protection scope.

Claims (12)

1. a kind of shifting deposit unit characterized by comprising
Input unit, pull-up unit, flow leakage prevention unit, storage unit, coupling unit and output unit;
The input unit includes the first control terminal, and for the first pulse signal of response, first voltage signal is transmitted to first Node, and second voltage signal is transmitted to second node;
The pull-up unit includes that the second voltage signal is transmitted to by the second control terminal for responding the second pulse signal The first node, and the signal of the response first node, are transmitted to the second node for the first voltage signal;
The flow leakage prevention unit prevents the electric current of the second node to be transmitted to third section for responding the second voltage signal Point;
The storage unit is used to keep the current potential of the first node;
The coupling unit is used to couple the current potential of the third node;
The output unit includes input terminal and output end, for responding the signal of the first node, by the first voltage Signal is transmitted to the output end, or the signal for responding the third node, by clock signal transmission to the output End;
Wherein, second control terminal is electrically connected with the output end of shifting deposit unit described in next stage, the second pulse letter Number for shifting deposit unit described in next stage output signal;
The input unit includes the first transistor and second transistor, wherein
The grid of the first transistor is connected to first control terminal to receive first pulse signal, and described first is brilliant First pole of body pipe receives the first voltage signal, and the second pole of the first transistor is connected to the first node;
The grid of the second transistor is connected to first control terminal to receive first pulse signal, and described second is brilliant First pole of body pipe receives the second voltage signal, and the second pole of the second transistor is connected to the second node;
The pull-up unit includes third transistor and the 4th transistor, wherein
The grid of the third transistor is connected to the first node, and the first pole of the third transistor receives described first Second pole of voltage signal, the third transistor is connected to the second node;
The grid of 4th transistor is connected to second control terminal to receive second pulse signal, and the described 4th is brilliant First pole of body pipe receives the second voltage signal, and the second pole of the 4th transistor is connected to the first node.
2. shifting deposit unit as described in claim 1, which is characterized in that the flow leakage prevention unit includes the 5th transistor, The grid of 5th transistor receives the second voltage signal, and the first pole of the 5th transistor is connected to described second Second pole of node, the 5th transistor is connected to the third node.
3. shifting deposit unit as claimed in claim 2, which is characterized in that the storage unit includes first capacitor, described First pole plate of first capacitor receives the first voltage signal, and the second pole plate of the first capacitor is connected to the first segment Point.
4. shifting deposit unit as claimed in claim 3, which is characterized in that the coupling unit includes the second capacitor, described First pole plate of the second capacitor is connected to the third node, and the second pole plate of second capacitor is connected to the output end.
5. shifting deposit unit as claimed in claim 4, which is characterized in that the output unit includes the 6th transistor and the Seven transistors, wherein
The grid of 6th transistor is connected to the first node, and the first pole of the 6th transistor receives described first Second pole of voltage signal, the 6th transistor is connected to the output end;
The grid of 7th transistor is connected to the third node, and the first pole of the 7th transistor is connected to described defeated Enter end to receive the clock signal, the second pole of the 7th transistor is connected to the output end.
6. shifting deposit unit as described in claim 1, which is characterized in that the voltage of the first voltage signal is higher than described The voltage of second voltage signal.
7. shifting deposit unit as claimed in claim 5, which is characterized in that the first transistor, the second transistor, The third transistor, the 4th transistor, the 5th transistor, the 6th transistor and the 7th transistor are equal It for P-type transistor, or is N-type transistor.
8. shifting deposit unit as claimed in claim 5, which is characterized in that the first transistor, the second transistor, The third transistor, the 4th transistor, the 5th transistor, the 6th transistor and the 7th transistor are equal For amorphous silicon transistor or it is low-temperature polycrystalline silicon transistor or is oxide semi conductor transistor.
9. a kind of shift-register circuit, which includes that N number of cascade displacement as described in claim 1 is posted Memory cell, wherein N is the positive integer more than or equal to 2.
10. shift-register circuit as claimed in claim 9, which is characterized in that second control of M grades of multiple grades End is electrically connected M+1 grades of the output end, and M grades of first control terminal of the multiple grade is electrically connected M-1 grades The output end, wherein M is positive integer and 2≤M≤N-1.
11. a kind of driving method of shifting deposit unit, for driving such as the described in any item shift LD lists of claim 1-8 Member characterized by comprising
At the first moment, the first control terminal of Xiang Suoshu inputs the first level, the second control terminal of Xiang Suoshu, input terminal input the Two level;
At the second moment, Xiang Suoshu input terminal inputs first level, and the first control terminal of Xiang Suoshu, second control terminal are defeated Enter the second electrical level;
At the third moment, the first control terminal of Xiang Suoshu, the input terminal input the second electrical level, and the second control terminal of Xiang Suoshu is defeated Enter first level;
At the 4th moment, the first control terminal of Xiang Suoshu, second control terminal input the second electrical level, and Xiang Suoshu input terminal is defeated Enter first level.
12. a kind of display device, using as described in the described in any item shifting deposit units of claim 1-8 and claim 11 Shifting deposit unit driving method.
CN201610341898.8A 2016-05-20 2016-05-20 Shifting deposit unit and its driving method, shift-register circuit, display device Active CN105810142B (en)

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