CN105719689A - Static random access memory capable of improving writing capacity of storage units as well as write operation method of static random access memory - Google Patents
Static random access memory capable of improving writing capacity of storage units as well as write operation method of static random access memory Download PDFInfo
- Publication number
- CN105719689A CN105719689A CN201610202253.6A CN201610202253A CN105719689A CN 105719689 A CN105719689 A CN 105719689A CN 201610202253 A CN201610202253 A CN 201610202253A CN 105719689 A CN105719689 A CN 105719689A
- Authority
- CN
- China
- Prior art keywords
- word
- line
- write
- memory element
- driver
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 13
- 230000003068 static effect Effects 0.000 title abstract 5
- 238000006880 cross-coupling reaction Methods 0.000 claims abstract description 9
- 238000005728 strengthening Methods 0.000 claims description 10
- 238000007667 floating Methods 0.000 claims description 5
- 238000012423 maintenance Methods 0.000 claims description 5
- 230000002708 enhancing effect Effects 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000013500 data storage Methods 0.000 abstract 1
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
Abstract
The invention provides a static random access memory capable of improving writing capacity of storage units as well as a write operation method of the static random access memory. The grounded end of each storage unit is suspended during write operation on the premise that the data storage capacity of the storage units is not affected during keeping operation and reading operation, positive feedback between two cross-coupling phase inverters in each storage unit is broken, and accordingly, the writing capacity of the storage units is improved. The static random access memory comprises a control circuit and pre-decoder, a bit line pre-charger and equalizer, a sense amplifier and write driver, a word line decoder and driver, an NMOS (N-channel metal oxide semiconductor) power source and a storage array. According to the write operation method, during write operation, word line signals of storage units in selected rows in the storage array are drawn high, inverted signals of a write word line are drawn low, the NMOS power source is cut off, virtual ground terminals are suspended, the positive feedback between the two cross-coupling phase inverters used for storage in each storage unit is broken, and the storage units are rewritten; the storage units enter a keeping mode at the falling edge of the word line signals.
Description
Technical field
The present invention relates to SRAM design field, be specially a kind of SRAM strengthening memory element write capability and write operation method thereof.
Background technology
SRAM is as the important memory element in integrated circuit, due to its high-performance, high reliability, the advantage such as low-power consumption is widely used in high-performance calculation device system (CPU), SOC(system on a chip) (SOC), handheld device etc. calculates field.
Along with the continuous evolution of Technology, constantly reducing of dimensions of semiconductor devices, local and overall process deviation, the performance to integrated circuit, the impact that reliability causes is increasing.Meanwhile, the reliability of circuit is also proposed bigger challenge by constantly declining of supply voltage.The write capability of SRAM memory element, refers to when write operation, and when wordline is opened, write driver drives bit line to rewrite the ability of memory element.
Such as the memory element design principle figure that Figure of description 2, Fig. 2 is traditional.This memory element 200 is made up of four transistors, respectively first and second NMOS transfer tube 205,206, first and second pulldown NMOS transistor 201,202 and first and second pullup PMOS transistor 203,204.Wordline 115 connects the grid end of first and second NMOS transfer tube 205,206.Bit line 220 connects the source of a NMOS transfer tube 205.Bit line anti-221 connects the source of the 2nd NMOS transfer tube 206.Memory cell data 222 connects the drain terminal of first pulldown NMOS transistor the 201, the 2nd NMOS transfer tube the 205, first pullup PMOS transistor 203；Connect the grid end of second pulldown NMOS transistor the 202, second pullup PMOS transistor 204.Memory cell data anti-223 connects the drain terminal of second pulldown NMOS transistor the 202, second pullup PMOS transistor 204；Connect the grid end of first pulldown NMOS transistor the 201, first pullup PMOS transistor 203.Supply voltage 224 connects the source of first and second pullup PMOS transistor 203,204.Ground 225 connects the source of first and second pulldown NMOS transistor 201,202.
Source ground connection due to first and second pulldown NMOS transistor 201,202, the cross-linked phase inverter being made up of first and second pulldown NMOS transistor 201,202 and first and second pullup PMOS transistor 205,206 joins end to end and forms positive feedback, is therefore difficult to be written over.When write operation, first or two NMOS transfer tube 205/206 must be better than first and second pullup PMOS transistor 203/204, data 222 and the data anti-223 of memory element 200 could be rewritten.Along with the decline of supply voltage, and the threshold voltage variation of transistor that process deviation causes is increasing, rewrites memory element more and more difficult.Under some technique and voltage conditions, write operation failure can be caused, thus reducing the yield of whole memorizer.
Therefore, when not affecting maintenance and read operation under the premise of the ability of storage unit stores data, when write operation, strengthen memory element write capability, be very helpful for improving the yield of whole memorizer.
Summary of the invention
For problems of the prior art, the present invention provides a kind of SRAM strengthening memory element write capability and write operation method thereof, when not affecting maintenance and read operation under the premise of the ability of storage unit stores data, by when write operation by memory element earth terminal floating, interrupt the positive feedback between two cross coupling inverters in memory element, thus improving the write capability of memory element.
The present invention is achieved through the following technical solutions:
A kind of SRAM strengthening memory element write capability, including control circuit and Pre-decoder, bit line precharge and equalizer, sense amplifier and write driver, word-line decoder and driver, NMOS current source, storage array；Control circuit is connected word-line decoder and driver with decoder by the locally-written enable inverted signal of a plurality of row pre-decode and；Control circuit is connected bit line precharge and equalizer, sense amplifier and write driver with decoder also by a plurality of row control signal；The input link address signal of control circuit and decoder, write enable signal is anti-, chip selection signal is anti-and clock signal；Bit line precharge is connected with the input/output terminal of equalizer, sense amplifier and write driver to be write data and reads data；Word-line decoder is connected storage array with driver by a plurality of word-line signal, and word-line decoder is connected NMOS current source with driver also by a plurality of write word line inverted signal；NMOS current source connects storage array by a plurality of virtual earth；Storage array connects bit line precharge and equalizer, sense amplifier and write driver by multiple bit lines.
Preferably, storage array is made up of several memory element, and the quantity of memory element is multiplied by bit wide columns equal to word length line number in memorizer；Wherein memory element is made up of two cross coupling inverters for storing and two NMOS transfer tubes for reading and writing, and the source of the pulldown NMOS transistor in two cross coupling inverters connects virtual earth, and same line storage unit shares a virtual earth.
Preferably, described NMOS current source is made up of several nmos pass transistors, and the quantity of nmos pass transistor is equal to word length number in memorizer；The drain terminal correspondence of each nmos pass transistor connects the virtual earth of a line storage unit, grid termination write word line inverted signal, source ground connection.
Preferably, described word-line decoder and driver, it is made up of several word-line decoders and driver submodule, the quantity of word-line decoder and driver submodule is equal to word length number in memorizer；Described word-line decoder and driver submodule are by word-line decoder submodule, a phase inverter and one two input or door composition；The output word-line signal that the input of phase inverter connects word-line decoder submodule is anti-, and output connects word-line signal；One input of two inputs or door connects locally-written enable inverted signal, and another input connects wordline inverted signal, and output connects write word line inverted signal.
A kind of write operation method of the SRAM strengthening memory element write capability, when write operation, for the memory element in row selected in storage array, word-line signal is drawn high, write word line inverted signal drags down, and NMOS current source turns off, virtual earth floating, the positive feedback being used between two the cross-linked phase inverters stored in memory element is interrupted, and memory element is written over；At the trailing edge of word-line signal, when namely write operation terminates, write word line inverted signal is drawn high, and NMOS current source is opened, and virtual earth is pulled to ground, and memory element enters maintenance pattern.
Preferably, when keeping pattern and read operation, write word line inverted signal is high, and NMOS current source is opened, and virtual earth is pulled to ground.
Compared with prior art, the present invention has following useful technique effect:
Memorizer of the present invention keeps and during read operation under the premise of the ability of storage unit stores data not affecting, by the NMOS current source that is correspondingly arranged with each line storage unit of storage array when write operation by memory element earth terminal floating, interrupt the positive feedback between two cross coupling inverters in memory element, thus improving the write capability of memory element.SRAM the minimum supply voltage of writing of normal operation can be reduced 360 millivolts by the present invention.
Accompanying drawing explanation
Fig. 1 is the SRAM structural schematic block diagram described in present example.
Fig. 2 is memory element design principle structure chart in prior art.
Fig. 3 is the memory element design principle structure chart described in present example.
Fig. 4 is the memory element design principle structure chart that the NMOS current source described in present example and a line share virtual earth.
Fig. 5 is the word-line decoder described in present example and driver design submodule schematic diagram.
Detailed description of the invention
Below in conjunction with specific embodiment, the present invention is described in further detail, and the explanation of the invention is not limited.
As it is shown in figure 1, a kind of SRAM strengthening memory element write capability of the present invention includes, control circuit and Pre-decoder 101, bit line precharge and equalizer, sense amplifier and write driver 102, word-line decoder and driver 103, NMOS current source 104, and storage array 105.
Control circuit is connected word-line decoder and driver 103 with decoder 101 by a plurality of row pre-decode 113 and a locally-written enable inverted signal 114；Control circuit is connected bit line precharge and equalizer, sense amplifier and write driver 102 with decoder 101 also by a plurality of row control signal 112；
Word-line decoder is connected storage array 105 with driver 103 by a plurality of word-line signal 115, and word-line decoder is connected NMOS current source 104 with driver 103 also by a plurality of write word line inverted signal 116；
NMOS current source 104 connects storage array 105 by a plurality of virtual earth 117；
Storage array 105 connects bit line precharge and equalizer, sense amplifier and write driver 102 by multiple bit lines 118.
As it is shown on figure 3, memory element 300 is made up of four transistors, respectively first and second NMOS transfer tube 205,206, first and second pulldown NMOS transistor 201,202 and first and second pullup PMOS transistor 203,204.Wordline 115 connects the grid end of first and second NMOS transfer tube 205,206.Bit line 220 connects the source of a NMOS transfer tube 205.Bit line anti-221 connects the source of the 2nd NMOS transfer tube 206.Memory cell data 222 connects the drain terminal of first pulldown NMOS transistor the 201, the 2nd NMOS transfer tube the 205, first pullup PMOS transistor 203；Connect the grid end of second pulldown NMOS transistor the 202, second pullup PMOS transistor 204.Memory cell data anti-223 connects the drain terminal of second pulldown NMOS transistor the 202, second pullup PMOS transistor 204；Connect the grid end of first pulldown NMOS transistor the 201, first pullup PMOS transistor 203.Supply voltage 224 connects the source of first and second pullup PMOS transistor 203,204.Virtual earth 117 connects the source of first and second pulldown NMOS transistor 201,202.
The phase inverter cross-couplings of first and second pulldown NMOS transistor 201,202 and first and second pullup PMOS transistor 205,206 composition joins end to end, and is responsible for storage memory cell data 222 and memory cell data anti-223.
First and second NMOS transfer tube 205,206 is controlled by wordline 115, is written and read operation by the anti-221 pairs of memory cell data 222 of bit line 220 and bit line and memory cell data anti-223.
As shown in Figure 4, NMOS current source 400 is made up of nmos pass transistor 401, and its drain terminal connects virtual earth 117, grid termination write word line inverted signal 116, source ground connection 225.A line shares the memory element 402 of virtual earth and is made up of memory element 300 in bit wide Fig. 3, and they share same wordline 115 and same virtual earth 117.
When keeping pattern and read operation, write word line inverted signal 116 is high, and in NMOS current source 400, nmos pass transistor 402 is opened, and virtual earth is pulled to ground 117, and now memory element 300 is identical with conventional memory cell 200 in Fig. 2.When write operation, for selected row 402, word-line signal draws high 115, write word line inverted signal drags down 116, in NMOS current source 400, nmos pass transistor 402 turns off, virtual earth floating 117, the positive feedback being responsible between two cross-linked phase inverters of storage in memory element 300 is interrupted, and memory element 300 is easier to be written over.At the trailing edge of word-line signal 115, when namely write operation terminates, anti-116 signals of write word line are drawn high, and in NMOS current source 400, nmos pass transistor 402 is opened, and virtual earth 117 is pulled to ground, and memory element 300 enters maintenance pattern.
As it is shown in figure 5, word-line decoder and driver submodule are made up of word-line decoder submodule 501, phase inverter 502, two input or door 503.The input of phase inverter 502 connects the output word-line signal anti-510 of word-line decoder submodule 501, and output connects wordline 115.One input of two inputs or door connects locally-written enable inverted signal 512, and another input connects wordline inverted signal 510, and output connects write word line inverted signal 116.
When keeping, wordline inverted signal 510 is high, and therefore wordline 115 is low, and write word line inverted signal 116 is high.
When read operation, for decoding invalid word-line decoder submodule 501, wordline inverted signal 510 is high, and therefore wordline 115 is low, and write word line inverted signal 116 is high；For decoding effective word-line decoder submodule 501, wordline inverted signal 510 is low, and therefore wordline 115 is high, and during due to read operation, locally-written enable inverted signal 512 is high, and therefore write word line inverted signal 116 is high.
When write operation, for decoding invalid word-line decoder submodule 501, wordline inverted signal 510 is high, and therefore wordline 115 is low, and write word line inverted signal 116 is high；For decoding effective word-line decoder submodule 501, wordline inverted signal 510 is low, and therefore wordline 115 is high, and during due to read operation, locally-written enable inverted signal 512 is low, and therefore write word line inverted signal 116 is low.
When write operation terminates, wordline inverted signal 510 is drawn high, and therefore wordline 115 is low, and write word line inverted signal 116 is high.
Claims (6)
1. the SRAM strengthening memory element write capability, it is characterized in that, including control circuit and Pre-decoder (101), bit line precharge and equalizer, sense amplifier and write driver (102), word-line decoder and driver (103), NMOS current source (104), storage array (105)；
Control circuit is connected word-line decoder and driver (103) with decoder (101) by the locally-written enable inverted signal (114) of a plurality of row pre-decode (113) and；Control circuit is connected bit line precharge and equalizer, sense amplifier and write driver (102) with decoder (101) also by a plurality of row control signal (112)；The input link address signal of control circuit and decoder (101), write enable signal is anti-, chip selection signal is anti-and clock signal (110)；
Bit line precharge is connected with the input/output terminal of equalizer, sense amplifier and write driver (102) to be write data and reads data (111)；
Word-line decoder is connected storage array (105) with driver (103) by a plurality of word-line signal (115), and word-line decoder is connected NMOS current source (104) with driver (103) also by a plurality of write word line inverted signal (116)；
NMOS current source (104) connects storage array (105) by a plurality of virtual earth (117)；
Storage array (105) connects bit line precharge and equalizer, sense amplifier and write driver (102) by multiple bit lines (118).
2. a kind of SRAM strengthening memory element write capability according to claim 1, it is characterized in that, storage array (105) is made up of several memory element (300), and the quantity of memory element is multiplied by bit wide columns equal to word length line number in memorizer；Wherein memory element (300) is made up of two cross coupling inverters for storing and two NMOS transfer tubes for reading and writing, the source of the pulldown NMOS transistor in two cross coupling inverters connects virtual earth (117), and same line storage unit (300) shares a virtual earth (117).
3. a kind of SRAM strengthening memory element write capability according to claim 1, it is characterised in that described NMOS current source (104) is made up of several nmos pass transistors, the quantity of nmos pass transistor is equal to word length number in memorizer；The drain terminal correspondence of each nmos pass transistor connects the virtual earth (117) of a line storage unit (300), grid termination write word line inverted signal (116), source ground connection.
4. a kind of SRAM strengthening memory element write capability according to claim 1, it is characterized in that, described word-line decoder and driver (103), being made up of several word-line decoders and driver submodule (500), the quantity of word-line decoder and driver submodule (500) is equal to word length number in memorizer；Described word-line decoder and driver submodule (500) are by word-line decoder submodule (501), a phase inverter (502) and one two input or door (503) composition；The input of phase inverter (502) connects the output word-line signal anti-(510) of word-line decoder submodule (501), and output connects word-line signal (115)；One input of two inputs or door (503) connects locally-written enable inverted signal (114), and another input connects wordline inverted signal (510), and output connects write word line inverted signal (116).
5. the write operation method of the SRAM of an enhancing memory element write capability as claimed in claim 1, it is characterized in that, when write operation, for the memory element (300) in row selected in storage array (105), word-line signal (115) is drawn high, write word line inverted signal (116) drags down, NMOS current source (104) turns off, virtual earth (117) floating, the positive feedback being used between two the cross-linked phase inverters stored in memory element (300) is interrupted, and memory element (300) is written over；At the trailing edge of word-line signal, when namely write operation terminates, write word line inverted signal (116) is drawn high, and NMOS current source (104) is opened, and virtual earth (117) is pulled to ground, and memory element enters maintenance pattern.
6. write operation method according to claim 5, it is characterised in that when keeping pattern and read operation, write word line inverted signal (116) is high, and NMOS current source (104) is opened, and virtual earth (117) is pulled to ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610202253.6A CN105719689A (en) | 2016-03-31 | 2016-03-31 | Static random access memory capable of improving writing capacity of storage units as well as write operation method of static random access memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610202253.6A CN105719689A (en) | 2016-03-31 | 2016-03-31 | Static random access memory capable of improving writing capacity of storage units as well as write operation method of static random access memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105719689A true CN105719689A (en) | 2016-06-29 |
Family
ID=56160618
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610202253.6A Pending CN105719689A (en) | 2016-03-31 | 2016-03-31 | Static random access memory capable of improving writing capacity of storage units as well as write operation method of static random access memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105719689A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108735258A (en) * | 2017-04-24 | 2018-11-02 | 中芯国际集成电路制造(上海)有限公司 | Address decoder circuit |
| CN110364203A (en) * | 2019-06-20 | 2019-10-22 | 中山大学 | A storage system and calculation method supporting in-storage calculation |
| CN112863567A (en) * | 2021-03-10 | 2021-05-28 | 中电海康无锡科技有限公司 | Write circuit for STT-MRAM |
| CN114373492A (en) * | 2020-10-15 | 2022-04-19 | 意法半导体国际有限公司 | Apparatus and method for reading data from memory cells |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5986923A (en) * | 1998-05-06 | 1999-11-16 | Hewlett-Packard Company | Method and apparatus for improving read/write stability of a single-port SRAM cell |
| US20030090928A1 (en) * | 2001-11-09 | 2003-05-15 | Takashi Takemura | Semiconductor memory device |
| CN102137534A (en) * | 2011-01-26 | 2011-07-27 | 深圳茂硕电源科技股份有限公司 | Virtual ground type high-voltage constant-current circuit |
| CN103886896A (en) * | 2014-03-31 | 2014-06-25 | 西安华芯半导体有限公司 | Static random access memory for reducing writing power consumption by adopting static writing technology |
| CN205487356U (en) * | 2016-03-31 | 2016-08-17 | 西安紫光国芯半导体有限公司 | Reinforcing memory cell writes static RAM of ability |
-
2016
- 2016-03-31 CN CN201610202253.6A patent/CN105719689A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5986923A (en) * | 1998-05-06 | 1999-11-16 | Hewlett-Packard Company | Method and apparatus for improving read/write stability of a single-port SRAM cell |
| US20030090928A1 (en) * | 2001-11-09 | 2003-05-15 | Takashi Takemura | Semiconductor memory device |
| CN102137534A (en) * | 2011-01-26 | 2011-07-27 | 深圳茂硕电源科技股份有限公司 | Virtual ground type high-voltage constant-current circuit |
| CN103886896A (en) * | 2014-03-31 | 2014-06-25 | 西安华芯半导体有限公司 | Static random access memory for reducing writing power consumption by adopting static writing technology |
| CN205487356U (en) * | 2016-03-31 | 2016-08-17 | 西安紫光国芯半导体有限公司 | Reinforcing memory cell writes static RAM of ability |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108735258A (en) * | 2017-04-24 | 2018-11-02 | 中芯国际集成电路制造(上海)有限公司 | Address decoder circuit |
| CN108735258B (en) * | 2017-04-24 | 2020-10-09 | 中芯国际集成电路制造(上海)有限公司 | Address decoder circuit |
| CN110364203A (en) * | 2019-06-20 | 2019-10-22 | 中山大学 | A storage system and calculation method supporting in-storage calculation |
| CN114373492A (en) * | 2020-10-15 | 2022-04-19 | 意法半导体国际有限公司 | Apparatus and method for reading data from memory cells |
| CN112863567A (en) * | 2021-03-10 | 2021-05-28 | 中电海康无锡科技有限公司 | Write circuit for STT-MRAM |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10789998B2 (en) | Memory bank signal coupling buffer and method | |
| CN101582292B (en) | Memory circuit and method of operating the memory circuit | |
| US10867681B2 (en) | SRAM memory having subarrays with common IO block | |
| EP3304555B1 (en) | Low-power row-oriented memory write assist circuit | |
| CN102906819B (en) | Semiconductor storage | |
| US9653150B1 (en) | Static random access memory (SRAM) bitcell and memory architecture without a write bitline | |
| US7626878B1 (en) | Active bit line charge keeper | |
| JP2009272023A (en) | Semiconductor memory device | |
| CN105719689A (en) | Static random access memory capable of improving writing capacity of storage units as well as write operation method of static random access memory | |
| JP2004111027A (en) | Multiport sram cell writing circuit and method | |
| CN205487356U (en) | Reinforcing memory cell writes static RAM of ability | |
| US12009055B2 (en) | Far end driver for memory clock | |
| CN102394102B (en) | Close threshold power supply voltage SRAM unit with virtual address structure | |
| CN103886896B (en) | A kind of SRAM using static writing technology reduction to write power consumption | |
| CN102934169B (en) | Semiconductor storage | |
| CN101840728B (en) | Dual-end static random access memory (SRMA) unit | |
| TWI579863B (en) | 7t dual port static random access memory | |
| US7684231B2 (en) | Methods and apparatus for low power SRAM based on stored data | |
| TWI556239B (en) | 7t dual port static random access memory (3) | |
| CN114496023A (en) | Integrated circuit memory device and static random access memory device | |
| TW202119416A (en) | Memory write operation apparatus and method | |
| TWI556410B (en) | 7t dual port static random access memory (8) | |
| TWI573138B (en) | 7t dual port static random access memory (7) | |
| CN120104562A (en) | A high-density two-port buffer technology for system-on-chip | |
| JP2008065863A (en) | Semiconductor memory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20160629 |
|
| WD01 | Invention patent application deemed withdrawn after publication |