CN105633051A - Multi-chip multi-matching tiled sandwiched core package structure with partial framework exposed and process method of structure - Google Patents
Multi-chip multi-matching tiled sandwiched core package structure with partial framework exposed and process method of structure Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 230000008569 process Effects 0.000 title abstract description 16
- 238000004806 packaging method and process Methods 0.000 claims abstract description 40
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 10
- 238000005476 soldering Methods 0.000 claims abstract description 9
- 238000003825 pressing Methods 0.000 claims abstract description 8
- 239000011248 coating agent Substances 0.000 claims abstract description 7
- 238000000576 coating method Methods 0.000 claims abstract description 7
- 238000005520 cutting process Methods 0.000 claims abstract description 6
- 239000007943 implant Substances 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims description 31
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 19
- 229910052802 copper Inorganic materials 0.000 claims description 19
- 239000010949 copper Substances 0.000 claims description 19
- 238000005538 encapsulation Methods 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 6
- 238000007650 screen-printing Methods 0.000 claims description 6
- 230000005405 multipole Effects 0.000 claims description 3
- 239000004568 cement Substances 0.000 claims 5
- 239000006071 cream Substances 0.000 claims 5
- 238000003672 processing method Methods 0.000 claims 5
- JRBRVDCKNXZZGH-UHFFFAOYSA-N alumane;copper Chemical compound [AlH3].[Cu] JRBRVDCKNXZZGH-UHFFFAOYSA-N 0.000 claims 1
- TVZPLCNGKSPOJA-UHFFFAOYSA-N copper zinc Chemical compound [Cu].[Zn] TVZPLCNGKSPOJA-UHFFFAOYSA-N 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 abstract description 19
- 230000017525 heat dissipation Effects 0.000 abstract description 11
- 238000004519 manufacturing process Methods 0.000 abstract description 10
- 238000004080 punching Methods 0.000 abstract description 3
- 238000007789 sealing Methods 0.000 abstract description 2
- 230000009286 beneficial effect Effects 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 description 25
- 239000002184 metal Substances 0.000 description 25
- 239000000047 product Substances 0.000 description 15
- 238000000465 moulding Methods 0.000 description 7
- QBWKPGNFQQJGFY-QLFBSQMISA-N 3-[(1r)-1-[(2r,6s)-2,6-dimethylmorpholin-4-yl]ethyl]-n-[6-methyl-3-(1h-pyrazol-4-yl)imidazo[1,2-a]pyrazin-8-yl]-1,2-thiazol-5-amine Chemical compound N1([C@H](C)C2=NSC(NC=3C4=NC=C(N4C=C(C)N=3)C3=CNN=C3)=C2)C[C@H](C)O[C@H](C)C1 QBWKPGNFQQJGFY-QLFBSQMISA-N 0.000 description 4
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229940125846 compound 25 Drugs 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 239000008393 encapsulating agent Substances 0.000 description 4
- 238000012536 packaging technology Methods 0.000 description 4
- 238000003466 welding Methods 0.000 description 4
- 229910000952 Be alloy Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000005022 packaging material Substances 0.000 description 2
- 239000011265 semifinished product Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000009833 condensation Methods 0.000 description 1
- 230000005494 condensation Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000009192 sprinting Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
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- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/37124—Aluminium [Al] as principal constituent
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- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
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- H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/37147—Copper [Cu] as principal constituent
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- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/3754—Coating
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Abstract
本发明涉及一种部分框架外露多芯片多搭平铺夹芯封装结构及其工艺方法，所述方法包括以下步骤：步骤一、提供第一引线框；步骤二、在第一引线框涂覆锡膏；步骤三，在步骤二中第一引线框基岛区域涂覆的锡膏上植入第一芯片和第二芯片；步骤四，提供第二引线框，在第二引线框上涂覆锡膏；步骤五，将第二引线框压合在第一引线框上表面的第一芯片和第二芯片上，压合后第一引线框和第二引线框形成整体框架；步骤六，将步骤五形成的整体框架上下表面用压板压住，进行回流焊；步骤七，塑封料塑封；步骤八，切割或冲切作业。本发明的有益效果是：增加产品热消散的能力，降低产品的封装电阻。且整条产品可一体成型，生产效率高。
The present invention relates to a multi-chip and multi-lap tiled sandwich packaging structure with part of the frame exposed and a process method thereof. The method comprises the following steps: step 1, providing a first lead frame; step 2, coating tin on the first lead frame paste; Step 3, implant the first chip and the second chip on the solder paste coated in the base island area of the first lead frame in step 2; Step 4, provide a second lead frame, and coat tin on the second lead frame Paste; step five, press the second lead frame on the first chip and the second chip on the upper surface of the first lead frame, after pressing, the first lead frame and the second lead frame form an integral frame; step six, press the step Step 5: Press the upper and lower surfaces of the formed overall frame with a pressure plate, and perform reflow soldering; Step 7, Plastic sealing; Step 8, Cutting or punching operation. The invention has the beneficial effects of increasing the heat dissipation capability of the product and reducing the packaging resistance of the product. And the whole product can be integrally formed, and the production efficiency is high.
Description
技术领域 technical field
本发明涉及一种部分框架外露多芯片多搭平铺夹芯封装结构及其工艺方法，属于半导体封装技术领域。 The invention relates to a partially frame-exposed multi-chip multi-lapping sandwich packaging structure and a process method thereof, belonging to the technical field of semiconductor packaging.
背景技术 Background technique
近年来，随着电子产品对功率密度不断的追求，无论是Diode（二级管）还是Transistor（三极管）的封装，尤其是Transistor中的MOS产品正朝着更大功率、更小尺寸、更快速、散热更好的趋势在发展。封装的一次性制造方式也由单颗封装技术慢慢朝向小区域甚至更大区域的高密度高难度低成本一次性封装技术冲刺与挑战。 In recent years, with the continuous pursuit of power density in electronic products, whether it is Diode (secondary tube) or Transistor (transistor) packaging, especially the MOS products in Transistor are moving towards higher power, smaller size, faster , The trend of better heat dissipation is developing. The one-time manufacturing method of packaging is also gradually sprinting and challenging from single-chip packaging technology to high-density, high-difficulty and low-cost one-time packaging technology in small areas or even larger areas.
因此，也对MOS产品的封装在寄生的电阻、电容、电感等的各种电性能、封装的结构、封装的热消散性能力、封装的信赖性方面以及高难度一次性封装技术方面有了更多的要求。 Therefore, the packaging of MOS products has been improved in terms of various electrical properties such as parasitic resistance, capacitance, and inductance, packaging structure, heat dissipation capability of packaging, reliability of packaging, and high-difficulty one-time packaging technology. much request.
传统的Diode（二级管）以及Transistor（三极管）或是MOS产品的封装一般依据产品特性、功率的不同以及成本的考虑因素，利用了金线、银合金线、铜线、铝线以及铝带的焊线方式作为芯片与内引脚的主要的互联技术，从而实现电气连接。然而焊线的技术方式对产品的性能存在了以下几个方面的限制与缺陷： Traditional Diode (secondary tube) and Transistor (transistor) or MOS product packages generally use gold wires, silver alloy wires, copper wires, aluminum wires, and aluminum strips based on product characteristics, power differences, and cost considerations. The wire bonding method is used as the main interconnection technology between the chip and the internal pins, so as to realize the electrical connection. However, the technical method of welding wire has the following limitations and defects on the performance of the product:
一、封装与制造方面的限制与缺陷： 1. Limitations and defects in packaging and manufacturing:
1）、焊接能力（Bondability）方面：常常会因为金属丝材料、金属引脚材料的变化以及设备与工具的参数片变化、性能与精度的变化以及保养与校正管理而造成的第一焊点以及第二焊点结合面的虚焊、脱落、断点、颈部裂缝、塌线以及短路等种种的困扰，导致了封装良率无法提升、成本无法下降、可靠性的不稳定； 1) In terms of welding ability (Bondability): the first solder joint and the Various troubles such as virtual soldering, peeling, breakpoints, neck cracks, collapsed wires, and short circuits on the joint surface of the second solder joint lead to the inability to increase the packaging yield, the cost cannot be reduced, and the reliability is unstable;
2）、一次性高密度封装技术方面：传统的互联方式几乎都是在矩阵型金属引线框上采用单颗芯片一颗一颗芯片重复进行装片、金属丝采高温超声一根线一根线的焊接方式。而这样情况下无论是专业的装片机、球焊打线机、键合铝线/铝带机或是铜片搭接机等机器设备再高速的重复动作都无法提升生产效率、无法降低单位成本，也因为设备不断的提升生产速度同样的也提升了制造的不稳定性。 2) Disposable high-density packaging technology: the traditional interconnection method is almost always to use a single chip on a matrix metal lead frame to repeatedly mount chips one by one, and use high-temperature ultrasonic wires for metal wires. welding method. In this case, whether it is a professional chip loading machine, a ball bonding machine, a bonding aluminum wire/aluminum strip machine or a copper lap splicing machine, no matter how high-speed and repetitive actions of machinery and equipment can not improve production efficiency, it is impossible to reduce the unit. Cost, but also because the continuous improvement of equipment production speed also increases the instability of manufacturing.
二、封装产品的特性能方面的限制与缺陷： 2. Limitations and defects in the performance of packaged products:
1）、热消散方面：传统的Diode（二级管）以及Transistor（三极管）或是MOS的封装产品，一般都是由塑封料包覆、只留外部引脚暴露在塑封体之外，由于塑封料本身不是一种热导的物质，所以传统的Diode（二级管）以及Transistor（三极管）或是MOS产品在工作时所产生的热量很难通过塑封料消散出塑封料物质的封装体，只能依靠细细的金属丝互联在金属引脚材料来帮助热能的消散，但是这种热消散的途径对热的消散能力是非常有限的，反而形成热消散的阻力； 1) In terms of heat dissipation: traditional Diode (secondary tube) and Transistor (transistor) or MOS package products are generally covered by plastic packaging materials, leaving only the external pins exposed outside the plastic package. The material itself is not a thermally conductive substance, so the heat generated by the traditional Diode (secondary tube) and Transistor (triode) or MOS products is difficult to dissipate through the plastic packaging material. It can rely on thin metal wires interconnected with metal pin materials to help dissipate heat energy, but this way of heat dissipation is very limited in heat dissipation capacity, and instead forms resistance to heat dissipation;
2）、电阻率（Resistivity）方面：大家都知道电阻率（resistivity）是用来表示各种物质电阻特性的物理量。在温度一定的情况下，有公式R=ρl/s其中的ρ就是电阻率，l为材料的长度，s为面积。可以看出，材料的电阻大小正比于材料的长度，而反比于其面积。由上式可知电阻率的定义：ρ=Rs/l。传统的Diode（二级管）以及Transistor（三极管）或是MOS的封装产品，采用焊线形成互联，由此可清楚的知道用来执行电源或是信号的金属丝会因为，导体材料的长度与截面积的变化而影响到电阻率的大小以及接触电阻的损耗，尤其是应用在功率方面的产品影响更是明显。 2), resistivity (Resistivity): We all know that resistivity (resistivity) is a physical quantity used to express the resistance characteristics of various substances. In the case of a certain temperature, there is a formula R=ρl/s where ρ is the resistivity, l is the length of the material, and s is the area. It can be seen that the resistance of a material is proportional to its length and inversely proportional to its area. The definition of resistivity can be known from the above formula: ρ=Rs/l. Traditional Diode (secondary tube) and Transistor (transistor) or MOS packaging products are interconnected by bonding wires, so it is clear that the metal wire used to perform power or signal will be due to the length of the conductor material and The change of cross-sectional area affects the size of resistivity and the loss of contact resistance, especially the impact of products applied in power is more obvious.
为解决上述问题，业界对传统的Diode（二级管）以及Transistor（三极管）或是MOS的封装产品进行了改进，用金属带、金属夹板代替焊线，来降低封装电阻、电感与期望改善热消散的能力。 In order to solve the above problems, the industry has improved the traditional Diode (secondary tube) and Transistor (transistor) or MOS packaging products, using metal strips and metal splints instead of welding wires to reduce package resistance, inductance and expect to improve thermal performance. ability to dissipate.
如图1所示，为一种现有的MOS封装结构，此结构中引线框11包含管芯焊盘和引脚，在引线框11的管芯焊盘上植入第一芯片12、第二芯片13。第一芯片12的源极通过第一金属夹板14电耦合至引线框11，第一芯片12的栅极通过第一金属焊线16电耦合至引线框11。第二芯片13的源极通过第二金属夹板15电耦合至引线框11，第二芯片13的栅极通过第二金属焊线17电耦合至引线框11。再进行包封、切割、测试等后续工序。此MOS封装结构用金属夹板取代了传统MOS封装中的焊线，降低了部分封装电阻，但是还是存在以下缺陷：首先，此MOS封装结构中芯片的漏极、源极和栅极与引线框形成互联分别要用到不同的设备，制程复杂，设备的购置成本较高；其次，此MOS封装结构在把金属夹板和金属焊线耦合至芯片和引脚上时，只能一颗颗芯片进行，无法整条一体成型，制造效率较低。 As shown in Figure 1, it is a kind of existing MOS package structure, and lead frame 11 comprises die pad and pin in this structure, implants first chip 12, second chip 12 on the die pad of lead frame 11. Chip 13. The source of the first chip 12 is electrically coupled to the lead frame 11 through the first metal splint 14 , and the gate of the first chip 12 is electrically coupled to the lead frame 11 through the first metal bonding wire 16 . The source of the second chip 13 is electrically coupled to the lead frame 11 through the second metal splint 15 , and the gate of the second chip 13 is electrically coupled to the lead frame 11 through the second metal bonding wire 17 . Follow-up processes such as encapsulation, cutting, and testing are then carried out. This MOS packaging structure replaces the bonding wires in the traditional MOS packaging with metal splints, which reduces part of the packaging resistance, but there are still the following defects: First, the drain, source and gate of the chip in this MOS packaging structure are formed with the lead frame. Different devices are required for interconnection, the manufacturing process is complicated, and the purchase cost of the devices is high; secondly, when the metal splint and metal bonding wires are coupled to the chips and pins in this MOS packaging structure, it can only be done one by one. The whole strip cannot be integrally formed, and the manufacturing efficiency is low.
发明内容 Contents of the invention
本发明所要解决的技术问题是针对上述现有技术提供一种部分框架外露多芯片多搭平铺夹芯封装结构及其工艺方法，整条产品可一体成型，生产效率高，工艺简单，可降低成本，并且具有较好的散热性和较低的封装电阻和电感。 The technical problem to be solved by the present invention is to provide a partially frame-exposed multi-chip multi-lapped sandwich packaging structure and its process method for the above-mentioned prior art. The whole product can be integrally formed, with high production efficiency and simple process, which can reduce cost, and has better heat dissipation and lower package resistance and inductance.
本发明解决上述问题所采用的技术方案为：一种部分框架外露多芯片多搭平铺夹芯封装结构，它包括第一引线框、第二引线框、第一芯片和第二芯片，所述第二引线框包括第一上水平段、第一中间连接段、第一下水平段、第二上水平段、第二中间连接段和第二下水平段，所述第一芯片和第二芯片分别夹设在第一引线框与第二引线框的第一上水平段和第二上水平段之间，所述第一芯片的正面和背面分别通过锡膏与第二引线框的第一上水平段和第一引线框电性连接，第二芯片的正面和背面分别通过锡膏与第二引线框的第二上水平段和第一引线框电性连接，所述第一引线框和第二引线框外包封有塑封料，所述第二引线框的第一上水平段上表面和第二上水平段上表面不齐平，所述第一引线框下表面暴露于塑封料之外，所述第二引线框的第一上水平段上表面或第二上水平段上表面中的一个暴露于塑封料之外，所述第二引线框的第一下水平段下表面和第二下水平段下表面分别搭设在第一引线框上表面上。 The technical solution adopted by the present invention to solve the above problems is: a partial frame exposed multi-chip multi-lap tiled sandwich package structure, which includes a first lead frame, a second lead frame, a first chip and a second chip, the The second lead frame includes a first upper horizontal section, a first intermediate connecting section, a first lower horizontal section, a second upper horizontal section, a second intermediate connecting section and a second lower horizontal section, the first chip and the second chip respectively sandwiched between the first lead frame and the first upper horizontal section and the second upper horizontal section of the second lead frame, the front and back sides of the first chip are respectively connected to the first upper horizontal section of the second lead frame by solder paste. The horizontal section is electrically connected to the first lead frame, and the front and back sides of the second chip are respectively electrically connected to the second upper horizontal section of the second lead frame and the first lead frame through solder paste, and the first lead frame and the first lead frame are electrically connected to each other. The second lead frame is encapsulated with a molding compound, the upper surface of the first upper horizontal section of the second lead frame is not flush with the upper surface of the second upper horizontal section, and the lower surface of the first lead frame is exposed outside the molding compound, One of the upper surface of the first upper horizontal section or the upper surface of the second upper horizontal section of the second lead frame is exposed to the molding compound, and the lower surface of the first lower horizontal section and the second lower horizontal section of the second lead frame The lower surfaces of the horizontal sections are respectively built on the upper surfaces of the first lead frame.
所述第一引线框和第二引线框均为整体框架。 Both the first lead frame and the second lead frame are integral frames.
一种部分框架外露多芯片多搭平铺夹芯封装结构的工艺方法，所述方法包括如下步骤： A process method for a partially frame-exposed multi-chip multi-lapped sandwich packaging structure, said method comprising the following steps:
步骤一、提供第一引线框； Step 1, providing a first lead frame;
步骤二、在第一引线框基岛区域通过网板印刷的方式涂覆锡膏； Step 2, coating solder paste on the base island area of the first lead frame by screen printing;
步骤三，在步骤二中第一引线框基岛区域涂覆的锡膏上植入第一芯片和第二芯片； Step 3, implanting the first chip and the second chip on the solder paste coated on the base island area of the first lead frame in step 2;
步骤四，提供第二引线框，所述第二引线框包括第一上水平段、第一中间连接段、第一下水平段、第二上水平段、第二中间连接段和第二下水平段，在第二引线框的第一上水平段下表面、第一下水平段下表面、第二上水平段下表面和第二下水平段下表面通过网板印刷的方式涂覆锡膏； Step 4, providing a second lead frame, the second lead frame includes a first upper horizontal section, a first intermediate connecting section, a first lower horizontal section, a second upper horizontal section, a second intermediate connecting section and a second lower horizontal section segment, coating solder paste on the lower surface of the first upper horizontal section, the lower surface of the first lower horizontal section, the lower surface of the second upper horizontal section, and the lower surface of the second lower horizontal section of the second lead frame by screen printing;
步骤五，将第二引线框的第一上水平段和第二上水平段分别压合在第一引线框上表面的第一芯片和第二芯片上，且第二引线框的第一下水平段下表面和第二下水平段下表面分别搭设在第一引线框上表面上，压合后第一引线框和第二引线框形成整体框架； Step 5, respectively pressing the first upper horizontal section and the second upper horizontal section of the second lead frame on the first chip and the second chip on the upper surface of the first lead frame, and the first lower horizontal section of the second lead frame The lower surface of the section and the lower surface of the second lower horizontal section are respectively built on the upper surface of the first lead frame, and after pressing, the first lead frame and the second lead frame form an integral frame;
步骤六，将步骤五形成的整体框架上下表面用压板压住，进行回流焊； Step 6, press the upper and lower surfaces of the overall frame formed in step 5 with a pressure plate, and perform reflow soldering;
步骤七，将步骤六经过回流焊后的整体框架采用塑封料进行塑封，塑封后第二引线框的第一上水平段上表面和第二上水平段上表面中的一个暴露在塑封料之外； In step seven, the overall frame after reflow soldering in step six is plastic-sealed with a plastic encapsulant, and one of the upper surface of the first upper horizontal section of the second lead frame and the upper surface of the second upper horizontal section of the second lead frame is exposed outside the plastic encapsulant ;
步骤八，将步骤七完成塑封的半成品进行切割或是冲切作业，使原本阵列式塑封体，切割或是冲切独立开来，制得部分框架外露多芯片多搭平铺夹芯封装结构。 Step 8: Cutting or punching the semi-finished product that has been plastic-encapsulated in step 7, so that the original array-type plastic package can be cut or punched independently, and a part of the frame is exposed, and the multi-chip and tiled sandwich packaging structure is obtained.
所述第一引线框和第二引线框的材质可以为合金铜材、纯铜材、铝镀铜材、锌镀铜材、镍铁合金材，也可以为其它CTE范围是8*10^-6/℃~25*10^-6/℃的导电材质。 The material of the first lead frame and the second lead frame can be alloy copper material, pure copper material, aluminum-plated copper material, zinc-plated copper material, nickel-iron alloy material, or other CTE range of 8*10^-6 /℃~25*10^-6/℃ conductive material.
所述第一芯片和第二芯片为可以与金属锡结合的二极芯片、三极芯片或多极芯片。 The first chip and the second chip are two-pole chips, three-pole chips or multi-pole chips that can be combined with metal tin.
所述压板材质的热膨胀系数CTE与第一引线框、第二引线框材质的热膨胀系数CTE接近，其CTE范围是8*10^-6/℃~25*10^-6/℃。 The thermal expansion coefficient CTE of the pressing plate material is close to the thermal expansion coefficient CTE of the first lead frame and the second lead frame material, and the CTE range is 8*10^-6/°C~25*10^-6/°C.
所述步骤二和步骤四可通过不同机台同时进行。 The step 2 and step 4 can be carried out simultaneously through different machines.
与现有技术相比，本发明的优点在于： Compared with the prior art, the present invention has the advantages of:
1、本发明一种部分框架外露多芯片多搭平铺夹芯封装结构的第二引线框直接与MOS芯片的源极和栅极形成电性连接，取代了传统MOS芯片封装中利用金属焊线形成互联的工艺，充分减少了封装电阻，本发明的技术可以比传统封装设计的封装电阻降低至少30%以上； 1. In the present invention, the second lead frame of the exposed multi-chip multi-lay sandwich packaging structure is directly electrically connected to the source and gate of the MOS chip, replacing the use of metal bonding wires in traditional MOS chip packaging. The process of forming interconnection fully reduces the packaging resistance, and the technology of the present invention can reduce the packaging resistance by at least 30% compared with the traditional packaging design;
2、本发明一种部分框架外露多芯片多搭平铺夹芯封装结构的第二引线框直接通过锡膏与MOS芯片的源极和栅极形成电性连接，完全减免了金属焊线的互联工序，完全节省了金属焊线互联工序的设备购置、工序材料等成本。且本发明的第二引线框为整条一体成型的，与芯片形成电性连接也是整条一步完成，与传统金属焊线、金属片互联一个个芯片形成互联的工艺相比，工艺较为简单，生产效率有了明显的提高； 2. In the present invention, the second lead frame of a multi-chip multi-lay sandwich packaging structure with part of the frame exposed is directly electrically connected to the source and gate of the MOS chip through solder paste, which completely reduces the interconnection of metal bonding wires The process completely saves the cost of equipment purchase and process materials in the metal bonding wire interconnection process. Moreover, the second lead frame of the present invention is integrally formed in one piece, and the electrical connection with the chip is also completed in one step. Compared with the traditional metal bonding wire and metal sheet interconnection process to form interconnection of chips, the process is relatively simple. Production efficiency has been significantly improved;
3、本发明的一种部分框架外露多芯片多搭平铺夹芯封装结构由于芯片上下两个表面都直接与引线框相接触，芯片工作时产生的热量可通过引线框散出，且本发明的第一引线框下表面直接暴露在塑封料之外，本发明的部分框架外露多芯片多搭平铺夹芯封装结构具有较好的散热性能；而且本发明可再依据产品功率、导热或是散热的不同自由的在引线框上外加散热器,用以进一步增加产品热消散的能力； 3. A part of the framework of the present invention exposes multi-chip multi-lay tile sandwich packaging structure. Since the upper and lower surfaces of the chip are directly in contact with the lead frame, the heat generated when the chip is working can be dissipated through the lead frame, and the present invention The lower surface of the first lead frame is directly exposed to the plastic encapsulant, and the exposed part of the frame of the present invention has a multi-chip multi-lap tiled sandwich packaging structure with better heat dissipation performance; and the present invention can be based on product power, heat conduction or The difference in heat dissipation is free to add a heat sink on the lead frame to further increase the heat dissipation capability of the product;
4、本发明的一种部分框架外露多芯片多搭平铺夹芯封装结构使用上下压板压住整体框架进行回流焊，使得框架在回流焊时不易被锡膏受热熔解后的冷却过程的凝聚所顶起，保证框架结构的总高度，防止芯片的移动或旋转，并且能确保框架暴露外脚的共面性。 4. A part of the framework of the present invention with exposed multi-chip multi-lay tile sandwich packaging structure uses the upper and lower pressure plates to press the overall frame for reflow soldering, so that the frame is not easily affected by the condensation of the solder paste during the cooling process after thermal melting during reflow soldering. Jacking up ensures the overall height of the frame structure, prevents the chip from moving or rotating, and ensures the coplanarity of the exposed outer legs of the frame.
附图说明 Description of drawings
图1为一种已知的MOS封装结构示意图。 FIG. 1 is a schematic diagram of a known MOS package structure.
图2本发明制造的一种部分框架外露多芯片多搭平铺夹芯封装结构的侧面图。 Fig. 2 is a side view of a multi-chip multi-lap tiled sandwich packaging structure with part of the frame exposed and manufactured by the present invention.
图3本发明制造的一种部分框架外露多芯片多搭平铺夹芯封装结构的俯视图。 Fig. 3 is a top view of a multi-chip multi-lap flat sandwich packaging structure with part of the frame exposed and manufactured by the present invention.
图4为本发明已完成装片的第一引线框的立体视图。 Fig. 4 is a perspective view of the first lead frame that has been chip-loaded in the present invention.
图5为本发明中第二引线框的立体视图。 Fig. 5 is a perspective view of the second lead frame in the present invention.
图6（a）至图6（h）为本发明一种部分框架外露多芯片多搭平铺夹芯封装结构工艺方法的流程图。 FIG. 6( a ) to FIG. 6( h ) are flowcharts of a process method of a multi-chip and multi-lap tiled sandwich packaging structure with part of the frame exposed in the present invention.
其中： in:
引线框11 Lead frame 11
第一芯片12 first chip 12
第二芯片13 second chip 13
第一金属夹板14 The first metal splint 14
第二金属夹板15 The second metal splint 15
第一金属焊线16 First metal bonding wire 16
第二金属焊线17 Second metal bonding wire 17
第一引线框21 First lead frame 21
第二引线框22 Second lead frame 22
第一上水平段221 First Upper Horizontal Section 221
第一中间连接段222 The first intermediate connection section 222
第一下水平段223 First Lower Level 223
第二上水平段224 Second Upper Horizontal Section 224
第二中间连接段225 The second intermediate connection section 225
第二下水平段226 The second lower horizontal section 226
第一芯片23 first chip 23
锡膏24 Solder paste 24
塑封料25 Plastic compound 25
第二芯片26。 the second chip 26 .
具体实施方式 detailed description
以下结合附图实施例对本发明作进一步详细描述。 The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.
如图6（a）~图6（h）所示，本实施例中的一种部分框架外露多芯片多搭平铺夹芯封装结构的工艺方法，其具体工艺步骤如下： As shown in Fig. 6(a) to Fig. 6(h), in this embodiment, a process method in which part of the frame is exposed, multi-chips and multi-layer tiled sandwich packaging structure, the specific process steps are as follows:
步骤一、参见图6（a），提供第一引线框，第一引线框的材质为合金铜材、纯铜材、铝镀铜材、锌镀铜材、镍铁合金材，也可以为其它CTE范围是8*10^-6/℃~25*10^-6/℃的导电材质； Step 1, see Figure 6(a), provide the first lead frame, the material of the first lead frame is alloy copper material, pure copper material, aluminum copper plated material, zinc plated copper material, nickel-iron alloy material, or other CTE The range is 8*10^-6/℃~25*10^-6/℃ conductive material;
步骤二、参见图6（b），在第一引线框基岛区域通过网板印刷的方式涂覆锡膏，目的是为实现后续第一芯片植入后与基岛接合，通过调整网板的厚度和开口的面积可以精确的控制锡膏的厚度、面积以及位置； Step 2. Referring to Figure 6(b), apply solder paste on the base island area of the first lead frame by screen printing. The purpose is to realize the bonding with the base island after the first chip is implanted. Thickness and opening area can precisely control the thickness, area and position of solder paste;
步骤三，参见图6（c），在步骤二中第一引线框基岛区域涂覆的锡膏上植入第一芯片和第二芯片； Step 3, see FIG. 6(c), implant the first chip and the second chip on the solder paste coated on the base island area of the first lead frame in step 2;
步骤四，参见图6（d），提供第二引线框，所述第二引线框包括第一上水平段、第一中间连接段、第一下水平段、第二上水平段、第二中间连接段和第二下水平段，第二引线框的材质为合金铜材、纯铜材、铝镀铜材、锌镀铜材、镍铁合金材，也可以为其它CTE范围是8*10^-6/℃~25*10^-6/℃的导电材质。在第二引线框的第一上水平段下表面、第一下水平段下表面、第二上水平段下表面和第二下水平段下表面通过网板印刷的方式涂覆锡膏，通过调整网板的厚度和开口的面积可以精确的控制锡膏的厚度、面积以及位置； Step 4, see FIG. 6(d), provide a second lead frame, the second lead frame includes a first upper horizontal section, a first middle connecting section, a first lower horizontal section, a second upper horizontal section, a second middle For the connection section and the second lower horizontal section, the material of the second lead frame is alloy copper, pure copper, aluminum-plated copper, zinc-plated copper, nickel-iron alloy, or other materials. The CTE range is 8*10^- 6/℃~25*10^-6/℃ conductive material. Coating solder paste on the lower surface of the first upper horizontal section, the lower surface of the first lower horizontal section, the lower surface of the second upper horizontal section, and the lower surface of the second lower horizontal section of the second lead frame by screen printing, and adjusting The thickness of the stencil and the area of the opening can precisely control the thickness, area and position of the solder paste;
步骤五，参见图6（e），将第二引线框的第一上水平段和第二上水平段分别压合在第一引线框上表面的第一芯片和第二芯片上，使第一芯片和第二芯片分别与第二引线框通过第一上水平段下表面和第二上水平段下表面的锡膏形成电性连接，且第二引线框的第一下水平段下表面和第二下水平段下表面分别搭设在第一引线框上表面上，压合后第一引线框和第二引线框形成整体框架； Step 5, see FIG. 6(e), press-bond the first upper horizontal section and the second upper horizontal section of the second lead frame on the first chip and the second chip on the upper surface of the first lead frame respectively, so that the first The chip and the second chip are respectively electrically connected to the second lead frame through the solder paste on the lower surface of the first upper horizontal section and the lower surface of the second upper horizontal section, and the lower surface of the first lower horizontal section of the second lead frame is connected to the lower surface of the second upper horizontal section. The lower surfaces of the two lower horizontal sections are respectively built on the upper surface of the first lead frame, and after pressing, the first lead frame and the second lead frame form an integral frame;
步骤六，参见图6（f），将步骤五形成的整体框架上下表面用压板压住，进行回流焊。压板的材质要求不容易发生形变且具有良好的热传导性能，其热膨胀系数CTE与第一引线框和第二引线框材质的热膨胀系数CTE接近，其CTE范围是8*10^-6/℃~25*10^-6/℃； Step 6, see Figure 6(f), press the upper and lower surfaces of the overall frame formed in step 5 with a pressure plate, and perform reflow soldering. The material of the pressure plate is not easy to deform and has good thermal conductivity. Its thermal expansion coefficient CTE is close to the thermal expansion coefficient CTE of the first lead frame and the second lead frame material, and its CTE range is 8*10^-6/℃~25 *10^-6/℃;
步骤七，参见图6（g），将步骤六经过回流焊后的整体框架采用塑封料进行塑封，塑封后第二引线框的第一上水平段上表面和第二上水平段上表面中的一个暴露在塑封料之外； Step 7, see Figure 6(g), the overall frame after reflow soldering in step 6 is plastic-sealed with a plastic encapsulant, and the upper surface of the first upper horizontal section and the upper surface of the second upper horizontal section of the second lead frame after plastic sealing One is exposed from the molding compound;
步骤八，参见图6（h），将步骤七完成塑封的半成品进行切割或是冲切作业，使原本阵列式塑封体，切割或是冲切独立开来，制得部分框架外露多芯片多搭平铺夹芯封装结构。 Step 8, see Figure 6(h), cutting or punching the semi-finished product that has been plastic-encapsulated in step 7, so that the original array plastic package can be cut or punched independently, and a part of the frame exposed with multiple chips can be obtained. Flat sandwich package structure.
上述步骤中，步骤二和步骤四可通过不同机台同时进行。 Among the above steps, step 2 and step 4 can be performed simultaneously by different machines.
参见图2~图5，本发明一种部分框架外露多芯片多搭平铺夹芯封装结构，它包括第一引线框21、第二引线框22、第一芯片23和第二芯片26，所述第二引线框22包括第一上水平段221、第一中间连接段222、第一下水平段223、第二上水平段224、第二中间连接段225和第二下水平段226，所述第一芯片23和第二芯片26分别夹设在第一引线框21与第二引线框22的第一上水平段221和第二上水平段224之间，所述第一芯片23的正面和背面分别通过锡膏24与第二引线框22的第一上水平段221和第一引线框21电性连接，第二芯片26的正面和背面分别通过锡膏24与第二引线框22的第二上水平段224和第一引线框21电性连接，所述第一引线框21和第二引线框22外包封有塑封料25，所述第二引线框22的第一上水平段221上表面和第二上水平段224上表面不齐平，所述第一引线框21下表面暴露于塑封料25之外，所述第二引线框22的第一上水平段221上表面和第二上水平段224上表面中的一个暴露于塑封料25之外，所述第二引线框22的第一下水平段223下表面和第二下水平段226下表面分别搭设在第一引线框21上表面上。 Referring to Fig. 2 ~ Fig. 5, the present invention a kind of multi-chip tiled sandwich packaging structure exposed part of the frame, it includes the first lead frame 21, the second lead frame 22, the first chip 23 and the second chip 26, so The second lead frame 22 includes a first upper horizontal section 221, a first intermediate connecting section 222, a first lower horizontal section 223, a second upper horizontal section 224, a second intermediate connecting section 225 and a second lower horizontal section 226, so The first chip 23 and the second chip 26 are sandwiched between the first upper horizontal section 221 and the second upper horizontal section 224 of the first lead frame 21 and the second lead frame 22 respectively, and the front surface of the first chip 23 and the back side are electrically connected to the first upper horizontal section 221 of the second lead frame 22 and the first lead frame 21 through the solder paste 24 respectively, and the front and back sides of the second chip 26 are connected to the second lead frame 22 through the solder paste 24 respectively. The second upper horizontal section 224 is electrically connected to the first lead frame 21, the first lead frame 21 and the second lead frame 22 are encapsulated with a molding compound 25, and the first upper horizontal section 221 of the second lead frame 22 The upper surface and the upper surface of the second upper horizontal section 224 are not flush, the lower surface of the first lead frame 21 is exposed outside the molding compound 25, the upper surface of the first upper horizontal section 221 of the second lead frame 22 and the second One of the upper surfaces of the two upper horizontal sections 224 is exposed outside the molding compound 25, and the lower surface of the first lower horizontal section 223 and the lower surface of the second lower horizontal section 226 of the second lead frame 22 are respectively built on the first lead frame. 21 on the upper surface.
所述第一引线框21和第二引线框22均为整体框架，其材质可以为合金铜材、纯铜材、铝镀铜材、锌镀铜材、镍铁合金材，也可以为其它CTE范围是8*10^-6/℃~25*10^-6/℃的导电材质。 The first lead frame 21 and the second lead frame 22 are integral frames, and their materials can be alloy copper, pure copper, aluminum-plated copper, zinc-plated copper, nickel-iron alloy, or other CTE ranges. It is a conductive material of 8*10^-6/℃~25*10^-6/℃.
所述第一芯片23和第二芯片26为可以与金属锡结合的二极芯片、三极芯片或多极芯片。 The first chip 23 and the second chip 26 are two-pole chips, three-pole chips or multi-pole chips that can be combined with metal tin.
除上述实施例外，本发明还包括有其他实施方式，凡采用等同变换或者等效替换方式形成的技术方案，均应落入本发明权利要求的保护范围之内。 In addition to the above-mentioned embodiments, the present invention also includes other implementations, and any technical solution formed by equivalent transformation or equivalent replacement shall fall within the protection scope of the claims of the present invention.
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