CN105448347B - The test method of phase transition storage - Google Patents
The test method of phase transition storage Download PDFInfo
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- CN105448347B CN105448347B CN201410415020.5A CN201410415020A CN105448347B CN 105448347 B CN105448347 B CN 105448347B CN 201410415020 A CN201410415020 A CN 201410415020A CN 105448347 B CN105448347 B CN 105448347B
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- 238000010998 test method Methods 0.000 title claims abstract description 10
- 230000007704 transition Effects 0.000 title abstract description 14
- 239000012782 phase change material Substances 0.000 claims abstract description 132
- 230000008859 change Effects 0.000 claims abstract description 66
- 230000015654 memory Effects 0.000 claims abstract description 51
- 238000000034 method Methods 0.000 claims abstract description 17
- 238000012360 testing method Methods 0.000 claims description 30
- 229910000618 GeSbTe Inorganic materials 0.000 claims description 4
- 229910000796 S alloy Inorganic materials 0.000 claims description 2
- 230000002159 abnormal effect Effects 0.000 abstract description 3
- 230000008569 process Effects 0.000 description 3
- 238000011160 research Methods 0.000 description 3
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000005864 Sulphur Substances 0.000 description 1
- 150000004770 chalcogenides Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
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- 230000005855 radiation Effects 0.000 description 1
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Abstract
This application discloses a kind of test method of phase transition storage, which includes the following steps：The phase state of phase-change material in reading phase change memories, and it is denoted as the first phase；Apply the first group pulse signal to phase transition storage, sets the reference upper level value of the signal amplitude of the first group pulse signal as Ka, the signal amplitude of the 1st subpulse signal is set as Kb, and read the phase state for applying the phase-change material after the first group pulse signal every time；Apply signal amplitude K to phase transition storagen=Kb+c(n‑1)KbN-th pulse signal, and if Kn< KaAnd the phase state of phase-change material is changed into the second phase, illustrates that phase-change material turns to the working properly of the second phase by the first phase, if Kn> KaAnd the phase state of phase-change material is not changed into the second phase, illustrates that phase-change material is abnormal by the work of the first phase the second phase of steering.This method is capable of detecting when whether the work of the phase transition in phase transition storage is normal.
Description
Technical Field
The present disclosure relates to the field of semiconductor integrated circuits, and more particularly, to a method for testing a phase change memory.
Background
Phase Change Memory (PCM) is a non-volatile Memory device that stores data using a difference in conductivity of a Phase Change material between crystalline and amorphous states. The phase change memory has the advantages of high reading speed, high erasable times, small size of components, strong vibration resistance, radiation resistance and the like, is widely applied to the fields of digital cameras, music players, telephones and the like, and becomes the most mainstream product for replacing flash memories.
In the amorphous state, the phase change material has short range atomic energy levels and a low free electron density, making it highly resistive (which can exceed 1 megaohm). Since this state generally occurs after RESET (erase operation), the amorphous state is generally referred to as the RESET state. In the crystalline state, the phase change material has a long atomic energy level and a high free resistance density, so that the phase change material has low resistance (generally 1-10 kilo-ohm). Since this state usually occurs after a SET (write operation), the crystalline state is generally referred to as the SET state.
The phase change memory has the working principle that pulse signals act on a device unit to enable the phase change material to generate reversible phase change between an amorphous state and a crystalline state, and the writing, erasing and reading operations of information are realized by distinguishing high resistance in the amorphous state from low resistance in the crystalline state. The specific process of the erasing operation (RESET) is as follows: when a short and strong pulse signal is applied to raise the temperature of the phase-change material in the device unit to be above the melting temperature, the phase-change material is rapidly cooled, and the phase-change material is converted from the crystalline state to the amorphous state. The specific process of the write operation (SET) is as follows: when a long and medium-intensity pulse signal is applied to raise the temperature of the phase-change material to be below the melting temperature and to be above the crystallization temperature, the pulse signal is maintained for a period of time to promote the growth of crystal nuclei, so that the phase-change material is converted from the amorphous state to the crystalline state. The specific process of the read operation is as follows: after applying a very weak pulse signal that does not affect the state of the phase change material, the state of the device cell is read by measuring its resistance value.
Currently, the development direction of the phase change memory is to reduce power consumption, and the power consumption of the phase change memory is closely related to phase transition of the phase change material (power consumption required for phase transition, such as RESET current, etc.). Therefore, theoretical support can be provided for designers to reduce the power consumption of the phase change memory by acquiring the resistance of the phase change material. During the operation of the phase change memory, the phase transition (transition between the RESET state and the SET state) of the phase change material may sometimes fail, that is, the phase change material may not operate normally from the RESET state to the SET state, or the phase change material may not operate normally from the SET state to the RESET state, so that the phase change memory may not operate normally. In view of the above problems, no effective solution exists at present.
Disclosure of Invention
The present application is directed to a method for testing a phase change memory to detect whether a phase transition operation in the phase change memory is normal.
In order to achieve the above object, the present application provides a method for testing a phase change memory, the method comprising the steps of: reading the phase state of the phase change material in the phase change memory and recording as a first phase state; applying a first group of pulse signals to the phase change memory, the first group of pulse signals including 1 st to nth pulse signals with gradually increased signal amplitude, setting the reference upper limit value of the signal amplitude of the first group of pulse signals to be KaSetting the signal amplitude of the 1 st pulse signal to be KbAnd reading the phase state of the phase change material after each application of the first set of pulse signals; applying a signal amplitude K to a phase change memoryn＝Kb+c(n-1)KbWhere c is a constant if Kn＜KaAnd the phase state of the phase-change material is converted into a second phase state, which indicates that the phase-change material normally works when being converted from the first phase state to the second phase state, if Kn＞KaThe phase state of the phase-change material is not converted into the second phase state, which indicates that the phase-change material is abnormal in working from the first phase state to the second phase state; wherein, the first phase state is a RESET state, and the second phase state is a SET state; or the first phase state is SET state and the second phase state is RESET state.
Further, when the phase change material is in a normal working state from the first phase state to the second phase state, the testing method further comprises the following steps: applying a second group of pulse signals to the phase change memory, the second group of pulse signals including 1 st to m th pulse signals with gradually increased signal amplitudes, setting the reference upper limit value of the signal amplitudes of the second group of pulse signals to be KdSetting the signal amplitude of the 1 st pulse signal to be KeAnd reading the phase state of the phase change material after each application of the second set of pulse signals; applying a signal amplitude K to a phase change memorym＝Ke+f(m-1)KeWhere f is a constant if Km＜KdAnd the phase state of the phase-change material is converted into the first phase state, which indicates that the phase-change material normally works when being converted from the second phase state to the first phase state, if K ism＞KdAnd the phase state of the phase-change material is not converted into the first phase state, which indicates that the phase-change material is abnormally converted from the second phase state to the first phase state.
Further, the test method terminates after the following period: the phase change material is abnormally changed from a first phase state to a second phase state; or the phase change material is normally switched from the first phase state to the second phase state; or the phase change material is normally switched from the second phase state to the first phase state; or a phase change material that is not properly working to change from the second phase to the first phase.
Further, the step of reading the phase state of the phase change material comprises: performing a read operation on the phase change memory to obtain a true resistance of the phase change material; and comparing the real resistance with the reference resistance, wherein if the real resistance is greater than the reference resistance, the phase state of the phase-change material is a RESET state, and if the real resistance is less than the reference resistance, the phase state of the phase-change material is an SET state.
Further, the step of performing a read operation on the phase change memory includes: applying a test voltage and a test current to the phase change material; and calculating to obtain the real resistance according to the test voltage and the test current.
Furthermore, the phase-change material is a sulfur GeSbTe alloy, and the reference resistance is 50-200K omega.
Furthermore, the first group of pulse signals are pulse voltages, the signal amplitude of the first group of pulse signals is the pulse width of the first group of pulse signals, and in the first group of pulse signals, K isa＝3～5V，Kb＝1～3V，c＝0.05～0.3。
Further, in the first group of pulse signals, Ka＝5V，Kb＝2V，c＝0.1。
Furthermore, the second group of pulse signals are pulse voltages, the signal amplitude of the second group of pulse signals is the pulse width of the second group of pulse signals, and in the second group of pulse signals, K isd＝3～5V，Ke＝1～3V，f＝0.05～0.3。
Further, in the second group of pulse signals, Kd＝5V，Ke＝2V，f＝0.1。
By applying the technical scheme of the application, the phase state of the phase change material in the phase change memory is read and recorded as a first phase state, then a first group of pulse signals are applied to the phase change memory, wherein the signal amplitude K is applied to the phase change memoryn＝Kb+c(n-1)KbWhen the pulse signal is n, if K isn＜KaAnd the phase state of the phase-change material is converted into a second phase state, which indicates that the phase-change material normally works when being converted from the first phase state to the second phase state, if Kn＞KaAnd the phase state of the phase-change material is not converted into the second phase state, which indicates that the phase-change material is abnormally converted from the first phase state to the second phase state. Therefore, the testing method can detect that the phase change material is normally enough to change from the first phase state to the second phase state. Further, the purpose of obtaining the resistance of the phase change material is achieved by performing a read operation on the phase change memory to obtain the true resistance of the phase change material in the step of reading the phase state of the phase change material after each application of the first set of pulse signals.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
fig. 1 shows a flow chart of a method for testing a phase change memory according to an embodiment of the present disclosure.
Detailed Description
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, and it should be understood that when used in this specification the singular forms "a", "an", and/or "the" include "specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
Spatially relative terms, such as "above … …," "above … …," "above … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial relationship to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, devices described as "above" or "on" other devices or configurations would then be oriented "below" or "under" the other devices or configurations. Thus, the exemplary term "above … …" can include both an orientation of "above … …" and "below … …". The device may be otherwise variously oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
As described in the background, it is not possible in the prior art to detect whether a phase transition in a phase change memory operates normally. In view of the above problems, the inventors of the present application have studied and proposed a method for testing a phase change memory. As shown in fig. 1, the testing method includes the steps of: reading the phase state of the phase change material in the phase change memory and recording as a first phase state; applying a first group of pulse signals to the phase change memory, the first group of pulse signals including 1 st to nth pulse signals with gradually increased signal amplitude, setting the reference upper limit value of the signal amplitude of the first group of pulse signals to be KaSetting the signal amplitude of the 1 st pulse signal to be KbAnd reading the phase state of the phase change material after each application of the first set of pulse signals; applying a signal amplitude K to a phase change memoryn＝Kb+c(n-1)KbWhere c is a constant if Kn＜KaAnd the phase state of the phase-change material is converted into a second phase state, which indicates that the phase-change material normally works when being converted from the first phase state to the second phase state, if Kn＞KaThe phase state of the phase-change material is not converted into the second phase state, which indicates that the phase-change material is abnormal in working from the first phase state to the second phase state; wherein, the first phase state is a RESET state, and the second phase state is a SET state; or the first phase state is SET state and the second phase state is RESET state.
The testing method comprises reading the phase state of the phase change material in the phase change memory, and recording as the first phase state, and applying the first group of pulse signals to the phase change memory, wherein the signal amplitude K is applied to the phase change memoryn＝Kb+c(n-1)KbWhen the pulse signal is n, if K isn＜KaAnd the phase state of the phase-change material is converted into a second phase state, which indicates that the phase-change material normally works when being converted from the first phase state to the second phase state, if Kn＞KaAnd the phase state of the phase-change material is not converted into the second phase state, which indicates that the phase-change material is abnormally converted from the first phase state to the second phase state. Therefore, the testing method can detect that the phase change material is normally enough to change from the first phase state to the second phase state. Further, the purpose of obtaining the resistance of the phase change material is achieved by performing a read operation on the phase change memory to obtain the true resistance of the phase change material in the step of reading the phase state of the phase change material after each application of the first set of pulse signals.
Exemplary embodiments of the test methods provided according to the present application will be described in more detail below. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.
First, the phase state of the phase change material in the phase change memory is read and recorded as a first phase state. In this step, the first phase state may be a RESET state or a RESET state. Preferably, the step comprises: performing a read operation on the phase change memory to obtain a true resistance of the phase change material; and comparing the real resistance with the reference resistance, wherein if the real resistance is greater than the reference resistance, the phase state of the phase-change material is a RESET state, and if the real resistance is less than the reference resistance, the phase state of the phase-change material is an SET state.
The phase change material may be a chalcogenide phase change material commonly used in the art. Preferably, the phase change material is a GeSbTe sulphur alloy, such as GeSb2Te4And the like. Of course, the kind of the phase change material is not limited to the above preferred embodiment. Meanwhile, the type of the phase-change material determines the size of the reference resistance. When the phase change material is a GeSbTe sulfur alloy, the reference resistance is preferably 50-200K omega.
The read operation is to apply a weak pulse signal that does not affect the state of the phase change material to the phase change memory to read the resistance of the phase change material. Specifically, the read operation includes the steps of: applying a test voltage and a test current to the phase change material; and calculating to obtain the real resistance according to the test voltage and the test current.
After the step of reading the phase state of the phase change material in the phase change memory is finished, applying a first group of pulse signals to the phase change memory, wherein the first group of pulse signals comprises 1 st to nth pulse signals with gradually increased signal amplitude, and setting the reference upper limit value of the signal amplitude of the first group of pulse signals to be KaSetting the signal amplitude of the 1 st pulse signal to be KbAnd reading the phase state of the phase change material after each application of the first set of pulse signals. At the same time, when applying signal amplitude K to the phase change memoryn＝Kb+c(n-1)KbIs the nth pulse signal, and if Kn＜KaAnd the phase state of the phase-change material is converted into a second phase state, which indicates that the phase-change material normally works when being converted from the first phase state to the second phase state, if Kn＞KaAnd the phase state of the phase-change material is not converted into the second phase state, which indicates that the phase-change material is abnormally converted from the first phase state to the second phase state.
In the step, the first phase state is a RESET state, and the second phase state is a SET state; or the first phase state is SET state and the second phase state is RESET state. Furthermore, the type of the first set of pulse signals is related to the phase transition of the phase change material. When the first phase state is a RESET state and the second phase state is a SET state, the first group of pulse signals are long and medium-strength pulse signals. When the first phase state is a SET state and the second phase state is a RESET state, the first group of pulse signals are short and strong pulse signals.
The first group of pulse signals may be pulse voltages or pulse currents, and the signal amplitude of the first group of pulse signals may be a pulse width of the first group of pulse signals. When the first set of pulse signals are pulsed voltages, one skilled in the art can set the parameters of the first set of pulse signals according to the teachings of the present application. The inventor obtains a first group of pulse signals through a great deal of experimental researchThe optimum parameters of (1). Among the optimum parameters, Ka＝3～5V，Kb1-3V, and c is 0.05-0.3. More preferably, Ka＝5V，Kb2V, c is 0.1. Experimental research shows that the working condition that the phase change material is switched from the first phase state to the second phase state can be detected more accurately by adopting the parameters for testing.
When the phase change material is in normal operation from the first phase state to the second phase state, the testing method further comprises the following steps: applying a second group of pulse signals to the phase change memory, the second group of pulse signals including 1 st to m th pulse signals with gradually increased signal amplitudes, setting the reference upper limit value of the signal amplitudes of the second group of pulse signals to be KdSetting the signal amplitude of the 1 st pulse signal to be KeAnd reading the phase state of the phase change material after each application of the second set of pulse signals; applying a signal amplitude K to a phase change memorym＝Ke+f(m-1)KeWhere f is a constant if Km＜KdAnd the phase state of the phase-change material is converted into the first phase state, which indicates that the phase-change material normally works when being converted from the second phase state to the first phase state, if K ism＞KdAnd the phase state of the phase-change material is not converted into the first phase state, which indicates that the phase-change material is abnormally converted from the second phase state to the first phase state.
In the step, the first phase state is a RESET state, and the second phase state is a SET state; or the first phase state is SET state and the second phase state is RESET state. Furthermore, the type of the first set of pulse signals is related to the phase transition of the phase change material. When the first phase state is a RESET state and the second phase state is a SET state, the second group of pulse signals are short and strong pulse signals. When the first phase state is a SET state and the second phase state is a RESET state, the first group of pulse signals are long and medium-strength pulse signals.
The second group of pulse signals can be pulse voltage or pulse current, and the signal amplitude of the second group of pulse signals can be the pulse width of the first group of pulse signals. When the second group of pulse signals are pulse voltages, those skilled in the art can use the present inventionThe teaching sets parameters for the second set of pulse signals. The inventor has obtained the best parameters of the second group of pulse signals through a great deal of experimental research. Among the optimum parameters, Ka＝3～5V，Kb1-3V, and c is 0.05-0.3. More preferably, Ka＝5V，Kb2V, c is 0.1. Experimental research shows that the working condition that the phase change material is converted from the second phase state to the first phase state can be detected more accurately by adopting the parameters for testing.
In the above test modes provided by the present application, the test mode may be terminated after obtaining the expected result. Preferably, the test method terminates after the following period: the phase change material is abnormally changed from a first phase state to a second phase state; or the phase change material is normally switched from the first phase state to the second phase state; or the phase change material is normally switched from the second phase state to the first phase state; or a phase change material that is not properly working to change from the second phase to the first phase. At this time, it is indicated that the phase change memory is not working normally, the test mode should be terminated, and the idea of the phase change memory working abnormally should be further analyzed, and the subsequent improvement work should be performed.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
(1) the phase change memory is characterized in that the phase state of a phase change material in the phase change memory is read and recorded as a first phase state, and then a first group of pulse signals are applied to the phase change memory, wherein the signal amplitude K is applied to the phase change memoryn＝Kb+c(n-1)KbWhen the pulse signal is n, if K isn＜KaAnd the phase state of the phase-change material is converted into a second phase state, which indicates that the phase-change material normally works when being converted from the first phase state to the second phase state, if Kn＞KaAnd the phase state of the phase-change material is not converted into the second phase state, which indicates that the phase-change material is abnormally converted from the first phase state to the second phase state. Therefore, the testing method can detect that the phase change material is normally enough to change from the first phase state to the second phase state.
(2) Further, in the step of reading the phase state of the phase change material after each application of the first group of pulse signals, the application performs a read operation on the phase change memory to obtain the true resistance of the phase change material, so as to achieve the purpose of obtaining the resistance of the phase change material.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A test method of a phase change memory is characterized by comprising the following steps:
reading the phase state of the phase change material in the phase change memory and recording the phase state as a first phase state;
applying a first group of pulse signals to the phase change memory, wherein the first group of pulse signals comprises 1 st to nth pulse signals with gradually increased signal amplitude, and the reference upper limit value of the signal amplitude of the first group of pulse signals is set to be KaSetting the signal amplitude of the 1 st pulse signal to be KbAnd is combined withReading a phase state of the phase change material after application of each pulse signal of the first set of pulse signals;
the step of applying the first set of pulse signals to the phase change memory further comprises: applying a signal amplitude K to the phase change memoryn＝Kb+c(n-1)KbWherein c is a constant if Kn＜KaAnd the phase state of the phase-change material is converted into a second phase state, which indicates that the phase-change material normally works when being converted from the first phase state to the second phase state, if Kn＞KaAnd the phase state of the phase change material is not converted into the second phase state, which indicates that the phase change material is abnormally converted from the first phase state to the second phase state; wherein,
the first phase state is a RESET state, and the second phase state is a SET state; or the first phase state is a SET state, and the second phase state is a RESET state.
2. The method of claim 1, wherein when the phase change material changes from the first phase state to the second phase state, the method further comprises the following steps:
applying a second group of pulse signals to the phase change memory, wherein the second group of pulse signals comprises 1 st to m th pulse signals with gradually increased signal amplitude, and the reference upper limit value of the signal amplitude of the second group of pulse signals is set to be KdSetting the signal amplitude of the 1 st pulse signal to be KeAnd reading the phase state of the phase change material after each pulse signal in the second group of pulse signals is applied;
the step of applying the second set of pulse signals to the phase change memory further comprises: applying a signal amplitude K to the phase change memorym＝Ke+f(m-1)KeWhere f is a constant if Km＜KdAnd the phase state of the phase-change material is converted into the first phase state, which indicates that the phase-change material normally works when being converted from the second phase state to the first phase state, if Km＞KdAnd the phase state of the phase change material is not converted into the first phase state, which indicates that the phase change material is abnormally converted from the second phase state to the first phase state.
3. The test method of claim 2, wherein the test method terminates after a period of:
the phase change material is not normally operated from the first phase state to the second phase state; or
The phase change material is switched from the first phase state to the second phase state to work normally; or
The phase change material is normally switched from the second phase state to the first phase state; or
The phase change material may not operate properly from the second phase to the first phase.
4. The testing method of claim 2, wherein the step of reading the phase state of the phase change material comprises:
performing a read operation on the phase change memory to obtain a true resistance of the phase change material;
and comparing the real resistance with a reference resistance, wherein if the real resistance is larger than the reference resistance, the phase state of the phase-change material is the RESET state, and if the real resistance is smaller than the reference resistance, the phase state of the phase-change material is the SET state.
5. The method of claim 4, wherein the step of performing a read operation on the phase change memory comprises:
applying a test voltage and a test current to the phase change material;
and calculating the real resistance according to the test voltage and the test current.
6. The test method according to claim 4, wherein the phase change material is a GeSbTe sulfur alloy, and the reference resistance is 50-200K Ω.
7. The method according to claim 1, wherein the first set of pulse signals are pulse voltages, the first set of pulse signals have signal amplitudes of pulse widths of the first set of pulse signals, and K is the pulse width of the first set of pulse signalsa＝3～5V，Kb＝1～3V，c＝0.05～0.3。
8. The method of claim 7, wherein K is the first set of pulse signalsa＝5V，Kb＝2V，c＝0.1。
9. The method according to claim 2, wherein the second set of pulse signals are pulse voltages, the signal amplitude of the second set of pulse signals is the pulse width of the second set of pulse signals, and in the second set of pulse signals, K isd＝3～5V，Ke＝1～3V，f＝0.05～0.3。
10. The method of claim 9, wherein K is K in the second set of pulse signalsd＝5V，Ke＝2V，f＝0.1。
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1669091A (en) * | 2002-09-11 | 2005-09-14 | 奥翁尼克斯公司 | Programming a phase-change material memory |
| CN102741935A (en) * | 2010-02-02 | 2012-10-17 | Nxp股份有限公司 | Phase change memory programming method and phase change memory |
| CN102842341A (en) * | 2011-06-23 | 2012-12-26 | 旺宏电子股份有限公司 | High-endurance phase-change memory device and method of operating the same |
| US8576619B2 (en) * | 2011-01-28 | 2013-11-05 | SK Hynix Inc. | Phase change random access memory apparatus performing a firing operation |
-
2014
- 2014-08-21 CN CN201410415020.5A patent/CN105448347B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1669091A (en) * | 2002-09-11 | 2005-09-14 | 奥翁尼克斯公司 | Programming a phase-change material memory |
| CN102741935A (en) * | 2010-02-02 | 2012-10-17 | Nxp股份有限公司 | Phase change memory programming method and phase change memory |
| US8576619B2 (en) * | 2011-01-28 | 2013-11-05 | SK Hynix Inc. | Phase change random access memory apparatus performing a firing operation |
| CN102842341A (en) * | 2011-06-23 | 2012-12-26 | 旺宏电子股份有限公司 | High-endurance phase-change memory device and method of operating the same |
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