CN105405832A - Part frame exposed multi-chip flat-paved sandwich encapsulation structure and technological process thereof - Google Patents
Part frame exposed multi-chip flat-paved sandwich encapsulation structure and technological process thereof Download PDFInfo
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- CN105405832A CN105405832A CN201510989782.0A CN201510989782A CN105405832A CN 105405832 A CN105405832 A CN 105405832A CN 201510989782 A CN201510989782 A CN 201510989782A CN 105405832 A CN105405832 A CN 105405832A
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 230000008569 process Effects 0.000 title claims abstract description 23
- 238000005538 encapsulation Methods 0.000 title claims description 5
- 229910000679 solder Inorganic materials 0.000 claims abstract description 40
- 238000004806 packaging method and process Methods 0.000 claims abstract description 37
- 238000005476 soldering Methods 0.000 claims abstract description 19
- 239000011248 coating agent Substances 0.000 claims abstract description 10
- 238000000576 coating method Methods 0.000 claims abstract description 10
- 238000003825 pressing Methods 0.000 claims abstract description 8
- 238000004080 punching Methods 0.000 claims abstract description 6
- 150000001875 compounds Chemical class 0.000 claims abstract description 5
- 238000005520 cutting process Methods 0.000 claims abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims description 36
- 239000002184 metal Substances 0.000 claims description 36
- 239000000463 material Substances 0.000 claims description 29
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 25
- 229910052802 copper Inorganic materials 0.000 claims description 25
- 239000010949 copper Substances 0.000 claims description 25
- 238000007650 screen-printing Methods 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 7
- 238000000465 moulding Methods 0.000 claims description 7
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 claims description 6
- 229910000952 Be alloy Inorganic materials 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 230000005405 multipole Effects 0.000 claims description 3
- 239000011265 semifinished product Substances 0.000 claims description 3
- 230000017525 heat dissipation Effects 0.000 abstract description 10
- 238000007789 sealing Methods 0.000 abstract description 2
- 230000009286 beneficial effect Effects 0.000 abstract 1
- 239000000047 product Substances 0.000 description 14
- 238000004519 manufacturing process Methods 0.000 description 11
- 238000003466 welding Methods 0.000 description 7
- 239000008393 encapsulating agent Substances 0.000 description 6
- 239000000956 alloy Substances 0.000 description 5
- TVTJUIAKQFIXCE-HUKYDQBMSA-N 2-amino-9-[(2R,3S,4S,5R)-4-fluoro-3-hydroxy-5-(hydroxymethyl)oxolan-2-yl]-7-prop-2-ynyl-1H-purine-6,8-dione Chemical compound NC=1NC(C=2N(C(N(C=2N=1)[C@@H]1O[C@@H]([C@H]([C@H]1O)F)CO)=O)CC#C)=O TVTJUIAKQFIXCE-HUKYDQBMSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229940125851 compound 27 Drugs 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 238000012536 packaging technology Methods 0.000 description 4
- 239000002699 waste material Substances 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000005022 packaging material Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011093 chipboard Substances 0.000 description 1
- 238000009833 condensation Methods 0.000 description 1
- 230000005494 condensation Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000009192 sprinting Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49537—Plurality of lead frames mounted in one device
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L21/603—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving the application of pressure, e.g. thermo-compression bonding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D
- H01L25/072—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D the devices being arranged next to each other
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
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- Lead Frames For Integrated Circuits (AREA)
Abstract
本发明涉及一种部分框架外露多芯片平铺夹芯封装结构及其工艺方法，所述方法包括以下步骤：步骤一、提供第一引线框；步骤二、在第一引线框上涂覆锡膏；步骤三、在第一引线框锡膏上植入第一芯片；步骤四、提供第二引线框；步骤五、在第二引线框上涂覆锡膏；步骤六、将第二引线框压合在第一芯片上；步骤七、进行回流焊；步骤八、在第二引线框上涂覆锡膏；步骤九、在第二引线框上植入第二芯片；步骤十、提供第三引线框；步骤十一、在第三引线框上涂覆锡膏；步骤十二、将第三引线框压合在第二芯片上；步骤十三、进行回流焊；步骤十四、塑封料塑封；步骤十五、切割或冲切作业。本发明的有益效果是：增加产品热消散的能力，降低产品的封装电阻。
The present invention relates to a multi-chip tiled sandwich packaging structure with partial frame exposed and a process method thereof. The method comprises the following steps: step 1, providing a first lead frame; step 2, coating solder paste on the first lead frame ; Step 3, implanting the first chip on the first lead frame solder paste; Step 4, providing the second lead frame; Step 5, coating the solder paste on the second lead frame; Step 6, pressing the second lead frame combined on the first chip; step seven, reflow soldering; step eight, coating solder paste on the second lead frame; step nine, implanting the second chip on the second lead frame; step ten, providing the third lead Frame; step eleven, coating solder paste on the third lead frame; step twelve, pressing the third lead frame on the second chip; step thirteen, performing reflow soldering; step fourteen, plastic sealing compound; Step fifteen, cutting or punching operation. The invention has the beneficial effects of increasing the heat dissipation capability of the product and reducing the packaging resistance of the product.
Description
技术领域 technical field
本发明涉及一种部分框架外露多芯片平铺夹芯封装结构及其工艺方法，属于半导体封装技术领域。 The invention relates to a partially frame-exposed multi-chip tiled sandwich packaging structure and a process method thereof, belonging to the technical field of semiconductor packaging.
背景技术 Background technique
近年来，随着电子产品对功率密度不断的追求，无论是Diode（二级管）还是Transistor（三极管）的封装，尤其是Transistor中的MOS产品正朝着更大功率、更小尺寸、更快速、散热更好的趋势在发展。封装的一次性制造方式也由单颗封装技术慢慢朝向小区域甚至更大区域的高密度高难度低成本一次性封装技术冲刺与挑战。 In recent years, with the continuous pursuit of power density in electronic products, whether it is Diode (secondary tube) or Transistor (transistor) packaging, especially the MOS products in Transistor are moving towards higher power, smaller size, faster , The trend of better heat dissipation is developing. The one-time manufacturing method of packaging is also gradually sprinting and challenging from single-chip packaging technology to high-density, high-difficulty and low-cost one-time packaging technology in small areas or even larger areas.
因此，也对MOS产品的封装在寄生的电阻、电容、电感等的各种电性能、封装的结构、封装的热消散性能力、封装的信赖性方面以及高难度一次性封装技术方面有了更多的要求。 Therefore, the packaging of MOS products has been improved in terms of various electrical properties such as parasitic resistance, capacitance, and inductance, packaging structure, heat dissipation capability of packaging, reliability of packaging, and high-difficulty one-time packaging technology. much request.
传统的Diode（二级管）以及Transistor（三极管）或是MOS产品的封装一般依据产品特性、功率的不同以及成本的考虑因素，利用了金线、银合金线、铜线、铝线以及铝带的焊线方式作为芯片与内引脚的主要的互联技术，从而实现电气连接。然而焊线的技术方式对产品的性能存在了以下几个方面的限制与缺陷： Traditional Diode (secondary tube) and Transistor (transistor) or MOS product packages generally use gold wires, silver alloy wires, copper wires, aluminum wires, and aluminum strips based on product characteristics, power differences, and cost considerations. The wire bonding method is used as the main interconnection technology between the chip and the internal pins, so as to realize the electrical connection. However, the technical method of welding wire has the following limitations and defects on the performance of the product:
一、封装与制造方面的限制与缺陷： 1. Limitations and defects in packaging and manufacturing:
1）、焊接能力（Bondability）方面：常常会因为金属丝材料、金属引脚材料的变化以及设备与工具的参数片变化、性能与精度的变化以及保养与校正管理而造成的第一焊点以及第二焊点结合面的虚焊、脱落、断点、颈部裂缝、塌线以及短路等种种的困扰，导致了封装良率无法提升、成本无法下降、可靠性的不稳定； 1) In terms of welding ability (Bondability): the first solder joint and the Various troubles such as virtual soldering, peeling, breakpoints, neck cracks, collapsed wires, and short circuits on the joint surface of the second solder joint lead to the inability to increase the packaging yield, the cost cannot be reduced, and the reliability is unstable;
2）、一次性高密度封装技术方面：传统的互联方式几乎都是在矩阵型金属引线框上采用单颗芯片一颗一颗芯片重复进行装片、金属丝采高温超声一根线一根线的焊接方式。而这样情况下无论是专业的装片机、球焊打线机、键合铝线/铝带机或是铜片搭接机等机器设备再高速的重复动作都无法提升生产效率、无法降低单位成本，也因为设备不断的提升生产速度同样的也提升了制造的不稳定性。 2) Disposable high-density packaging technology: the traditional interconnection method is almost always to use a single chip on a matrix metal lead frame to repeatedly mount chips one by one, and use high-temperature ultrasonic wires for metal wires. welding method. In this case, whether it is a professional chip loading machine, a ball bonding machine, a bonding aluminum wire/aluminum strip machine or a copper lap splicing machine, no matter how high-speed and repetitive actions of machinery and equipment can not improve production efficiency, it is impossible to reduce the unit. Cost, but also because the continuous improvement of equipment production speed also increases the instability of manufacturing.
二、封装产品的特性能方面的限制与缺陷： 2. Limitations and defects in the performance of packaged products:
1）、热消散方面：传统的Diode（二级管）以及Transistor（三极管）或是MOS的封装产品，一般都是由塑封料包覆、只留外部引脚暴露在塑封体之外，由于塑封料本身不是一种热导的物质，所以传统的Diode（二级管）以及Transistor（三极管）或是MOS产品在工作时所产生的热量很难通过塑封料消散出塑封料物质的封装体，只能依靠细细的金属丝互联在金属引脚材料来帮助热能的消散，但是这种热消散的途径对热的消散能力是非常有限的，反而形成热消散的阻力； 1) In terms of heat dissipation: traditional Diode (secondary tube) and Transistor (transistor) or MOS package products are generally covered by plastic packaging materials, leaving only the external pins exposed outside the plastic package. The material itself is not a thermally conductive substance, so the heat generated by the traditional Diode (secondary tube) and Transistor (triode) or MOS products is difficult to dissipate through the plastic packaging material. It can rely on thin metal wires interconnected with metal pin materials to help dissipate heat energy, but this way of heat dissipation is very limited in heat dissipation capacity, and instead forms resistance to heat dissipation;
2）、电阻率（Resistivity）方面：大家都知道电阻率（resistivity）是用来表示各种物质电阻特性的物理量。在温度一定的情况下，有公式R=ρl/s其中的ρ就是电阻率，l为材料的长度，s为面积。可以看出，材料的电阻大小正比于材料的长度，而反比于其面积。由上式可知电阻率的定义：ρ=Rs/l。传统的Diode（二级管）以及Transistor（三极管）或是MOS的封装产品，采用焊线形成互联，由此可清楚的知道用来执行电源或是信号的金属丝会因为，导体材料的长度与截面积的变化而影响到电阻率的大小以及接触电阻的损耗，尤其是应用在功率方面的产品影响更是明显。 2), resistivity (Resistivity): We all know that resistivity (resistivity) is a physical quantity used to express the resistance characteristics of various substances. In the case of a certain temperature, there is a formula R=ρl/s where ρ is the resistivity, l is the length of the material, and s is the area. It can be seen that the resistance of a material is proportional to its length and inversely proportional to its area. The definition of resistivity can be known from the above formula: ρ=Rs/l. Traditional Diode (secondary tube) and Transistor (transistor) or MOS packaging products are interconnected by bonding wires, so it is clear that the metal wire used to perform power or signal will be due to the length of the conductor material and The change of cross-sectional area affects the size of resistivity and the loss of contact resistance, especially the impact of products applied in power is more obvious.
为解决上述问题，业界对传统的Diode（二级管）以及Transistor（三极管）或是MOS的封装产品进行了改进，用金属带、金属夹板代替焊线，来降低封装电阻、电感与期望改善热消散的能力。 In order to solve the above problems, the industry has improved the traditional Diode (secondary tube) and Transistor (transistor) or MOS packaging products, using metal strips and metal splints instead of welding wires to reduce package resistance, inductance and expect to improve thermal performance. ability to dissipate.
如图1所示，为一种现有的MOS封装结构，此结构中引线框11包含管芯焊盘和引脚，在引线框11的管芯焊盘上植入第一芯片12、第二芯片13。第一芯片12的源极通过第一金属夹板14电耦合至引线框11，第一芯片12的栅极通过第一金属焊线16电耦合至引线框11。第二芯片13的源极通过第二金属夹板15电耦合至引线框11，第二芯片13的栅极通过第二金属焊线17电耦合至引线框11。再进行包封、切割、测试等后续工序。此MOS封装结构用金属夹板取代了传统MOS封装中的焊线，降低了部分封装电阻，但是还是存在以下缺陷： As shown in Figure 1, it is a kind of existing MOS package structure, and lead frame 11 comprises die pad and pin in this structure, implants first chip 12, second chip 12 on the die pad of lead frame 11. Chip 13. The source of the first chip 12 is electrically coupled to the lead frame 11 through the first metal splint 14 , and the gate of the first chip 12 is electrically coupled to the lead frame 11 through the first metal bonding wire 16 . The source of the second chip 13 is electrically coupled to the lead frame 11 through the second metal splint 15 , and the gate of the second chip 13 is electrically coupled to the lead frame 11 through the second metal bonding wire 17 . Follow-up processes such as encapsulation, cutting, and testing are then carried out. This MOS package structure replaces the bonding wires in the traditional MOS package with a metal splint, which reduces part of the package resistance, but still has the following defects:
1.)此MOS封装结构中芯片的漏极、源极和栅极与引线框形成互联分别要用到不同的设备，制程复杂，设备的购置成本较高。 1.) In this MOS package structure, different devices are required to form the interconnection between the drain, source and gate of the chip and the lead frame, the manufacturing process is complicated, and the purchase cost of the device is high.
2.)此MOS封装结构在把金属夹板和金属焊线耦合至芯片和引脚上时，只能一颗颗芯片进行，无法整条一体成型，制造效率较低。 2.) In this MOS packaging structure, when the metal splint and metal bonding wire are coupled to the chip and the pin, it can only be carried out one by one, and the whole piece cannot be integrally formed, and the manufacturing efficiency is low.
3.)此MOS封装的内外引脚不是一体形成，而是通过焊料焊接而成，所以内外引脚结合处（即金属夹板、金属带与引线框接触处）仍存在较高的接触电阻。 3.) The internal and external pins of this MOS package are not integrally formed, but welded by solder, so there is still a high contact resistance at the junction of the internal and external pins (that is, the contact between the metal splint, the metal strip and the lead frame).
4.)使用金属夹板耦合于芯片和金属引脚上时，因其芯片板图不同或是芯片面积不同时，金属夹板以及金属夹板的冲切与搬运模具和机构，就必须要重新设计、重新制造，而这些变更往往会造成购置金钱的浪费、重新架构时间成本的浪费、商机成本的浪费以及人员配置的浪费。 4.) When using a metal splint to couple to the chip and the metal pin, because of the different chip board or chip area, the metal splint and the punching and handling mold and mechanism of the metal splint must be redesigned and redesigned. Manufacturing, and these changes often result in waste of purchase money, waste of re-architecting time costs, waste of business opportunity costs, and waste of staffing.
5.)使用金属夹板耦合于芯片和金属引脚上时，因其金属夹板非常小在生产冲切、搬运以及在焊接过程中，常常发生金属夹板运输时掉落、焊接时倾倒以及焊接不良，倒致良率与可靠性的受损。 5.) When using a metal splint to couple to the chip and metal pins, because the metal splint is very small, during the production punching, handling and welding process, the metal splint often falls during transportation, falls during welding, and poor welding. This leads to loss of yield and reliability.
发明内容 Contents of the invention
本发明所要解决的技术问题是针对上述现有技术提供一种部分框架外露多芯片平铺夹芯封装结构及其工艺方法，整条产品可一体成型，生产效率高，工艺简单，可降低成本，并且具有较好的散热性和较低的封装电阻和电感。 The technical problem to be solved by the present invention is to provide a partial frame exposed multi-chip tiled sandwich packaging structure and its process method for the above-mentioned prior art. The whole product can be integrally formed, with high production efficiency, simple process, and can reduce costs. And it has better heat dissipation and lower package resistance and inductance.
本发明解决上述问题所采用的技术方案为：一种部分框架外露多芯片平铺夹芯封装结构，它包括第一引线框、第二引线框、第三引线框、第一芯片和第二芯片，所述第二引线框和第三引线框呈Z形，所述Z形的第二引线框包括第一上水平段、第一中间连接段和第一下水平段，所述Z形的第三引线框包括第二上水平段、第二中间连接段和第二下水平段，所述第一芯片夹设在第一引线框与第一上水平段之间，所述第一芯片的正面和背面分别通过锡膏与第一上水平段和第一引线框电性连接，所述第二芯片夹设在第一下水平段与第二上水平段之间，所述第二芯片的正面和背面分别通过锡膏与第二上水平段和第一下水平段电性连接，所述第一引线框、第二引线框和第三引线框外包封有塑封料，所述第一引线框下表面、第一下水平段下表面和第二下水平段下表面齐平且均暴露在塑封料之外，所述第一上水平段上表面和第二上水平段上表面不齐平，所述第一上水平段上表面或第二上水平段上表面暴露在塑封料之外。 The technical solution adopted by the present invention to solve the above problems is: a multi-chip tiled sandwich packaging structure with part of the frame exposed, which includes a first lead frame, a second lead frame, a third lead frame, a first chip and a second chip , the second lead frame and the third lead frame are Z-shaped, the Z-shaped second lead frame includes a first upper horizontal section, a first intermediate connection section and a first lower horizontal section, and the Z-shaped first The three lead frames include a second upper horizontal section, a second intermediate connection section and a second lower horizontal section, the first chip is sandwiched between the first lead frame and the first upper horizontal section, the front side of the first chip and the back side are respectively electrically connected to the first upper horizontal section and the first lead frame through solder paste, the second chip is sandwiched between the first lower horizontal section and the second upper horizontal section, and the front side of the second chip and the back side are respectively electrically connected to the second upper horizontal section and the first lower horizontal section through solder paste, the first lead frame, the second lead frame and the third lead frame are encapsulated with a plastic encapsulant, and the first lead frame The lower surface, the lower surface of the first lower horizontal section, and the lower surface of the second lower horizontal section are flush and exposed to the plastic encapsulant, and the upper surface of the first upper horizontal section and the upper surface of the second upper horizontal section are not flush, The upper surface of the first upper horizontal section or the upper surface of the second upper horizontal section is exposed outside the molding compound.
所述第一引线框、第二引线框和第三引线框均为整体框架。 The first lead frame, the second lead frame and the third lead frame are all integral frames.
一种部分框架外露多芯片平铺夹芯封装结构的工艺方法，所述方法包括如下步骤： A process method for a multi-chip tiled sandwich packaging structure with a part of the frame exposed, the method includes the following steps:
步骤一、提供第一引线框； Step 1, providing a first lead frame;
步骤二、在第一引线框基岛区域通过网板印刷的方式涂覆锡膏； Step 2, coating solder paste on the base island area of the first lead frame by screen printing;
步骤三、在步骤二中第一引线框基岛区域涂覆的锡膏上植入第一芯片； Step 3, implanting the first chip on the solder paste coated on the base island area of the first lead frame in step 2;
步骤四、提供第二引线框，所述第二引线框为Z形，所述Z形的第二引线框包括第一上水平段、第一中间连接段和第一下水平段； Step 4, providing a second lead frame, the second lead frame is Z-shaped, and the Z-shaped second lead frame includes a first upper horizontal section, a first intermediate connecting section and a first lower horizontal section;
步骤五、在第二引线框的第一上水平段的下表面通过网板印刷的方式涂覆锡膏； Step 5, coating solder paste on the lower surface of the first upper horizontal section of the second lead frame by screen printing;
步骤六、将第二引线框的第一上水平段压合在第一引线框上表面的第一芯片上，压合后第一引线框和第二引线框形成整体框架，第一引线框下表面与第二引线框第一下水平段下表面齐平； Step 6. Press the first upper horizontal section of the second lead frame onto the first chip on the upper surface of the first lead frame. After pressing, the first lead frame and the second lead frame form an overall frame, and the lower part of the first lead frame The surface is flush with the lower surface of the first lower horizontal section of the second lead frame;
步骤七、将步骤六形成的整体框架上下表面用压板压住，进行回流焊； Step 7. Press the upper and lower surfaces of the overall frame formed in step 6 with a pressure plate, and perform reflow soldering;
步骤八、完成回流焊后，在第二引线框的第一下水平段的上表面通过网板印刷的方式涂覆锡膏； Step 8. After the reflow soldering is completed, apply solder paste on the upper surface of the first lower horizontal section of the second lead frame by screen printing;
步骤九、在步骤八中第二引线框的第一下水平段上表面涂覆的锡膏上植入第二芯片； Step 9, implanting a second chip on the solder paste coated on the upper surface of the first lower horizontal section of the second lead frame in step 8;
步骤十、提供第三引线框，所述第三引线框为Z形，所述Z形的第三引线框包括第二上水平段、第二中间连接段和第二下水平段； Step 10, providing a third lead frame, the third lead frame is Z-shaped, and the Z-shaped third lead frame includes a second upper horizontal section, a second intermediate connection section and a second lower horizontal section;
步骤十一、在第三引线框的第二上水平段的下表面通过网板印刷的方式涂覆锡膏； Step eleven, coating solder paste on the lower surface of the second upper horizontal section of the third lead frame by screen printing;
步骤十二、将第三引线框的第二上水平段压合在第二引线框的第一下水平段上表面的第二芯片上，压合后第一引线框、第二引线框和第三引线框形成整体框架，第一引线框下表面、第二引线框第一下水平段下表面与第三引线框第二下水平段下表面齐平； Step 12, press the second upper horizontal section of the third lead frame on the second chip on the upper surface of the first lower horizontal section of the second lead frame, after pressing the first lead frame, the second lead frame and the second lead frame The three lead frames form an overall frame, the lower surface of the first lead frame, the lower surface of the first lower horizontal section of the second lead frame and the lower surface of the second lower horizontal section of the third lead frame are flush;
步骤十三、将步骤十二形成的整体框架上下表面用压板压住，进行回流焊； Step 13, press the upper and lower surfaces of the overall frame formed in step 12 with a pressure plate, and perform reflow soldering;
步骤十四、将步骤十三经过回流焊后的整体框架采用塑封料进行塑封，塑封后第二引线框的第一上水平段上表面或第三引线框的第二上水平段上表面暴露在塑封料之外； Step 14: Plastic-encapsulate the overall frame after reflow soldering in step 13. After plastic-encapsulation, the upper surface of the first upper horizontal section of the second lead frame or the upper surface of the second upper horizontal section of the third lead frame is exposed on the other than plastic encapsulant;
步骤十五、将步骤十四完成塑封的半成品进行切割或是冲切作业，使原本阵列式塑封体，切割或是冲切独立开来，制得部分框架外露多芯片平铺夹芯封装结构。 Step 15: Cutting or punching the plastic-encapsulated semi-finished product in step 14, so that the original array-type plastic package can be cut or punched independently, and a multi-chip tiled sandwich packaging structure with part of the frame exposed is obtained.
所述第一引线框压合第二引线框形成整体框架，可以在第二引线框植入第二芯片后进行实施。 The first lead frame is pressed together with the second lead frame to form an overall frame, which can be implemented after the second lead frame is implanted into the second chip.
所述第一引线框、第二引线框和第三引线框的材质可以为合金铜材、纯铜材、铝镀铜材、锌镀铜材、镍铁合金材，也可以为其它CTE范围是8*10^-6/℃~25*10^-6/℃的导电材质。 The material of the first lead frame, the second lead frame and the third lead frame can be alloy copper material, pure copper material, aluminum-plated copper material, zinc-plated copper material, nickel-iron alloy material, or other CTE range of 8 *10^-6/℃~25*10^-6/℃ conductive material.
所述第一芯片和第二芯片为可以与金属锡结合的二极芯片、三极芯片或多极芯片。 The first chip and the second chip are two-pole chips, three-pole chips or multi-pole chips that can be combined with metal tin.
所述压板材质的热膨胀系数CTE与第一引线框、第二引线框和第三引线框材质的热膨胀系数CTE接近，其CTE范围是8*10^-6/℃~25*10^-6/℃。 The thermal expansion coefficient CTE of the pressure plate material is close to the thermal expansion coefficient CTE of the first lead frame, the second lead frame and the third lead frame material, and the CTE range is 8*10^-6/°C~25*10^-6/°C ℃.
所述步骤二、步骤五和步骤十一可通过不同机台同时进行。 The step 2, step 5 and step 11 can be carried out simultaneously by different machines.
与现有技术相比，本发明的优点在于： Compared with the prior art, the present invention has the advantages of:
1、本发明一种部分框架外露多芯片平铺夹芯封装结构的第二引线框与第三引线框直接与MOS芯片的源极和栅极形成电性连接，取代了传统MOS芯片封装中利用金属焊线形成互联的工艺，充分减少了封装电阻。同时由于引线框内脚与外脚为一体成型形成，进一步减少了封装电阻，本发明的技术可以比传统封装设计的封装电阻降低至少30%以上； 1. In the present invention, the second lead frame and the third lead frame of the exposed multi-chip tiled sandwich packaging structure are directly electrically connected to the source and gate of the MOS chip, replacing the traditional MOS chip package. Metal bonding wires form the interconnection process, which substantially reduces the package resistance. At the same time, since the inner pin and the outer pin of the lead frame are integrally formed, the packaging resistance is further reduced, and the technology of the present invention can reduce the packaging resistance by at least 30% compared with the traditional packaging design;
2、本发明一种部分框架外露多芯片平铺夹芯封装结构的第二引线框与第三引线框直接通过锡膏与MOS芯片的源极和栅极形成电性连接，完全减免了金属焊线的互联工序，完全节省了金属焊线互联工序的设备购置、工序材料等成本。且本发明的第二引线框和第三引线框都为整条一体成型的，与芯片形成电性连接也是整条一步完成，与传统金属焊线、金属片互联一个个芯片形成互联的工艺相比，工艺较为简单，生产效率有了明显的提高； 2. In the present invention, the second lead frame and the third lead frame of a multi-chip tiled sandwich packaging structure with part of the frame exposed are directly electrically connected to the source and gate of the MOS chip through solder paste, completely eliminating the need for metal soldering. The interconnection process of wires completely saves the cost of equipment purchase and process materials in the interconnection process of metal bonding wires. Moreover, the second lead frame and the third lead frame of the present invention are all integrally formed in one piece, and the electrical connection with the chip is also completed in one step, which is similar to the traditional metal bonding wire and metal sheet interconnection process of interconnecting chips. Compared with this method, the process is relatively simple, and the production efficiency has been significantly improved;
3、本发明的一种部分框架外露多芯片平铺夹芯封装结构由于芯片上下两个表面都直接与引线框相接触，芯片工作时产生的热量可通过引线框散出，且本发明的第一引线框下表面直接暴露在塑封料之外，本发明的部分框架外露多芯片平铺夹芯封装结构具有较好的散热性能；而且本发明可再依据产品功率、导热或是散热的不同自由的在引线框上外加散热器,用以进一步增加产品热消散的能力； 3. In the multi-chip tiled sandwich packaging structure with part of the frame exposed in the present invention, since the upper and lower surfaces of the chip are directly in contact with the lead frame, the heat generated when the chip is working can be dissipated through the lead frame, and the first chip of the present invention The lower surface of a lead frame is directly exposed to the plastic encapsulant, and the multi-chip tiled sandwich packaging structure with part of the frame exposed in the present invention has better heat dissipation performance; moreover, the present invention can freely A radiator is added to the lead frame to further increase the heat dissipation capability of the product;
4、本发明的一种部分框架外露多芯片平铺夹芯封装结构使用上下压板压住整体框架进行回流焊，使得框架在回流焊时不易被锡膏受热熔解后的冷却过程的凝聚所顶起，保证框架结构的总高度，防止芯片的移动或旋转，并且能确保框架暴露外脚的共面性。 4. The multi-chip tiled sandwich packaging structure with part of the frame exposed in the present invention uses upper and lower pressure plates to press the overall frame for reflow soldering, so that the frame is not easy to be jacked up by the condensation of the cooling process after the solder paste is heated and melted during reflow soldering , to ensure the overall height of the frame structure, prevent the chip from moving or rotating, and ensure the coplanarity of the exposed outer feet of the frame.
附图说明 Description of drawings
图1为一种已知的MOS封装结构示意图。 FIG. 1 is a schematic diagram of a known MOS package structure.
图2本发明制造的一种部分框架外露多芯片平铺夹芯封装结构的侧面图。 Fig. 2 is a side view of a multi-chip tiled sandwich package structure with part of the frame exposed manufactured by the present invention.
图3本发明制造的一种部分框架外露多芯片平铺夹芯封装结构的俯视图。 Fig. 3 is a top view of a multi-chip tiled sandwich packaging structure with part of the frame exposed manufactured by the present invention.
图4为本发明中第一引线框的立体视图。 Fig. 4 is a perspective view of the first lead frame in the present invention.
图5为本发明中第二引线框的立体视图。 Fig. 5 is a perspective view of the second lead frame in the present invention.
图6为本发明中第三引线框的立体视图。 Fig. 6 is a perspective view of a third lead frame in the present invention.
图7为本发明中第一引线框、第一芯片、第二引线框、第二芯片和第三引线框的分解立体示意图。 7 is an exploded perspective view of the first lead frame, the first chip, the second lead frame, the second chip and the third lead frame in the present invention.
图8（a）至图8（n）为本发明一种部分框架外露多芯片平铺夹芯封装结构工艺方法的流程图。 8( a ) to 8 ( n ) are flow charts of a process method for a multi-chip tiled sandwich packaging structure with part of the frame exposed in the present invention.
其中： in:
引线框11 Lead frame 11
第一芯片12 first chip 12
第二芯片13 second chip 13
第一金属夹板14 The first metal splint 14
第二金属夹板15 The second metal splint 15
第一金属焊线16 First metal bonding wire 16
第二金属焊线17 Second metal bonding wire 17
第一引线框21 First lead frame 21
第二引线框22 Second lead frame 22
第一上水平段221 First Upper Horizontal Section 221
第一中间连接段222 The first intermediate connection section 222
第一下水平段223 First Lower Level 223
第三引线框23 The third lead frame 23
第二上水平段231 The second upper horizontal section 231
第二中间连接段232 The second intermediate connection section 232
第二下水平段233 The second lower horizontal section 233
第一芯片24 first chip 24
第二芯片25 second chip 25
锡膏26 Solder paste 26
塑封料27。 Molding compound 27.
具体实施方式 detailed description
以下结合附图实施例对本发明作进一步详细描述。 The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.
如图8（a）~图8（n）所示，本实施例中的一种部分框架外露多芯片平铺夹芯封装结构的工艺方法，其具体工艺步骤如下： As shown in Fig. 8(a) to Fig. 8(n), a process method of a multi-chip tiled sandwich packaging structure with part of the frame exposed in this embodiment, the specific process steps are as follows:
步骤一、参见图8（a），提供第一引线框，第一引线框的材质为合金铜材、纯铜材、铝镀铜材、锌镀铜材、镍铁合金材，也可以为其它CTE范围是8*10^-6/℃~25*10^-6/℃的导电材质； Step 1, see Figure 8 (a), provide the first lead frame, the material of the first lead frame is alloy copper material, pure copper material, aluminum copper plated material, zinc plated copper material, nickel-iron alloy material, or other CTE The range is 8*10^-6/℃~25*10^-6/℃ conductive material;
步骤二、参见图8（b），在第一引线框基岛区域通过网板印刷的方式涂覆锡膏，目的是为实现后续第一芯片植入后与基岛接合，通过调整网板的厚度和开口的面积可以精确的控制锡膏的厚度、面积以及位置； Step 2, see Figure 8(b), apply solder paste on the base island area of the first lead frame by screen printing, the purpose is to realize the bonding with the base island after the first chip is implanted. Thickness and opening area can precisely control the thickness, area and position of solder paste;
步骤三、参见图8（c），在步骤二中第一引线框基岛区域涂覆的锡膏上植入第一芯片； Step 3, referring to FIG. 8(c), implanting the first chip on the solder paste coated on the base island area of the first lead frame in step 2;
步骤四、参见图8（d），提供第二引线框，所述第二引线框为Z形，所述Z形的第二引线框包括第一上水平段、第一中间连接段和第一下水平段，第二引线框的材质为合金铜材、纯铜材、铝镀铜材、锌镀铜材、镍铁合金材，也可以为其它CTE范围是8*10^-6/℃~25*10^-6/℃的导电材质； Step 4. Referring to FIG. 8(d), a second lead frame is provided. The second lead frame is Z-shaped, and the Z-shaped second lead frame includes a first upper horizontal section, a first middle connecting section and a first In the lower horizontal section, the material of the second lead frame is alloy copper, pure copper, aluminum-plated copper, zinc-plated copper, nickel-iron alloy, or other materials. The CTE range is 8*10^-6/℃~25 *10^-6/℃ conductive material;
步骤五、参见图8（e），在第二引线框的第一上水平段的下表面通过网板印刷的方式涂覆锡膏，目的是为实现后续第二引线框的引脚与第一芯片正面形成电性连接，通过调整网板的厚度和开口的面积可以精确的控制锡膏的厚度、面积以及位置； Step 5, see Figure 8(e), apply solder paste on the lower surface of the first upper horizontal section of the second lead frame by screen printing, in order to realize the connection between the pins of the subsequent second lead frame and the first The front side of the chip forms an electrical connection, and the thickness, area and position of the solder paste can be precisely controlled by adjusting the thickness of the stencil and the area of the opening;
步骤六、参见图8（f），将第二引线框的第一上水平段压合在第一引线框上表面的第一芯片上，使第一芯片与第二引线框通过第一上水平段下表面的锡膏形成电性连接，压合后第一引线框和第二引线框形成整体框架，第一引线框下表面与第二引线框第一下水平段下表面齐平； Step 6. Referring to Figure 8(f), press the first upper horizontal section of the second lead frame onto the first chip on the upper surface of the first lead frame, so that the first chip and the second lead frame pass through the first upper level The solder paste on the lower surface of the segment forms an electrical connection, and after pressing, the first lead frame and the second lead frame form an integral frame, and the lower surface of the first lead frame is flush with the lower surface of the first lower horizontal segment of the second lead frame;
步骤七、参见图8（g），将步骤六形成的整体框架上下表面用压板压住，进行回流焊。压板的材质要求不容易发生形变且具有良好的热传导性能，其热膨胀系数CTE与第一引线框和第二引线框材质的热膨胀系数CTE接近，其CTE范围是8*10^-6/℃~25*10^-6/℃； Step 7, see Figure 8 (g), press the upper and lower surfaces of the overall frame formed in step 6 with a pressure plate, and perform reflow soldering. The material of the pressure plate is not easy to deform and has good thermal conductivity. Its thermal expansion coefficient CTE is close to the thermal expansion coefficient CTE of the first lead frame and the second lead frame material, and its CTE range is 8*10^-6/℃~25 *10^-6/℃;
步骤八、参见图8（h），完成回流焊后，在第二引线框的第一下水平段的上表面通过网板印刷的方式涂覆锡膏； Step 8. Referring to FIG. 8(h), after the reflow soldering is completed, apply solder paste on the upper surface of the first lower horizontal section of the second lead frame by screen printing;
步骤九、参见图8（i），在步骤八中第二引线框的第一下水平段上表面涂覆的锡膏上植入第二芯片； Step 9, referring to FIG. 8(i), implanting a second chip on the solder paste coated on the surface of the first lower horizontal section of the second lead frame in step 8;
步骤十、参见图8（j），提供第三引线框，所述第三引线框为Z形，所述Z形的第三引线框包括第二上水平段、第二中间连接段和第二下水平段，第三引线框的材质为合金铜材、纯铜材、铝镀铜材、锌镀铜材、镍铁合金材，也可以为其它CTE范围是8*10^-6/℃~25*10^-6/℃的导电材质； Step 10. Referring to FIG. 8(j), a third lead frame is provided, the third lead frame is Z-shaped, and the Z-shaped third lead frame includes a second upper horizontal section, a second middle connecting section and a second In the lower horizontal section, the third lead frame is made of alloy copper, pure copper, aluminum-plated copper, zinc-plated copper, nickel-iron alloy, or other materials. The CTE range is 8*10^-6/℃~25 *10^-6/℃ conductive material;
步骤十一、参见图8（k），在第三引线框的第二上水平段的下表面通过网板印刷的方式涂覆锡膏，目的是为实现后续第三引线框的引脚与第二芯片正面形成电性连接，通过调整网板的厚度和开口的面积可以精确的控制锡膏的厚度、面积以及位置； Step 11. Referring to FIG. 8(k), apply solder paste on the lower surface of the second upper horizontal section of the third lead frame by screen printing, so as to realize the connection between the pins of the third lead frame and the second lead frame. The front side of the two chips is electrically connected, and the thickness, area and position of the solder paste can be precisely controlled by adjusting the thickness of the stencil and the area of the opening;
步骤十二、参见图8（l），将第三引线框的第二上水平段压合在第二引线框的第一下水平段上表面的第二芯片上，使第二芯片与第三引线框通过第二上水平段下表面的锡膏形成电性连接，压合后第一引线框、第二引线框和第三引线框形成整体框架，第一引线框下表面、第二引线框第一下水平段下表面与第三引线框第二下水平段下表面齐平； Step 12. Referring to FIG. 8(l), press the second upper horizontal section of the third lead frame onto the second chip on the upper surface of the first lower horizontal section of the second lead frame, so that the second chip and the third The lead frame is electrically connected through the solder paste on the lower surface of the second upper horizontal section. After pressing, the first lead frame, the second lead frame and the third lead frame form an overall frame. The lower surface of the first lead frame and the second lead frame The lower surface of the first lower horizontal section is flush with the lower surface of the second lower horizontal section of the third lead frame;
步骤十三、参见图8（m），将步骤十二形成的整体框架上下表面用压板压住，进行回流焊。压板的材质要求不容易发生形变且具有良好的热传导性能，其热膨胀系数CTE与第一引线框、第二引线框和第三引线框材质的热膨胀系数CTE接近，其CTE范围是8*10^-6/℃~25*10^-6/℃； Step 13, see Figure 8 (m), press the upper and lower surfaces of the overall frame formed in step 12 with a pressure plate, and perform reflow soldering. The material of the pressure plate is not easy to deform and has good thermal conductivity. Its thermal expansion coefficient CTE is close to the thermal expansion coefficient CTE of the first lead frame, the second lead frame and the third lead frame material, and its CTE range is 8*10^- 6/℃~25*10^-6/℃;
步骤十四、参见图8（n），将步骤十三经过回流焊后的整体框架采用塑封料进行塑封，塑封后第二引线框的第一上水平段上表面或第三引线框的第二上水平段上表面暴露在塑封料之外； Step 14. Referring to Figure 8(n), the overall frame after reflow soldering in step 13 is plastic-sealed with a plastic encapsulant. After plastic sealing, the upper surface of the first upper horizontal section of the second lead frame or the second The upper surface of the upper horizontal section is exposed to the plastic encapsulant;
步骤十五、将步骤十四完成塑封的半成品进行切割或是冲切作业，使原本阵列式塑封体，切割或是冲切独立开来，制得部分框架外露多芯片平铺夹芯封装结构。 Step 15: Cutting or punching the plastic-encapsulated semi-finished product in step 14, so that the original array-type plastic package can be cut or punched independently, and a multi-chip tiled sandwich packaging structure with part of the frame exposed is obtained.
上述步骤中，步骤六与步骤七第一引线框压合第二引线框形成整体框架并使用压板进行回流焊，可以在步骤九第二引线框植入第二芯片后进行实施。 In the above steps, step 6 and step 7, where the first lead frame is pressed to the second lead frame to form an overall frame, and the press plate is used for reflow soldering, can be implemented after the second lead frame is implanted into the second chip in step 9.
上述步骤中，步骤二、步骤五和步骤十一可通过不同机台同时进行。 Among the above steps, step 2, step 5 and step 11 can be performed simultaneously by different machines.
参见图2~图7，本发明一种部分框架外露多芯片平铺夹芯封装结构，它包括第一引线框21、第二引线框22、第三引线框23、第一芯片24和第二芯片25，所述第二引线框22和第三引线框23呈Z形，所述Z形的第二引线框22包括第一上水平段221、第一中间连接段222和第一下水平段223，所述Z形的第三引线框23包括第二上水平段231、第二中间连接段232和第二下水平段233，所述第一芯片24夹设在第一引线框21与第一上水平段221之间，所述第一芯片24的正面和背面分别通过锡膏26与第一上水平段221和第一引线框21电性连接，所述第二芯片25夹设在第一下水平段223与第二上水平段231之间，所述第二芯片25的正面和背面分别通过锡膏26与第二上水平段231和第一下水平段223电性连接，所述第一引线框21、第二引线框22和第三引线框23外包封有塑封料27，所述第一引线框21下表面、第一下水平段223下表面和第二下水平段233下表面齐平且均暴露在塑封料27之外，所述第一上水平段221上表面和第二上水平段231上表面不齐平，所述第一上水平段221上表面或第二上水平段231上表面暴露在塑封料27之外。 Referring to Fig. 2 ~ Fig. 7, the present invention is a multi-chip tiled sandwich packaging structure with part of the frame exposed, which includes a first lead frame 21, a second lead frame 22, a third lead frame 23, a first chip 24 and a second lead frame Chip 25, the second lead frame 22 and the third lead frame 23 are Z-shaped, and the Z-shaped second lead frame 22 includes a first upper horizontal section 221, a first intermediate connection section 222 and a first lower horizontal section 223, the Z-shaped third lead frame 23 includes a second upper horizontal section 231, a second intermediate connection section 232 and a second lower horizontal section 233, and the first chip 24 is sandwiched between the first lead frame 21 and the second Between an upper horizontal section 221, the front and the back of the first chip 24 are electrically connected to the first upper horizontal section 221 and the first lead frame 21 respectively through solder paste 26, and the second chip 25 is sandwiched between the first upper horizontal section 221 and the first lead frame 21. Between the lower horizontal section 223 and the second upper horizontal section 231, the front and back sides of the second chip 25 are electrically connected to the second upper horizontal section 231 and the first lower horizontal section 223 respectively through solder paste 26, the The first lead frame 21, the second lead frame 22 and the third lead frame 23 are encapsulated with a molding compound 27, the lower surface of the first lead frame 21, the lower surface of the first lower horizontal section 223 and the lower surface of the second lower horizontal section 233 The surfaces are flush and exposed outside the molding compound 27, the upper surface of the first upper horizontal section 221 and the upper surface of the second upper horizontal section 231 are not flush, and the upper surface of the first upper horizontal section 221 or the second upper surface The upper surface of the horizontal section 231 is exposed outside the molding compound 27 .
所述第一引线框21、第二引线框22和第三引线框23均为整体框架，其材质可以为合金铜材、纯铜材、铝镀铜材、锌镀铜材、镍铁合金材，也可以为其它CTE范围是8*10^-6/℃~25*10^-6/℃的导电材质。 The first lead frame 21, the second lead frame 22 and the third lead frame 23 are all integral frames, and their materials can be alloy copper, pure copper, aluminum-plated copper, zinc-plated copper, nickel-iron alloy, It can also be other conductive materials with a CTE range of 8*10^-6/℃~25*10^-6/℃.
所述第一芯片24和第二芯片25为可以与金属锡结合的二极芯片、三极芯片或多极芯片。 The first chip 24 and the second chip 25 are two-pole chips, three-pole chips or multi-pole chips that can be combined with metal tin.
除上述实施例外，本发明还包括有其他实施方式，凡采用等同变换或者等效替换方式形成的技术方案，均应落入本发明权利要求的保护范围之内。 In addition to the above-mentioned embodiments, the present invention also includes other implementations, and any technical solution formed by equivalent transformation or equivalent replacement shall fall within the protection scope of the claims of the present invention.
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