CN105280644B - One-time programming memory cell, array structure and operation method thereof - Google Patents

Abstract

A one-time programmable memory cell, array structure and operation method thereof. The one-time programmable memory cell includes: a transistor, a first varactor, and a second varactor. The transistor has a gate, a source and a drain. The gate is connected to a word line. The source is connected to a bit line. The first end of the first variable capacitor is connected to the drain of the transistor, and the second end of the first variable capacitor is connected to the first programming line. The second varactor has a first terminal connected to the drain of the transistor and a second terminal connected to a second program line.

Description

One-time programmed memory cell and its array structure and operation method

technical field

The present invention relates to a non-volatile memory, and in particular to a one time programming memory cell and its array structure and operation method.

Background technique

It is well known that non-volatile memory can retain its data content after power failure. Generally speaking, after the non-volatile memory is manufactured and leaves the factory, the user can program the non-volatile memory, and then record data in the non-volatile memory.

According to the number of programming times, non-volatile memory can be further divided into: multi-time programming memory (MTP memory for short), one-time programming memory (OTP memory for short) or mask type Read-only memory (Mask ROM memory).

Basically, users can program the MTP memory multiple times to modify the stored data multiple times. The user can only program the OTP memory once, and once the programming of the OTP memory is completed, the stored data cannot be modified. After the Mask ROM memory leaves the factory, all stored data has been recorded in it, and the user can only read the stored data in the MaskROM memory, but cannot program it.

Furthermore, the OTP memory can be divided into fuse type (fuse type) OTP memory and anti-fuse type (anti-fuse type) OTP memory according to its characteristics. When the memory cell (memory cell, also known as "memory cell") of the fuse type OTP memory has not been programmed (program), it is in a storage state of low resistance value; after programming, the memory cell has a high resistance The storage state of the value.

When the memory cell of the anti-fuse OTP memory has not been programmed, it has a storage state of high resistance; and after programming, the memory cell has a storage state of low resistance.

With the evolution of semiconductor technology, the technology of OTP memory is already compatible with the semiconductor technology of CMOS. With the continuous improvement of CMOS semiconductor technology, it is more necessary to improve the structure of the OTP memory so that the OTP memory has more reliable performance.

Contents of the invention

The main purpose of the present invention is to propose a programmed memory cell (memory cell, also referred to as "storage unit") and its array structure and operation method, in order to achieve 100% backup (in-cell 100% redundancy) in the memory cell Effect.

The invention relates to a one-time programming memory cell, comprising: a P-type substrate; a first gate structure formed on a surface of the P-type substrate and connected to a word line; a second gate structure, formed on the surface of the P-type substrate and connected to a first programming line; a third gate structure formed on the surface of the P-type substrate and connected to a second programming line; a first N-type diffusion region, formed under the surface of the P-type substrate and adjacent to a first side of the first gate structure, and the first N-type diffusion region is connected to a bit line; a second N-type diffusion region Diffusion region, formed under the surface of the P-type substrate and adjacent to a second side of the first gate structure, a first side of the second gate structure, a first side of the third gate structure One side; wherein, the channel region below the second gate structure is a first N-type doped channel region, the channel region below the third gate structure is a second N-type doped channel region, and the second The gate structure, the first N-type doped channel region and the second N-type diffusion region form a first varactor; the third gate structure, the second N-type doped channel region and the second N-type The diffusion region forms a second varactor; and, the first gate structure, the P-type substrate, the first N-type diffusion region and the second N-type diffusion region form a transistor.

The invention relates to a one-time programming memory cell, comprising: a transistor with a gate connected to a word line, a source connected to a bit line, and a drain; a first varactor with a first terminal connected to the drain of the transistor, having a second terminal connected to a first programming line; and a second varactor, having a first terminal connected to the drain of the transistor, having a second terminal connected to a second programming line.

The present invention relates to an array structure, comprising: a first programmed memory cell, comprising: a first transistor having a source, a drain connected to a first bit line, and a gate connected to a first bit line a word line; a first varactor having a first end connected to the source of the first transistor, a second end connected to the first programming line; and a second varactor having a first end connected to the source of the first transistor, a second terminal connected to the second programming line; and a second once-programmed memory cell, comprising: a second transistor having a source connected to a drain To the first bit line, a gate is connected to a second word line; a third varactor has a first end connected to the source of the second transistor, and a second end connected to the first programming line; and a fourth varactor having a first terminal connected to the source of the second transistor and a second terminal connected to the second programming line.

The present invention relates to an operation method of the above-mentioned array structure, comprising the following steps: entering a first programming cycle, changing the first varactor in the memory cell of the first programming into a first resistor; entering A confirmation cycle, reading a first read current generated by the memory cell of the first programming, and judging whether the memory cell of the first programming is a failure memory cell; and after confirming the first When the memory cell programmed for the first time is the failed memory cell, a second programming cycle is entered, and the second varactor in the memory cell programmed for the first time is changed to a second resistor.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the preferred embodiments are specifically cited below, together with the accompanying drawings, and are described in detail as follows:

Description of drawings

1A to 1D illustrate the first embodiment of the OTP memory cell of the present invention.

2A to 2C illustrate the second embodiment of the OTP memory cell of the present invention.

FIG. 3 shows a third embodiment of the OTP memory cell of the present invention.

FIG. 4 shows the fourth embodiment of the OTP memory cell of the present invention.

FIG. 5 is a schematic diagram of related control signals when programming an OTP memory cell.

FIG. 6A and FIG. 6B are schematic diagrams of related control signals for reading programmed memory cells and unprogrammed memory cells.

7A and FIG. 7B are schematic diagrams showing control signals related to remedial failed memory cells and read rescued memory cells.

FIG. 8A and FIG. 8B are diagrams showing an array structure composed of OTP memory cells according to the first embodiment of the present invention.

9A to 9C illustrate the process of programming OTP memory cells C00, C11, and C02 during the first programming cycle.

FIG. 10A to FIG. 10C show the process of reading all OTP memory cells during the confirmation cycle.

FIG. 11 is a flow chart of repairing programming failed memory cells during the second programming cycle.

Fig. 12 is a flowchart of the operation method of the array structure of the present invention.

FIG. 13 is a top view of an array structure according to another embodiment of the present invention.

【Symbol Description】

100: OTP memory cell

110: P-type well area

111, 121, 131: gate oxide layer

112, 122, 132: polysilicon gate

141, 142: N-type diffusion region

151, 152, 153, 154: touch points

242: N-type expansion area

342: N-type well area

442: N-type implantation area

800: array structure

S1210～S1216: Step flow

BL, BL0: bit line

WL, WL0, WL1, WL2: word lines

PL1: first programming line

PL2: second programming line

Detailed ways

Please refer to FIG. 1A to FIG. 1D , which illustrate a first embodiment of an OTP memory cell (memory cell, also referred to as a “storage unit”) of the present invention. Wherein, FIG. 1A is a perspective view of the first embodiment; FIG. 1B is a top view of the first embodiment; FIG. 1C is a cross-sectional view of the first embodiment in a1 and a2 directions; and, FIG. 1D is an equivalent of the first embodiment circuit diagram.

The OTP memory cell 100 has a substrate with a P-well region 110 . A first gate structure, a second gate structure, and a third gate structure are formed above the P-type well region 110 . Wherein, the first gate structure includes a gate oxide layer 111 and a first polysilicon gate 112 above it; the second gate structure includes a gate oxide layer 121 and a second polysilicon gate 122 above it; And the third gate structure includes a gate oxide layer 131 and a third polysilicon gate 132 thereon.

As shown in FIG. 1B , after the three gate structures are used as masks and the ion implantation process is performed, a first N-type diffusion region 141 and a second N-type diffusion region 142 are formed on the substrate of the P-type well region 110 . Wherein, the first N-type diffusion region 141 is adjacent to one side of the first gate structure; the second N-type diffusion region 142 is adjacent to the other side of the first gate structure. Furthermore, the first contact point 151 is formed on the first N-type diffusion region 141; the second contact point 152 is formed on the first polysilicon gate 112; the third contact point 153 is formed on the second polysilicon gate 122 ; and the fourth contact point 154 is formed on the third polysilicon gate 132 .

As shown in FIG. 1C, during the metal process step, the first contact point 151 is connected to a bit line BL (bit line); the second contact point 152 is connected to a word line WL (word line); the third contact point 153 connected to a first program line PL1; and, the fourth contact point 154 is connected to a second program line PL2.

Furthermore, it can be seen from FIG. 1C that the first N-type diffusion region 141, the first gate structure and the second N-type diffusion region 142 form an N-type transistor (NMOS transistor) T; the second gate structure and the second N-type The diffusion region 142 forms an N-type capacitor (NMOS capacitor) C. Similarly, the third gate structure and the second N-type diffusion region 142 form another N-type capacitor (not shown) C'.

It can be seen from the drawing of FIG. 1D that the gate of the N-type transistor T is connected to the word line WL, the first N-type diffusion region 141 of the N-type transistor T is connected to the bit line BL, and the second N-type diffusion region of the N-type transistor T is connected to the word line WL. 142 is connected to the first ends of the N-type capacitor C and another N-type capacitor C′. A second end of the N-type capacitor C is connected to the first programming line PL1, and a second end of the other N-type capacitor C' is connected to the second programming line PL2.

As shown in FIG. 1C, in the two N-type capacitors C and C', the channel region (channel region) under the second gate structure and the third gate structure is a P-type well region 110, so it is necessary to provide an appropriate forward bias After the positive bias voltage is applied to the second gate structure and the third gate structure, the two N-type capacitors C and C′ become capacitors with capacitance values.

Due to the advancement of semiconductor technology, after the OTP memory cell of the first embodiment is completed, the channel elimination step can be further used to change the two N-type capacitors C, C' into two variable capacitors (Varactor). Wherein, the channel elimination step may be a source/drain expansion step, a well formation step, or an ion implantation step. That is, an N-type doped channel region (N-type doped channel region) is formed under the second gate structure and the third gate structure. It is described in detail below.

Please refer to FIG. 2A to FIG. 2C , which illustrate the second embodiment of the OTP memory cell of the present invention. Wherein, FIG. 2A is a top view of the second embodiment; FIG. 2B is a cross-sectional view of the second embodiment along directions a1 and a2; and FIG. 2C is an equivalent circuit diagram of the second embodiment. Wherein, the perspective view of the second embodiment is the same as that of the first embodiment, and will not be repeated here.

Due to the advancement of semiconductor technology, after the OTP memory cell of the first embodiment is completed, the region of the N-type transistor T is covered earlier, and the source/drain extension process (source/drain extension process) is performed in the region of the N-type capacitor C ). Therefore, as shown in FIG. 2B , when the source/drain extension step is performed, an N-type extension region 242 is formed in the channel region under the second gate structure. Generally, when the length of the P-type channel is less than 40 nm, the two N-type extension regions 242 will merge together, which will make the P-type channel region disappear and form the varactor Va. As shown in FIG. 2B , the second gate structure does not need to provide any bias voltage, and the varactor Va has a varactor value. Similarly, the third gate structure and the two N-type extension regions 242 also form another varactor Va' (not shown). Furthermore, after programming, the performance of the anti-fuse OTP memory cell composed of varactors is better than that of the anti-fuse OTP memory cell composed of N-type capacitors.

Similarly, as shown in FIG. 2C , the gate of the N-type transistor T is connected to the word line WL, the first N-type diffusion region 141 of the N-type transistor T is connected to the bit line BL, and the second N-type diffusion region 141 of the N-type transistor T is connected to the bit line BL. The type diffusion region 142 is connected to the first ends of the varactor Va and another varactor Va'. The second end of the varactor Va is connected to the first programming line PL1, and the second end of the other varactor Va' is connected to the second programming line PL2.

Please refer to FIG. 3 , which shows a third embodiment of the OTP memory cell of the present invention. Wherein, the top view and equivalent circuit diagram of the third embodiment are the same as those of the second embodiment, and will not be repeated here.

After the OTP memory cell of the first embodiment is completed, the area of the N-type transistor T is first covered, and an N-well forming process is performed in the area of the N-type capacitor. Therefore, as shown in FIG. 3 , after the step of forming the N-type well region, an N-type well region 342 will be formed in the channel region under the second gate structure, and the P-type channel region will disappear to form a varactor Va. Similarly, an N-type well region 342 is also formed in the channel region below the third gate structure, and the P-type channel region disappears to form another varactor Va' (not shown).

Please refer to FIG. 4 , which shows a fourth embodiment of the OTP memory cell of the present invention. Wherein, the top view and equivalent circuit diagram of the fourth embodiment are the same as those of the second embodiment, and will not be repeated here.

After the OTP memory cell of the first embodiment is completed, the area of the N-type transistor T is covered first, and an N-type ion implanting process is performed in the area of the N-type capacitor. Therefore, as shown in FIG. 4 , after the N-type ion implantation step, an N-type implanted region 442 is formed in the P-type channel region under the second gate structure, and the P-type channel region disappears to form a varactor Va. Similarly, another N-type implanted region is formed in the channel region under the third gate structure, and the P-type channel region disappears to form another varactor Va' (not shown).

Please refer to FIG. 5 , which is a schematic diagram of related control signals when programming an OTP memory cell. During the programming period, when the OTP memory cell is a selected memory cell, Vdd is supplied to the word line WL, 0V is supplied to the bit line BL, Vpp is supplied to one programming line, and Vdd is supplied to the other programming line. For example, Vpp is supplied to the first programming line PL1, and Vdd is supplied to the second programming line PL2. Wherein, Vpp can be set as 6V, and Vdd is between 1V and 2.8V.

Take Figure 5 as an example for illustration. During the programming period, the voltage difference between the two ends of the variable capacitor Va is Vpp, so that the gate oxide layer of the variable capacitor Va is broken (rupture) to form a resistor Rva with a low resistance value; moreover, the voltage across the variable capacitor Va' The difference is Vdd, which is still in the withstand voltage range, and the gate oxide layer of the varactor Va' will not be broken.

After the programming cycle, the selected memory cell becomes a programmed memory cell, which has a low resistance resistor Rva. On the contrary, the unselected memory cells become non-programmed memory cells, and the gate oxide layers in the varactors Va and Va' are not ruptured, which can be regarded as high-resistance Variable container Va and Va'.

Please refer to FIG. 6A and FIG. 6B , which are schematic diagrams of related control signals for reading programmed memory cells and unprogrammed memory cells. During the reading period, Vdd is provided to the word line WL, 0V is provided to the bit line BL, and Vdd is provided to the two programming lines PL1 and PL2.

As shown in FIG. 6A , when the selected memory cell is a programmed memory cell, its bit line BL generates a relatively large read current Ir. On the contrary, as shown in FIG. 6B, when the selected memory cell is an unprogrammed memory cell, its bit line BL will generate a small read current Ir, and the read current Ir is about 0A. Therefore, the storage state of the OTP memory cell can be judged according to the magnitude of the read current Ir. For example, when the read current Ir is greater than the reference current, the memory cell is in the first storage state; when the read current Ir is smaller than the reference current, the memory cell is in the second storage state.

Furthermore, during the programming cycle, if the gate oxide layer of the selected memory cell cannot be successfully broken, it will cause a program fail and become a fail memory cell. At this time, the failed memory cell still has a high resistance value. Therefore, when the failed memory cell is read, the read current Ir is too low, which will lead to misjudgment.

Since the OTP memory cell of the present invention has two varactors, it is possible to remedy the failed memory cell in the reprogramming cycle (the second programming cycle). Please refer to FIG. 7A and FIG. 7B , which are schematic diagrams of related control signals for remediating a failed memory cell and reading a remedied memory cell. As shown in FIG. 7A , when the OTP memory cell is identified as a failed memory cell, the OTP memory cell has a resistor Rva with a high resistance value.

When performing a reprogramming cycle (the second programming cycle), select the failed memory cell as the selected memory cell, and provide Vdd to the word line WL, 0V to the bit line BL, Vpp to the second programming line PL2, and Vdd to the first programming line PL1. At this time, the voltage difference between the two ends of the varactor Va' is Vpp, so that the gate oxide layer of the varactor Va' is broken to form a resistor Rva' with a low resistance value. After the programming cycle, the selected memory cell becomes the programmed memory cell, which has a low resistance resistor Rva'.

As shown in FIG. 7B , during the read cycle, when the programmed memory cell is read again, Vdd is provided to the word line WL, 0V is provided to the bit line BL, and Vdd is provided to the two programming lines PL1 and PL2 . Therefore, the bit line BL generates a large read current Ir, and it can be confirmed that the memory cell is in the first storage state.

It can be seen from the above description that the OTP memory cell disclosed in the present invention includes two varactors, so the effect of in-cell 100% redundancy can be achieved.

Please refer to FIG. 8A and FIG. 8B , which show an array structure composed of OTP memory cells according to the first embodiment of the present invention. 8A is a top view of the layout of the first embodiment of the array structure; FIG. 8B is an equivalent circuit diagram of the array structure.

As shown in FIG. 8A , each dotted box represents an OTP memory cell. Same as FIG. 2A , each OTP memory cell has two N-type diffusion regions, a first gate structure, a second gate structure, and a third gate structure. Taking the OTP memory cell C00 as an example, the first polysilicon gate of the first gate structure can be connected to the word line WL0; the second polysilicon gate of the second gate structure can be connected to the first programming line PL1; And the third polysilicon gate of the third gate structure may be connected to the second programming line PL2.

Taking the OTP memory cells C00, C10, and C20 as an example, the first polysilicon gates of the first gate structure are all connected together and connected to the word line WL0. Moreover, the second polysilicon gates of OTP memory cells C00 and C10 are connected together and connected to the first programming line PL1; and the third polysilicon gates of OTP memory cells C10 and C20 are connected together and connected to The second programming line PL2.

After the structure of FIG. 8A is completed, a channel elimination step, such as a source/drain expansion step, a well formation step, or an ion implantation step, is required to integrate the second gate structure with the third gate structure. The channel is eliminated and a varactor is formed. That is, an N-type doped channel region is formed under the second gate structure and the third gate structure, thereby forming the array structure of the present invention.

As shown in FIG. 8B , the array structure 800 includes a plurality of OTP memory cells C00-C12, and each OTP memory cell includes an N-type transistor T and two varactors Va and Va'. Wherein, the first ends of the two varactors Va and Va' are connected to the drain of the N-type transistor T, the second end of the first varactor Va is connected to the first programming line PL1, and the second end of the second varactor Va' Connect to the second programming line PL2.

N-type transistor T gates in OTP memory cells C00 and C10 are connected to word line WL0; N-type transistor T gates in OTP memory cells C01 and C11 are connected to word line WL1; N-type transistors in OTP memory cells C02 and C12 The gate of transistor T is connected to word line WL2. Furthermore, the sources of the N-type transistors in the OTP memory cells C00, C01 and C02 are connected to the bit line BL0; the sources of the N-type transistors in the OTP memory cells C10, C11 and C12 are connected to the bit line BL1. Of course, the array structure of the present invention is not limited to 2×3 OTP memory cells, and those skilled in the art can expand it to an array structure composed of m×n OTP memory cells according to the contents of FIG. 8A to FIG. 8B . And m and n are any positive integers.

According to an embodiment of the present invention, during the first programming cycle, Vpp is provided to the first programming line PL1, and Vdd is provided to the second programming line PL2; during the second programming cycle, Vdd is provided to the first programming line PL1, Vpp is supplied to the second programming line PL2. Furthermore, when the word line WL of the OTP memory cell receives Vdd and the bit line BL receives 0V, the OTP memory cell is the selected memory cell.

The process of programming OTP memory cells C00, C11, and C02 in the first programming cycle will be described below by taking FIG. 9A to FIG. 9C as an example. Wherein, Vpp can be set as 6V, and Vdd is between 1V and 2.8V.

As shown in FIG. 9A, Vdd is supplied to the word line WL0, and 0V is supplied to the word lines WL1 and WL2. And, 0V is supplied to the bit line BL0, and Vdd is supplied to the bit line BL1. Therefore, the OTP memory cell C00 is the selected memory cell, and the other OTP memory cells are the non-selected memory cells. As shown in FIG. 9A for the OTP memory cell C00, the varactor Va becomes a resistor Rva and makes the OTP memory cell C00 a programming memory cell.

As shown in FIG. 9B, Vdd is supplied to the word line WL2, and 0V is supplied to the word lines WL0 and WL1. And, 0V is supplied to the bit line BL0, and Vdd is supplied to the bit line BL1. Therefore, the OTP memory cell C02 is the selected memory cell, and the other OTP memory cells are the non-selected memory cells. As for the OTP memory cell C02 shown in FIG. 9B , the varactor Va becomes a resistor Rva and makes the OTP memory cell C02 a programming memory cell.

As shown in FIG. 9C , Vdd is supplied to the word line WL1 , and 0V is supplied to the word lines WL0 and WL2 . And, Vdd is supplied to the bit line BL0, and 0V is supplied to the bit line BL1. Therefore, OTP memory cell C11 is a selected memory cell, and other OTP memory cells are non-selected memory cells. As shown in FIG. 9C for the OTP memory cell C11, the varactor Va becomes a resistor Rva and makes the OTP memory cell C11 a programming memory cell.

When the first programming cycle ends, OTP memory cells C00, C02, and C11 become programming memory cells. Therefore, a verification cycle is required to verify the storage status of the programmed memory cells. According to an embodiment of the present invention, the so-called confirmation period is to read and confirm the storage status of all OTP memory cells, so as to find out the failed memory cells.

During the confirmation cycle, Vdd is provided to the first programming line PL1 and the second programming line PL2 first. Moreover, when the word line WL of the OTP memory cell receives Vdd and the bit line BL receives 0V, the OTP memory cell is the selected memory cell and can receive the read current of the selected memory cell.

The flow of the confirmation cycle will be described below using FIGS. 10A to 10C . Among them, OTP memory cell C11 is a failure memory cell.

As shown in FIG. 10A, Vdd is supplied to the word line WL0, and 0V is supplied to the word lines WL1 and WL2. And, 0V is provided to the bit line BL0 and the bit line BL1. Therefore, OTP memory cells C00 and C10 are selected memory cells. Furthermore, since the OTP memory cell C00 generates a large read current Irc00 to the bit line BL0, it is confirmed that the OTP memory cell C00 is in the first storage state; and, since the OTP memory cell C10 does not generate a read current Irc10 (Irc10=0) To the bit line BL1, confirm that the OTP memory cell C10 is in the second storage state.

As shown in FIG. 10B , Vdd is supplied to the word line WL1 , and 0V is supplied to the word lines WL0 and WL2 . And, 0V is provided to the bit line BL0 and the bit line BL1. Therefore, OTP memory cells C01 and C11 are selected memory cells. Furthermore, since the OTP memory cell C01 does not generate the read current Irc01 (Irc01=0) to the bit line BL0, it is confirmed that the OTP memory cell C10 is in the second storage state; and, since the OTP memory cell C11 is a failed memory cell, the generated The read current Irc11 is very small, and makes the OTP memory cell C11 be misjudged as the second storage state.

As shown in FIG. 10C, Vdd is supplied to the word line WL2, and 0V is supplied to the word lines WL0 and WL1. And, 0V is provided to the bit line BL0 and the bit line BL1. Therefore, OTP memory cells C02 and C12 are selected memory cells. Furthermore, since the OTP memory cell C02 generates a large read current Irc02 to the bit line BL0, it is confirmed that the OTP memory cell C02 is in the first storage state; and, since the OTP memory cell C12 does not generate a read current Irc12 (Irc12=0) To the bit line BL1, confirm that the OTP memory cell C12 is in the second storage state.

Obviously, during the confirmation cycle, the storage state of the OTP memory cell C11 is read as the second storage state. However, since the OTP memory cell C11 should be in the first storage state, it can be confirmed that the OTP memory cell is a failed memory cell.

According to an embodiment of the present invention, when a failed memory cell is found after the validation cycle, a second programming cycle is performed. During the second programming cycle, Vdd is provided to the first programming line PL1, and Vpp is provided to the second programming line PL2. Similarly, in the second programming cycle, when the word line WL of the OTP memory cell receives Vdd and the bit line BL receives 0V, the OTP memory cell is the selected memory cell. The following uses FIG. 11 as an example to illustrate the process of repairing the failed programming memory cell during the second programming cycle. Wherein, Vpp can be set to 6V, and Vdd can be set between 1V-2.8V.

As shown in FIG. 11 , during the second programming cycle, Vdd is provided to the word line WL1 , and 0V is provided to the word lines WL0 and WL2 . And, Vdd is supplied to the bit line BL0, and 0V is supplied to the bit line BL1. Therefore, the OTP memory cell C11 is the selected memory cell, and a resistor Rva' is formed in the OTP memory cell C11 and the OTP memory cell C11 is modified from a failed memory cell to a programmed memory cell.

According to the above description, the operation method of the array structure of the present invention can be obtained. As shown in FIG. 12 , it is a flowchart of the operation method of the array structure of the present invention. First, enter the first programming cycle. That is, program the M OTP memory cells in the array structure, and change the first varactor in the M OTP memory cells to the first resistor (step S1210 ).

Next, enter the confirmation cycle. That is, read M OTP memory cells in the array structure, and confirm that N OTP memory cells are failure memory cells (step S1212 ). And, it is judged whether N is 0 (step S1214).

When N is not 0, enter the second programming cycle. That is, program N failed memory cells in the array structure, and change the second varactors in the N failed memory cells into second resistors (step S1216). After that, the operation flow is ended.

And, when N is 0, the operation flow is ended directly.

It can be seen from the above operation method that in the array structure of the present invention, each OTP memory cell includes two varactors. And according to the operation method of the array structure of the present invention, when the gate oxide layer of the first varactor Va cannot be broken smoothly in the first programming cycle, the gate oxide layer of the second varactor Va' can be broken in the second programming cycle. The extreme oxide layer makes the OTP memory cell a programming memory cell. Moreover, the effect of in-cell 100% redundancy is achieved.

Furthermore, as shown in FIG. 13 , it is a top view of an array structure according to another embodiment of the present invention. In Figure 13, each dotted box represents an OTP memory cell. The difference from FIG. 8A is that the second polysilicon gates of OTP memory cells C00, C10, C01 and C11 are connected together and connected to the first programming line PL1; and the third polysilicon gates of OTP memory cells C10, C20, C11 and C21 The polysilicon gates are connected together and to the second programming line PL2.

Similarly, after the structure in FIG. 13 is completed, a channel elimination step, such as a source/drain expansion step, a well formation step, or an ion implantation step, is required for the second gate structure and the third gate structure. The channel in is eliminated and a variable vessel is formed. After that, the array structure of the present invention is formed.

Furthermore, in the array structure shown in FIG. 13 , the bias voltages on the relevant signal lines during the first programming cycle, confirmation cycle and second programming cycle are exactly the same as those of the array structures shown in FIGS. 8A to 8B . Meanwhile, the flow chart of the operation method of the array structure shown in FIG. 12 is also applicable to the array structure shown in FIG. 13 . Therefore, the detailed operation principle will not be repeated.

In summary, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims (2)

1. A method of operating an array structure, the array structure comprising: Memory cells programmed for the first time, including: a first transistor having a drain, a source connected to a first bit line, and a gate connected to a first word line; a first varactor with a first end connected to the drain of the first transistor, and a second end connected to a first programming line; and a second varactor having a first end connected to the drain of the first transistor, and a second end connected to a second programming line; and Memory cells programmed for the second time, including: a second transistor having a drain, a source connected to the first bit line, and a gate connected to a second word line; a third varactor having a first end connected to the drain of the second transistor, and a second end connected to a third programming line; and a fourth varactor, with a first terminal connected to the drain of the second transistor, a second terminal connected to a fourth programming line, The operation method of the array structure comprises the following steps: Entering the first programming cycle, changing the first varactor in the first programming memory cell to the first resistor; Entering the confirmation cycle, reading the first read current generated by the memory cell programmed for the first time, and judging whether the memory cell programmed for the first time is a failed memory cell; and When it is confirmed that the memory cell programmed for the first time is the failed memory cell, a second programming cycle is entered, and the second varactor in the memory cell programmed for the first time is changed to a second resistor. 2. The operation method of the array structure as claimed in claim 1, wherein when the first read current is lower than the reference current, it is confirmed that the first programmed memory cell is the failed memory cell.