CN105185783B - Capacitive diode assembly and its manufacturing method - Google Patents
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- CN105185783B CN105185783B CN201510516284.4A CN201510516284A CN105185783B CN 105185783 B CN105185783 B CN 105185783B CN 201510516284 A CN201510516284 A CN 201510516284A CN 105185783 B CN105185783 B CN 105185783B
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Abstract
Disclose capacitive diode assembly and its manufacturing method.The capacitive diode assembly includes：The semiconductor substrate of first conduction type；The epitaxial layer of the second conduction type in semiconductor substrate, the second conduction type are different from the first conduction type；The isolated area of first conduction type, it is extended in semiconductor substrate from the surface of epitaxial layer across epitaxial layer, to limit the first active area of the first diode and the second active area of the second diode in the epitaxial layer, and the first active area and the second active area are separated from each other；First doped region of the first conduction type is extended to from epi-layer surface in epitaxial layer in the first active area；Second doped region of the second conduction type is extended to from epi-layer surface in epitaxial layer in the second active area；And conductive channel, it is extended into semiconductor substrate from epi-layer surface in the first active area so that epitaxial layer and semiconductor substrate are electrically connected to each other.The capacitive diode assembly can be used as non-polar capacity cell, can improve the transient response speed of Transient Voltage Suppressor.
Description
Technical field
The present invention relates to microelectronics technologies, more particularly, to capacitive diode assembly and its manufacturing method.
Background technology
Transient Voltage Suppressor TVS (Transient Voltage Suppressor) develops on the basis of voltage-stabiliser tube
High-effect circuit brake.The shape of TVS diode is no different with common voltage-stabiliser tube, however, due to special structure and technique
Design, the transient response speed and surge absoption ability of TVS diode are far above common voltage-stabiliser tube.For example, the sound of TVS diode
It is only 10 between seasonable-12Second, and up to thousands of watts of surge power can be absorbed.Under the conditions of applied in reverse, when bearing one
When the big pulse of high-energy, the working impedance of TVS diode can quickly be down to extremely low conduction value, to allow high current logical
It crosses, meanwhile, by voltage clamp in predeterminated level.Therefore, TVS diode can be effectively protected the first device of the precision in electronic circuit
Damage of the part from various surge pulses.
The manufacturing process of traditional TVS diode is fairly simple, usually by special shaped doped on P+ substrates/N+ substrates
Directly form PN junction.The response speed of TVS diode and its capacitance are closely related.Traditional TVS diode is mainly used in disappearing
Take the data terminal in electronic product, such as keyboard, side switch and power cord.Since such terminal speed is slower, to bis- poles TVS
The transient response speed of pipe is of less demanding, and capacitance is generally in 20pF or more.However, video data line has high data transmission
Rate (its data transmission rate is up to 480M, and some video data transmission rates reach 1G or more).Therefore, for the guarantor of video line
Shield, the transient response speed of traditional TVS diode cannot meet requirement.In transmission of video, the electricity of TVS diode
Hold and requires to be less than 1.0pF.
In existing TVS device, additional capacitor of the common rectifier diode as small capacitances value, with Zener diode
Series connection.The capacitance of the TVS device is by the capacitance depending on additional capacitor.Due to the unilateal conduction characteristic of rectifier diode,
The TVS device is also unidirectional device, and one-way low-capacitance ESD protection function may be implemented.However, not due to ghost effect and heat dissipation
Good, which is extremely difficult to higher transient power.
Therefore, for the application of TVS device, it is expected that developing novel capacitive device, the same of transient response speed is being improved
When, the requirement of unidirectional and bidirectional applications is taken into account, process complexity and cost are reduced, and high protection voltage is provided.
Invention content
The technical problem to be solved in the present invention is to provide a kind of capacitive diodes can be used for one-way or bi-directional TVS device
Component, which has ultra-low capacitance, to improve the transient response speed of TVS device.
According to an aspect of the present invention, a kind of capacitive diode assembly is provided, including：The semiconductor of first conduction type serves as a contrast
Bottom；The epitaxial layer of the second conduction type in semiconductor substrate, the second conduction type are different from the first conduction type；First
The isolated area of conduction type is extended to from the surface of epitaxial layer across epitaxial layer in semiconductor substrate, to limit in the epitaxial layer
Second active area of the first active area and the second diode of fixed first diode, and by the first active area and the second active area
It is separated from each other；First doped region of the first conduction type is extended to from epi-layer surface in epitaxial layer in the first active area；Second
Second doped region of conduction type is extended to from epi-layer surface in epitaxial layer in the second active area；And conductive channel,
One active area is extended into from epi-layer surface in semiconductor substrate so that epitaxial layer and semiconductor substrate are electrically connected to each other.
Preferably, the capacitive diode assembly further includes：Insulating layer on epitaxial layer；And interconnecting line, it wears
Cross insulating layer reach the first doped region and with the second doped region, and be electrically connected with the two.
Preferably, the PN junction of the first diode, semiconductor substrate and epitaxial layer are formed between the first doped region and epitaxial layer
Between form the PN junction of the second diode.
Preferably, the first diode and the second diode are connected in inverse parallel using semiconductor substrate and interconnecting line.
Preferably, the doping concentration of the first doped region is more than 1.0 × 1018cm-3, the doping concentration of the second doped region is more than
8.0×1019cm-3。
Preferably, the thickness of epitaxial layer is more than 2 μm.
Preferably, the first conduction type is one of N-type and p-type, and the second conduction type is another in N-type and p-type.
According to another aspect of the present invention, a kind of method of manufacture capacitive diode assembly is provided, including：In the first conduction
In the semiconductor substrate of type, the epitaxial layer of the second conduction type is formed, the second conduction type is different from the first conduction type；It adopts
With the first doping process, the isolated area of the first conduction type is formed, isolated area is extended to from the surface of epitaxial layer across epitaxial layer
In semiconductor substrate, to limit in the epitaxial layer the first diode the first active area and the second diode it is second active
Area, and the first active area and the second active area are separated from each other；Using the second doping process, the of the first conduction type is formed
One doped region, the first doped region are extended to from epi-layer surface in epitaxial layer in the first active area；Using third doping process, shape
At the second doped region of the second conduction type, the second doped region is extended to from epi-layer surface in epitaxial layer in the first active area；
And conductive channel is formed, the conductive channel extends into semiconductor substrate from epi-layer surface in the first active area, makes
It obtains epitaxial layer and semiconductor substrate is electrically connected to each other.
Preferably, the step of formation conductive channel includes：Insulating layer is formed on epitaxial layer；And it is formed across insulating layer
Conductive channel.
Preferably, the method further include the interconnecting line to be formed across insulating layer, interconnecting line and the first doped region and
It is electrically connected with the second doped region.
Preferably, the first conduction type is one of N-type and p-type, and the second conduction type is another in N-type and p-type.
Capacitive diode assembly according to an embodiment of the invention includes the first diode and the two or two pole of reverse parallel connection
Pipe has almost the same forward characteristic, so as to as non-polar capacitance in two directions.The ultra-low capacitance holds
Property diode assembly can be realized on the chip area of very little, greatly improve semiconductor devices integration packaging be applicable in
Property, so that device architecture is suitable for a variety of different packing forms.Since semiconductor substrate is drawn directly as another electrode,
It can reduce by 1 bonding gold wire when encapsulation, cost of manufacture can be greatly reduced, be conducive to industrialization.The present invention provides
It is such a can batch making ultra-low capacitance biphase rectification construction module.In addition, the production method and standard of the product
Bipolar process is mutually compatible with.
The capacitive diode assembly is connected in series with Zener diode, forms one-way or bi-directional Transient Voltage Suppressor.Institute
State only can increase 0.7V's when ultra-low capacitance capacitive diode assembly is connected with arbitrary TVS device on the voltage of former TVS device
Conduction voltage drop hardly changes the electrology characteristic of former TVS device.For example, by the ultra-low capacitance capacitive diode assembly and one
A forward voltage 0.8V, breakdown reverse voltage 20V, capacitance be 20pF unidirectional TVS device Series Package in a shell, will
A forward voltage 1.5V, breakdown reverse voltage 20.7V are obtained, and capacitance only has the ultra-low capacitance TVS device less than 1pF.
The capacitive diode assembly just always bears transient power by diode.When surge occurs, positive two poles
Pipe will be to be less than 10-12The speed moment of second opens, and so that surge current is passed through while generating a very small pressure drop, protects
It demonstrate,proves itself not to be damaged, continues the effect for keeping reducing capacitance.
Since capacitive diode assembly has ultralow capacitance, it is thus possible to improve the response speed of TVS device, pole
The big application range for having widened all kinds of devices.For example, some traditional TVS protection devices and two pole of ultra-low capacitance capacitive
After tube assembly combination, capacitance is greatly reduced, and can also be applied in the data transmission network of high frequency.
In Transient Voltage Suppressor, if capacitive diode assembly and Zener diode are formed in different semiconductor cores
On piece, the then manufacturing process that both can be separately optimized more flexiblely so that capacitive diode assembly provide low capacitance with
The transient response speed of TVS device is improved, Zener diode provides high-breakdown-voltage to obtain required protection voltage level.
Both it is respectively formed after capacitive diode assembly and Zener diode, connected using bonding line, and it is encapsulated in a shell
It is interior.
Description of the drawings
By referring to the drawings to the description of the embodiment of the present invention, the above and other purposes of the present invention, feature and
Advantage will be apparent from, in the accompanying drawings：
Fig. 1 shows the structural schematic diagram of capacitive diode assembly according to a first embodiment of the present invention；And
Fig. 2 a to 2g show manufacturing method each stage of capacitive diode assembly according to a second embodiment of the present invention
Sectional view.
Specific implementation mode
Hereinafter reference will be made to the drawings is more fully described the present invention.In various figures, identical element is using similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown certain
Well known part.
It should be appreciated that when describing some structure, it is known as positioned at another layer, another region when by one layer, a region
When " above " or " top ", can refer to above another layer, another region, or its with another layer, another
Also include other layers or region between region.Also, if the structure overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".If in order to describe located immediately at another layer, another region above scenario,
The form of presentation of " A is directly on B " or " A is on B and abuts therewith " will be used herein.
In addition, refer to the first conduction type and the second conduction type when describing the conduction type of semi-conducting material, wherein
First conduction type is one of p-type and N-type, and the second conduction type is another in p-type and N-type.
The present invention can be presented in a variety of manners, some of them example explained below.
Fig. 1 shows the structural schematic diagram of capacitive diode assembly according to a first embodiment of the present invention.The capacitive diode
Component includes the diode of two reverse parallel connections formed on a semiconductor substrate.
As shown in Figure 1, forming N-type epitaxial layer 103 in P++ types semiconductor substrate 101.The thickness of epitaxial layer 103 is for example
More than 2 μm.P+ type isolated area 104 is extended to across epitaxial layer 103 in semiconductor substrate 101 from the surface of epitaxial layer 103, to
The first active area of the first diode and the second active area of the second diode are limited in epitaxial layer 103.Isolated area 104 is by
One active area and the second active area are separated from each other.Correspondingly, isolated area 104 includes surrounding the first active area and the second active area
Peripheral portion, and middle section that the first active area and the second active area are separated from each other.
P++ types doped region 110 is located at the first active area, is extended in epitaxial layer 103 from 103 surface of epitaxial layer.For example, mixing
The doping concentration in miscellaneous area 110 is more than 1.0 × 1018cm-3.N++ doped regions 111 are located at the second active area, from 103 table of epitaxial layer
Face extends in epitaxial layer 103.For example, the doping concentration of doped region 111 is more than 8.0 × 1019cm-3。
Insulating layer 120 is located at 103 top of epitaxial layer.Conductive channel 107 passes through insulating layer 120 and epitaxial layer 103, into half
In conductor substrate 101, to which epitaxial layer 103 and semiconductor substrate 101 are electrically connected to each other.Interconnecting line 108 passes through insulating layer
120 reach the top surface of doped region 110 and 111, to which the two be electrically connected to each other.Interconnecting line 108 is additionally operable to and outside
Electrical connection between circuit, such as signal end I/O.
In the capacitive diode assembly of the embodiment, using conductive channel 107 by epitaxial layer 103 and semiconductor substrate
101 short circuits each other so that the current path between doped region 110, epitaxial layer 103, conductive channel 107 and semiconductor substrate 101
(as indicated by a dashed arrow in the figure) there is only a PN junctions on.Thus, the one or two is formed between doped region 110 and epitaxial layer 103
The PN junction of pole pipe forms the PN junction of the second diode between semiconductor substrate 101 and epitaxial layer 103, to realize first respectively
The basic structure of diode and the second diode.
Metal layer on back 160 is formed at the back side of semiconductor substrate 101, as ground terminal GND.First diode and second
Diode is connected in inverse parallel using semiconductor substrate 101 and interconnecting line 108.
The capacitive diode assembly includes the first diode and the second diode of reverse parallel connection, utilizes diode forward
The characteristic of low pressure drop and low on-resistance realizes the electrical characteristics of ultra-low capacitance biphase rectification.The capacitive diode assembly can conduct
Non-polar capacitance is used for one-way or bi-directional TVS device.
Fig. 2 a to 2g show manufacturing method each stage of capacitive diode assembly according to a second embodiment of the present invention
Sectional view.In the following description, it is specially one of p-type and N-type by the conduction type for describing semi-conducting material.It is appreciated that
If inverting the conduction type of each semi-conducting material, it is also possible to obtain the semiconductor devices of identical function.
As shown in Figure 2 a, N-type epitaxial layer 103 and insulating layer 120 are sequentially formed in P++ types semiconductor substrate 101.
Semiconductor substrate 101 is, for example, monocrystalline substrate, and N-type epitaxy layer 103 is, for example, silicon epitaxy layer, and is respectively adopted
Suitable dopant is doping to desired conduction type.It, can be in semiconductor in order to form p-type or n type semiconductor layer or region
The dopant of respective type is mixed in layer and region.For example, P-type dopant includes boron, N type dopant includes phosphorus or arsenic.At this
In embodiment, semiconductor substrate 101 is that doping concentration is 1019cm-3The heavy doping P++ substrates of magnitude, resistivity are about
0.004~0.006 Ω cm.
Epitaxial layer 103 may be used known depositing operation and be formed.For example, depositing operation can be selected from electron beam evaporation
(EBM), one kind in chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering.In this embodiment, epitaxial layer 103 is
N- epitaxial layers are lightly doped, resistivity is not less than 5.5 Ω cm, and thickness is not less than 5.5 μm.
Sputtering may be used in insulating layer 120 or thermal oxide is formed.For example, insulating layer 120 is the silica that thermal oxide is formed
Layer, in subsequent doping step, insulating layer 120 is as protective layer, and by the interlayer insulating film as resulting devices.
Then, the isolated area 104 of P+ type is made in the epitaxial layer, as shown in Figure 2 b.The isolated area 104 limits two two poles
The active area of pipe, and the active area of two diodes is isolated from each other.In this embodiment, isolated area 104 is, for example, B30Breast
The doping concentration that glue source technique makes is 4.0 × 1019cm-3P++ isolated areas.Isolated area 104 is formed in epitaxial layer 103 simultaneously
Extend to semiconductor substrate 101.The isolated area will be connected with semiconductor substrate 101 draws from the back side.Isolated area concentration is by shadow
The conducting resistance of rectifying device is rung, those skilled in the art can control isolated area concentration, but too low isolation according to device requirement
Area's concentration restricts the current capacity of rectifying device by serious, therefore should control not less than 1019cm-3The order of magnitude.
Then, the doped region 110 of P++ types is made in the active area of the first diode, as shown in Figure 2 c.In the embodiment
In, doped region 110 is a concentration of 1.0 × 10 that latex source diffuses to form18~9.9 × 1019cm-3Heavily doped region.This field
Technical staff can form the doped region 110 according to actual processing condition using ion implanting or other method of diffusion.It is described to mix
110 concentration of miscellaneous area should be not less than the doping concentration of the epitaxial layer 103.
Then, N++ doped regions 111 are made in the active area of the second diode, and in the active area system of the first diode
Make N++ doped regions 112, as shown in Figure 2 d.The doped region 112 is between the first active area and the peripheral portion of isolated area
Interface.Preferably, doped region 112 is also about doped region 110, stops ring to form voltage.In this embodiment, doped region
112 concentration made for phosphoric diffusion technology are about 8.0 × 1019cm-3~2.0 × 1020cm-3N++ doped regions.
It will be appreciated by those skilled in the art that the position of each doped region, size and doping concentration can be rationally designed to control
The capacitance of rectifying tube processed obtains satisfactory ultra-low capacitance capacitive diode assembly.
The access opening on insulating layer 120 and lead electrode hole are then turned on, as shown in Figure 2 e.It should be noted that described draw
Line electrode hole must retain a contact window that can expose doped region 112 and isolated area 104 simultaneously.
It is formed after access opening on insulating layer 120, further etches epitaxial layer 103 and semiconductor substrate via the hole
101 part stops at the predetermined depth for entering semiconductor substrate 101.
Then, conductive channel and interconnecting line are made, as shown in figure 2f.Conductive channel 107 passes through insulating layer 120 and extension
Layer 103, into semiconductor substrate 101.In this embodiment, using metallic aluminium as conductive channel and interconnecting line.It is conductive
Epitaxial layer 103 and 101 short circuit of semiconductor substrate are electrically connected by channel 107.Interconnecting line 108 will be produced on mixing for the first active area
Miscellaneous area 110 and the doped region 111 for being produced on the second active area are electrically connected, and can be brought out as signal end I/O.
Then, by chip thinning and back metal, as shown in Figure 2 g.The back side is formed at the back side of semiconductor substrate 101
Metal layer 160, as ground terminal GND.
In this embodiment, using gold as metal layer on back 106.Those skilled in the art can select according to packing forms
Different metal or metal alloy is as metal layer on back, such as gold, silver, copper, titanium silver, titanium nickel gold.
It should be noted that P+ or P++ indicates that p-type heavy doping, N+ or N++ indicate N-type heavy doping, N- in the above-described example
Indicate that N-type is lightly doped.Here, heavy doping and to be lightly doped be opposite concept, indicates that the doping concentration of heavy doping is more than and is lightly doped
Doping concentration, and not restriction to specific doping concentration range.
Device according to the present invention is can be seen that, ultra-low capacitance capacitive diode group can be prepared with simple step
Part.It being contacted with P++ semiconductor substrates 101 by extending to P+ isolated areas 104, regarding P++ semiconductor substrates 101 as ground terminal
GND, without drawing ground terminal from front.It not only contributes to reduce chip size in this way, moreover it is possible to device architecture be made to be suitable for
A variety of different packing forms.In addition, P++ semiconductor substrates 101 are drawn directly as ground connection GND electrodes, when packaged may be used
To reduce by 1 bonding gold wire, cost of manufacture can be greatly reduced, be conducive to industrialization.The ultralow electricity made according to the present invention
Appearance capacitive diode assembly, can free definition signal end I/O and ground terminal GND according to different use environments.
If capacitive diode assembly is formed a semiconductor core on piece, as individual device, then this need to be only used
The Zener diode tandem compound for inventing the ultra-low capacitance capacitive diode assembly provided and a traditional handicraft making encapsulates, i.e.,
A ultra-low capacitance Zener diode can be obtained, which, which will be provided with the Zener diode that the traditional handicraft makes, is had
Almost all electrology characteristic, while obtaining ultralow capacitance.
In the above description, well known structural element and step are not described in detail.But this field
It will be appreciated by the skilled person that can be by various technological means, to realize corresponding structural element and step.In addition, for shape
At identical structural element, those skilled in the art can be devised by and process as described above not fully identical side
Method.In addition, although respectively describing each embodiment above, but it is not intended that the measure in each embodiment cannot have
It is used in combination sharply.
The embodiment of the present invention is described above.But the purpose that these embodiments are merely to illustrate that, and
It is not intended to limit the scope of the invention.The scope of the present invention is limited by appended claims and its equivalent.This hair is not departed from
Bright range, those skilled in the art can make a variety of alternatives and modifications, these alternatives and modifications should all be fallen the present invention's
Within the scope of.
Claims (11)
1. a kind of capacitive diode assembly, including：
The semiconductor substrate of first conduction type；
The epitaxial layer of the second conduction type in semiconductor substrate, the second conduction type are different from the first conduction type；
The isolated area of first conduction type is extended to from the surface of epitaxial layer across epitaxial layer in semiconductor substrate, to outside
Prolong the second active area of the first active area and the second diode that the first diode is limited in layer, and by the first active area and
Two active areas are separated from each other；
First doped region of the first conduction type is extended to from epi-layer surface in epitaxial layer in the first active area；
Second doped region of the second conduction type is extended to from epi-layer surface in epitaxial layer in the second active area；And
Conductive channel is extended into from epi-layer surface in semiconductor substrate so that epitaxial layer and semiconductor in the first active area
Substrate is electrically connected to each other.
2. capacitive diode assembly according to claim 1, further includes：
Insulating layer on epitaxial layer；And
Interconnecting line, pass through insulating layer reach the first doped region and with the second doped region, and be electrically connected with the two.
3. capacitive diode assembly according to claim 1, wherein form the one or two between the first doped region and epitaxial layer
The PN junction of pole pipe forms the PN junction of the second diode between semiconductor substrate and epitaxial layer.
4. capacitive diode assembly according to claim 2, wherein the first diode and the second diode use semiconductor
Substrate and interconnecting line are connected in inverse parallel.
5. capacitive diode assembly according to claim 1, wherein the doping concentration of the first doped region be more than 1.0 ×
1018cm-3, the doping concentration of the second doped region is more than 8.0 × 1019cm-3。
6. capacitive diode assembly according to claim 1, wherein the thickness of epitaxial layer is more than 2 μm.
7. capacitive diode assembly according to any one of claim 1 to 6, wherein the first conduction type is N-type and P
One of type, the second conduction type are another in N-type and p-type.
8. a kind of method of manufacture capacitive diode assembly, including：
In the semiconductor substrate of the first conduction type, the epitaxial layer of the second conduction type, the second conduction type and first are formed
Conduction type is different；
Using the first doping process, the isolated area of the first conduction type is formed, isolated area passes through epitaxial layer from the surface of epitaxial layer
Extend in semiconductor substrate, to limit in the epitaxial layer the first diode the first active area and the second diode second
Active area, and the first active area and the second active area are separated from each other；
Using the second doping process, the first doped region of the first conduction type is formed, the first doped region is in the first active area from outer
Prolong layer surface to extend in epitaxial layer；
Using third doping process, the second doped region of the second conduction type is formed, the second doped region is in the first active area from outer
Prolong layer surface to extend in epitaxial layer；And
Conductive channel is formed, the conductive channel extends into semiconductor substrate from epi-layer surface in the first active area, makes
It obtains epitaxial layer and semiconductor substrate is electrically connected to each other.
9. according to the method described in claim 8, the step of wherein forming conductive channel includes：
Insulating layer is formed on epitaxial layer；And
Form the conductive channel across insulating layer.
10. according to the method described in claim 9, further including the interconnecting line to be formed across insulating layer, interconnecting line and first
Doped region and with the second doped region be electrically connected.
11. according to the method described in any one of claim 8-10, wherein the first conduction type is one of N-type and p-type, the
Two conduction types are another in N-type and p-type.
Priority Applications (1)
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101714759A (en) * | 2009-11-11 | 2010-05-26 | 上海长园维安微电子有限公司 | Low-capacitance bidirectional ESD protective device and preparation method thereof |
| CN101771042A (en) * | 2009-12-31 | 2010-07-07 | 上海长园维安微电子有限公司 | Programmable TVS apparatus with low capacitance and low voltage |
| CN102306649A (en) * | 2011-08-24 | 2012-01-04 | 浙江大学 | Bidirectional dual-channel transient voltage suppressor (TVS) |
| CN203445119U (en) * | 2013-09-16 | 2014-02-19 | 杭州士兰集成电路有限公司 | Integrated bi-directional ultra-low capacitance TVS device |
| CN205016525U (en) * | 2015-08-20 | 2016-02-03 | 北京燕东微电子有限公司 | Capacitive diode cluster spare |
Family Cites Families (2)
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| US7880223B2 (en) * | 2005-02-11 | 2011-02-01 | Alpha & Omega Semiconductor, Ltd. | Latch-up free vertical TVS diode array structure using trench isolation |
| US8338854B2 (en) * | 2009-03-31 | 2012-12-25 | Alpha And Omega Semiconductor Incorporated | TVS with low capacitance and forward voltage drop with depleted SCR as steering diode |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101714759A (en) * | 2009-11-11 | 2010-05-26 | 上海长园维安微电子有限公司 | Low-capacitance bidirectional ESD protective device and preparation method thereof |
| CN101771042A (en) * | 2009-12-31 | 2010-07-07 | 上海长园维安微电子有限公司 | Programmable TVS apparatus with low capacitance and low voltage |
| CN102306649A (en) * | 2011-08-24 | 2012-01-04 | 浙江大学 | Bidirectional dual-channel transient voltage suppressor (TVS) |
| CN203445119U (en) * | 2013-09-16 | 2014-02-19 | 杭州士兰集成电路有限公司 | Integrated bi-directional ultra-low capacitance TVS device |
| CN205016525U (en) * | 2015-08-20 | 2016-02-03 | 北京燕东微电子有限公司 | Capacitive diode cluster spare |
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