CN104732935B - Gate driving unit and display device with gate drive unit - Google Patents
Gate driving unit and display device with gate drive unit Download PDFInfo
- Publication number
- CN104732935B CN104732935B CN201510070813.2A CN201510070813A CN104732935B CN 104732935 B CN104732935 B CN 104732935B CN 201510070813 A CN201510070813 A CN 201510070813A CN 104732935 B CN104732935 B CN 104732935B
- Authority
- CN
- China
- Prior art keywords
- switch element
- path
- path terminal
- grid
- control end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000003071 parasitic effect Effects 0.000 claims description 9
- 230000006641 stabilisation Effects 0.000 abstract description 11
- 238000011105 stabilization Methods 0.000 abstract description 11
- 230000000087 stabilizing effect Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 22
- 238000004088 simulation Methods 0.000 description 12
- 239000010409 thin film Substances 0.000 description 11
- 230000008859 change Effects 0.000 description 10
- 239000008186 active pharmaceutical agent Substances 0.000 description 7
- 238000013499 data model Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 239000004973 liquid crystal related substance Substances 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 230000007423 decrease Effects 0.000 description 5
- 230000036962 time dependent Effects 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000024241 parasitism Effects 0.000 description 3
- 235000018734 Sambucus australis Nutrition 0.000 description 2
- 244000180577 Sambucus australis Species 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- OGFXBIXJCWAUCH-UHFFFAOYSA-N meso-secoisolariciresinol Natural products C1=2C=C(O)C(OC)=CC=2CC(CO)C(CO)C1C1=CC=C(O)C(OC)=C1 OGFXBIXJCWAUCH-UHFFFAOYSA-N 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 210000001367 artery Anatomy 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 210000003462 vein Anatomy 0.000 description 1
Landscapes
- Electronic Switches (AREA)
Abstract
The invention provides a gate driving unit and a display device with the gate drive unit. The gate driving unit comprises a first switch element, a second switch element, a third switch element and a fourth switch element. The first switch element is used for receiving a first clock signal and a first pulse signal. The second switch element is used for receiving a second pulse signal and connected with the first switch element. The third switch element is used for receiving a third clock signal and the second pulse signal and connected with the first switch element and the second switch element. The fourth switch element is used for receiving a fourth clock signal and reference low voltage and connected with the second switch element. The first switch element, the second switch element and the third switch element are dual-gate transistors. According to the gate driving unit and the display device, the dual-gate-structure transistors are used as an input tube and an output tube, the On state current is increased, the leakage current is reduced, and therefore no complex stabilization circuit is needed; meanwhile, as a stabilizing tube is the dual-gate-structure transistor, noise signals at the output end are well controlled, and reliability is high.
Description
Technical field
The present invention relates to a kind of drive circuit, more particularly to a kind of drive element of the grid and the display device using it.
Background technology
It is many excellent that liquid crystal indicator (Liquid Crystal Display, LCD) possesses frivolous, energy-conservation, radiationless etc.
Point, therefore gradually replaced traditional cathode-ray tube (CRT) display.At present liquid crystal display is widely used in height
The electronics such as clear DTV, desktop computer, personal digital assistant (PDA), notebook computer, mobile phone, digital camera
In equipment.
As a example by with thin film transistor (TFT) (Thin Film Transistor, TFT) liquid crystal indicator, it includes：Liquid crystal
Show panel and drive circuit, wherein, display panels include the infrabasal plate being made up of thin film transistor (TFT) array and by filter
The upper substrate that array is constituted, thin film transistor (TFT) array includes a plurality of gate line and a plurality of data lines, and two adjacent gate lines
A pixel cell is intersected to form with two adjacent data lines, each pixel cell at least includes a thin film transistor (TFT).And
Drive circuit includes：Gate driver circuit (gate drive circuit) and source electrode drive circuit (source drive
circuit).With cost degradation pursuit and the raising of manufacturing process of the producer to liquid crystal indicator, it is arranged at originally
Drive circuit integrated chip beyond display panels is arranged on the glass substrate of display panels and becomes possibility,
For example, grid-driving integrated circuit is arranged on array base palte (Gate IC in Array, GIA) so as to simplify liquid crystal display
The manufacture process of device, and reduce production cost.
But performance need of the development and people with lcd technology to display panels, the narrow side of large scale
Frame panel array substrate is challenged.Large size panel causes the load of array base palte bigger, loads bigger, output stage film
Transistor is bigger, and then cannot accomplish narrow frame, and excessive thin film transistor (TFT) causes the leakage current and noise of output stage to increase
Greatly, and the substantial amounts of clock feedthrough effect stablized output stage using transistor, and then cause output stage Leakage Current and noise
Should be very big, the reliability of integrated circuit can decline.
Therefore, it is necessary to provide improved technical scheme to overcome above technical problem present in prior art.
The content of the invention
The main technical problem to be solved in the present invention is to provide a kind of drive element of the grid, its simple structure, and reliability
It is high.
The present invention also provides a kind of display device using above-mentioned drive element of the grid.
To solve above-mentioned technical problem, the invention provides a kind of drive element of the grid, it include first switch element, the
Two switch elements, the 3rd switch element and the 4th switch element.The first switch element, including the first control end, first lead to
Terminal and alternate path end, first control end receives the first pulse signal, and first path terminal receives the first sequential letter
Number.The second switch element, including the second control end, third path end and fourth passage end, second control end and institute
The alternate path end for stating first switch element is connected, and the third path end receives the second clock signal, the four-way
Terminal is connected by the first electric capacity with the alternate path end of the first switch element, and the fourth passage end is used to export
This grade of gate drive signal.3rd switch element, including the 3rd control end, fifth passage end and the 6th path terminal, it is described
3rd control end receives the 3rd clock signal, the alternate path end phase of the fifth passage end and the first switch element
Even, the 6th path terminal receives the second pulse signal.4th switch element, including the 4th control end, the 7th path terminal
And the 8th path terminal, the 4th control end receives the 4th clock signal, the 7th path terminal and the second switch element
The fourth passage end be connected, the 8th path terminal receives low reference voltage.Wherein, the first switch element is to described
3rd switch element is double-gated transistor.
The present invention also provides a kind of display device, and the display device includes multistage drive element of the grid, and every grade of grid drives
Moving cell includes first switch element, second switch element, the 3rd switch element and the 4th switch element.The first switch unit
Part, including the first control end, the first path terminal and alternate path end, first control end receives the first pulse signal, described
First path terminal receives the first clock signal.The second switch element, including the second control end, third path end and four-way
Terminal, second control end is connected with the alternate path end of the first switch element, and the third path end receives
Second clock signal, the fourth passage end by the first electric capacity with described in the first switch element. alternate path end phase
Even, the fourth passage end is used to export this grade of gate drive signal.3rd switch element, including the 3rd control end, the
Five path terminals and the 6th path terminal, the 3rd control end receives the 3rd clock signal, the fifth passage end and described first
The alternate path end of switch element is connected, and the 6th path terminal receives the second pulse signal.4th switch element,
Including the 4th control end, the 7th path terminal and the 8th path terminal, the 4th control end receives the 4th clock signal, and the described 7th
Path terminal is connected with the fourth passage end of the second switch element, and the 8th path terminal receives low reference voltage.Its
In, the first switch element, the second switch element and the 3rd switch element are double-gated transistor.
Further, the 4th switch element is double-gated transistor.
Further, first electric capacity is between the third path end and fourth passage end of the second switch element
Parasitic capacitance.
Further, it is provided between the third path end and the fourth passage end of the second switch element solely
Vertical storage capacitance, first electric capacity is between the third path end of the second switch element and the fourth passage end
The parasitic capacitance and the separate storage electric capacity sum.
Further, first control end of the first switch element, described the second of the second switch element
3rd control end of control end and the third element is bigrid, the 4th control of the 4th switch element
Hold as grid, first path terminal of the first switch element, the third path end of the second switch element, institute
7th path terminal at the fifth passage end and the 4th switch element of stating the 3rd switch element is drain electrode, described
The alternate path end of first switch element, the fourth passage end of the second switch element, the 3rd switch unit
6th path terminal of part and the 8th path terminal of the 4th switch element are source electrode.
Further, the 4th switch element is single gate transistor, and the drive element of the grid is also stable including second
Module, second stable module includes first input end, the second input and the first output end, and the first input end is received
Second clock signal, second input receives the low reference voltage, and first output end is opened with described second
The second control end for closing element is connected.
Further, second stable module include the 5th switch element, the 6th switch element, the 7th switch element and
8th switch element, the 5th switch element includes the 5th control end, the 9th path terminal and the tenth path terminal, the 5th control
End processed and the 9th path terminal receive second clock signal；6th switch element include the 6th control end, the tenth
One path terminal and the 12nd path terminal, the 6th control end is connected with the tenth path terminal of the 5th switch element,
11st path terminal receives second clock signal；7th switch element includes the 7th control end, the tenth threeway
Terminal and the 14th path terminal, the 7th control end is connected with the 12nd path terminal of the 6th switch element, institute
State the tenth threeway terminal to be connected with second control end of the second switch element, the 14th path terminal receives described
Low reference voltage；8th switch element include the 8th control end, the 15th path terminal and the 16th path terminal, the described 8th
Control end is connected with the alternate path end of the first switch element, and the 15th path terminal and the described 6th switch are first
12nd path terminal of part is connected, and the 16th path terminal receives the low reference voltage.
Further, the 5th switch element, the 6th switch element, the 7th switch element and the described 8th
Switch element is single gate transistor.
Further, the 5th control end of the 5th switch element, the described 6th of the 6th switch element the
8th control end of control end, the 7th control end of the 7th switch element and the 8th switch element is
Single grid, the 9th path terminal, the 11st path terminal, the institute of the 6th switch element of the 5th switch element
15th path terminal of the tenth threeway terminal and the 8th switch element of stating the 7th switch element is drain electrode,
Tenth path terminal of the 5th switch element, the 12nd path terminal of the 6th switch element, the described 7th
14th path terminal of switch element and the 16th path terminal of the 8th switch element are source electrode.
The drive element of the grid and the display device using it of the present invention, using the transistor of double-gate structure as input pipe
(first switch element) and efferent duct (second switch element), increases ON state current, leakage current is reduced, so as to make
With complicated stabilizing circuit, simple structure；Simultaneous Stabilization pipe (the 3rd switch element) adopts the transistor of double-gate structure, and then makes
The noise signal of output end is by reasonable control, and reliability is high.
Description of the drawings
Fig. 1 is the electrical block diagram of the drive element of the grid of first embodiment of the invention.
Fig. 2 is the time diagram of the drive element of the grid of first embodiment of the invention.
Fig. 3 is the electrical block diagram of the drive element of the grid of second embodiment of the invention.
Fig. 4 is the time diagram of the drive element of the grid of second embodiment of the invention.
Fig. 5 a are the cross section of the double-gate structure thin film transistor (TFT) in first embodiment of the invention for drive element of the grid
Schematic diagram.
Fig. 5 b are the electric current electricity of the double-gate structure thin film transistor (TFT) in first embodiment of the invention for drive element of the grid
Pressure transfer characteristic curve schematic diagram.
Fig. 6 a export contrast schematic diagram for the simulation result of the drive element of the grid of first embodiment of the invention.
Fig. 6 b export contrast schematic diagram for the simulation result of the drive element of the grid of second embodiment of the invention.
Fig. 7 a are the simulation result output noise contrast schematic diagram of the drive element of the grid of first embodiment of the invention.
Fig. 7 b are the simulation result output noise contrast schematic diagram of the drive element of the grid of second embodiment of the invention.
Fig. 8 a export fall time contrast schematic diagram for the simulation result of the drive element of the grid of first embodiment of the invention.
Fig. 8 b export fall time contrast schematic diagram for the simulation result of the drive element of the grid of second embodiment of the invention.
Specific embodiment
It is understandable to enable the above objects, features and advantages of the present invention to become apparent from, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Although the present invention describes different elements, signal, port, component or portion using first, second, third, etc. term
Point, but these elements, signal, port, component or part are not limited by these terms.These terms are intended merely to one
Individual element, signal, port, component or part make a distinction with another element, signal, port, component or part.In the present invention
In, element, port, component or part and another element, port, component or part " connected ", " connection ", it is possible to understand that
To be directly electrically connected with, or it can be appreciated that there is the indirect electric connection of intermediary element.Unless otherwise defined, otherwise originally
All terms (including technical term and scientific terminology) that invention is used have and ordinary skill people of the art
The meaning that member is generally understood that.
Fig. 1 is the electrical block diagram of the drive element of the grid of first embodiment of the invention.As shown in figure 1, grid drives
Moving cell includes first switch element M1, second switch element M2, the 3rd switch element M3 and the 4th switch element M4.
Specifically, first switch element M1 includes the first control end, the first path terminal and alternate path end, the first control end
The first pulse signal Gn-4 is received, the first path terminal receives the first clock signal VA.Second switch element M2 includes the second control
End, third path end and fourth passage end, the second control end is connected with the alternate path end of first switch element M1, third path
End receives the second clock signal VB, the alternate path end phase that fourth passage end passes through the first electric capacity C1 and first switch element M1
Even, fourth passage end is used to export this grade of gate drive signal Gn, with driving load resistance RL and load capacitance CL.3rd switch
Element M3 include the 3rd control end, fifth passage end and the 6th path terminal, the 3rd control end receive the 3rd clock signal VC, the 5th
Path terminal is connected with the alternate path end of first switch element M1, and the 6th path terminal receives the second pulse signal Gn+1.4th opens
Closing element M4 includes the 4th control end, the 7th path terminal and the 8th path terminal, and the 4th control end receives the 4th clock signal VD, the
Seven path terminals are connected with the fourth passage end of second switch element M2, and the 8th path terminal receives low reference voltage VGL.Wherein, exist
In first embodiment of the invention, the first switch element to the 4th switch element M1～M4 is double-gated transistor.
Wherein, the first electric capacity C1 is the parasitism electricity between the fourth passage end of second switch element M2 and the second control end
Hold.Certainly it will be appreciated by those skilled in the art that be, it is also possible in second control end and the 4th of second switch element M2
Separate storage electric capacity is set between path terminal, and now, the first electric capacity C1 is the fourth passage end and second of second switch element M2
Parasitic capacitance between control end and separate storage electric capacity sum.
In the first embodiment of the invention, first switch element is N-type double-gated transistor to the 4th switch element M1～M4.
First control end of first switch element M1, second control end of second switch element M2, the 3rd control of the 3rd switch element M3
4th control end of end processed and the 4th switch element M4 is bigrid.That is, the control end of first switch element M1,
The control end of the control end, the control end of the 3rd switch element M3 and the 4th switch element M4 of second switch element M2 includes top
Grid and bottom-gate, wherein, the top-gated pole of first switch element M1 and bottom-gate receive the first pulse signal Gn-4 simultaneously, and the 3rd
The top-gated pole of switch element M3 and bottom-gate receive the 3rd clock signal VC, the top-gated pole of the 4th switch element M4 and bottom gate simultaneously
Pole receives the 4th clock signal VD simultaneously.
In an embodiment of the present invention, first path terminal of first switch element M1, the threeway of second switch element M2
Terminal, the fifth passage end of the 3rd switch element M3, the 7th path terminal of the 4th switch element M4 are drain electrode.First switch unit
The alternate path end of part M1, the fourth passage end of second switch element M2, the 6th path terminal of the 3rd switch element M3, the 4th open
The 8th path terminal for closing element M4 is source electrode.
Certainly, it will be appreciated by persons skilled in the art that first switch element also may be used to the 4th switch element M1～M4
To be realized, such as p-type double-gated transistor using other switch elements.Below with first switch element to the 4th switch element
M1～M4 be N-type double-gated transistor as a example by come specifically introduce the present invention specific embodiment and its operation principle.
Fig. 2 is referred to, it is the time diagram of the drive element of the grid of first embodiment.
The course of work of every one-level drive element of the grid as shown in Figure 2 is specifically now introduced, it can be divided into electric charge clearing
Stage 1, pre-charging stage 2, pull-up stage 3, drop-down stage 4,5 five stages of stabilization sub stage：
Electric charge resets the stage 1：First pulse signal Gn-4 is high level, and first switch element M1 conductings, the first sequential is believed
Number VA is low level, and voltage node Q at is pulled down to low level by the first switch element M1 of conducting.
Pre-charging stage 2：First pulse signal Gn-4 is high level, and first switch element M1 is turned on, the first clock signal
VA is high level, and node Q is precharged by the first switch element M1 for turning on.
The pull-up stage 3：First pulse signal Gn-4 is ended by high step-down, first switch element M1, but due in preliminary filling
Electric stage node Q has been electrically charged, therefore, second switch element M2 conducting, the second clock signal VB be high level, raster data model
The gate drive signal Gn of unit output is driven high, and due to the boot strap of the first electric capacity C1, the voltage at node Q is entered one
Step is drawn high.
It should be noted that in the present invention, can directly using the fourth passage end and second of second switch element M2
Parasitic capacitance between control end as the first electric capacity C1, or in order to lift pull-up effect, can be with second switch element
Separate storage electric capacity is set between second control end of M2 and fourth passage end, wherein, the separate storage electric capacity and second switch
The parasitic capacitance in parallel of element M2 is simultaneously equal to the parasitism of second switch element M2 collectively as the first electric capacity C1, i.e. the first electric capacity C1
Electric capacity and independent storage capacitance sum.
The drop-down stage 4：The level of the 4th clock signal VD is uprised by low, the 4th switch element M4 conductings, raster data model list
The gate drive signal Gn of unit's output is pulled low to low reference voltage VGL by the 4th switch element M4 of conducting, opens when second
The output end for closing element M2 is low level, and due to boot strap, the voltage of node Q is pulled low.
Stabilization sub stage 5：When the second pulse signal Gn+1 is by high step-down, the 3rd clock signal VC is height, the 3rd switch unit
Part M3 is turned on, and the voltage of node Q is dragged down again by the 3rd switch element M3 of conducting.Therefore, within the follow-up time, i.e., surely
Determine the stage, need to make node Q and the gate drive signal Gn of drive element of the grid output maintain low level, so as to obtain ideal
Waveform.
But, because the second clock signal VB is clock signal, it goes back within the follow-up time (i.e. after the stabilization sub stage)
Pulse can ceaselessly be produced, it will impact is produced on the gate drive signal Gn of node Q and drive element of the grid output, in order to disappear
Except these impacts, the embodiment of the present invention is improved using switch element M3.
Specifically, within the follow-up time, when the second clock signal VB is by low uprising, due to the bootstrapping of the first electric capacity C1
Effect, node Q can be coupled by the first electric capacity C1 and be produced noise, but work as the 3rd clock signal VC for high level, and the second pulse
When signal Gn+1 is low level, the 3rd switch element M3 conductings, the voltage of node Q is dragged down by the 3rd switch element M3 for turning on
To low level, the gate drive signal Gn of drive element of the grid output maintains low level.
Therefore, although being affected by the second clock signal VB high level, node Q voltages can be drawn high, due to switch
The effect of element M3, it can be such that node Q voltages and the gate drive signal Gn of drive element of the grid output is able to maintain that low
Level.
Can be seen by the description to one embodiment of the invention SECO, the raster data model list of one embodiment of the invention
Unit is using the transistor of double-gate structure as input pipe (first switch element M1) and efferent duct (second switch element M2), increase
ON state current, reduces leakage current, so as to without using complicated stabilizing circuit, simple structure.Additionally, the present invention one is real
The gate driver circuit for applying example utilizes the low level of the second pulse signal Gn+1 in the stabilization sub stage by the 3rd clock signal VC again
Carry out the voltage of stable node Q, the noise of Q points is controlled well, simultaneously because the low-voltage of node Q so that raster data model list
The gate drive signal Gn of unit's output maintains low level.
The first arteries and veins that the level V of the drive element of the grid of one embodiment of the invention and drive element of the grid afterwards are received
Rush the upper level Four gate drive signal that signal Gn-4 is the drive element of the grid output for differing level Four upwards；And penultimate stage
The second pulse signal Gn+1 that drive element of the grid before drive element of the grid and penultimate stage is received is difference one downwards
The next stage gate drive signal of the drive element of the grid output of level.
It should be noted that under this connected mode, because the first order to fourth stage drive element of the grid is without upwards
The drive element of the grid of difference level Four, drive element of the grid of the afterbody drive element of the grid without difference one-level downwards, institute
With the upper level Four gate drive signal Gn-4 of the first order to fourth stage drive element of the grid, afterbody drive element of the grid is downward
The drive element of the grid Gn+1 of difference one-level is intended to be provided by external signal circuit.
It is above circuit structure and the description of sequential working figure of the first embodiment of drive element of the grid of the present invention, shows
Introduce the circuit structure and sequential working figure of second embodiment of the invention.
Fig. 3 is the electrical block diagram of the drive element of the grid of second embodiment of the invention.As shown in figure 3, of the invention
The drive element of the grid of second embodiment include drive element of the grid as in the first embodiment, wherein difference is
4th switch element M4 is single gate transistor, and in addition the drive element of the grid of second embodiment of the invention also includes the second stable mode
Block (is not indicated), and second stable module includes first input end, the second input and the first output end, and first input end is received
The second clock signal VB, the second input receives low reference voltage VGL, and the of the first output end and second switch element M2
Two control ends are connected.In the present embodiment, the second stable module include the 5th switch element M5, the 6th switch element M6, the 7th
Switch element M7 and the 8th switch element M8.Certainly, it will be appreciated by persons skilled in the art that the 4th switch element M4 also may be used
Think double-gated transistor.
Specifically, the 5th switch element M5 includes the 5th control end, the 9th path terminal and the tenth path terminal, the 5th control end
And the 9th path terminal receive the second clock signal VB.6th switch element M6 includes the 6th control end, the 11st path terminal and the
12 path terminals, the 6th control end is connected with the tenth path terminal of the 5th switch element M5, when the 11st path terminal receives second
Sequential signal VB.7th switch element M7 include the 7th control end, the tenth threeway terminal and the 14th path terminal, the 7th control end with
12nd path terminal of the 6th switch element M6 is connected, second control end of the tenth threeway terminal and the second switch element M2
It is connected, the 14th path terminal receives low reference voltage VGL.8th switch element M8 includes the 8th control end, the 15th path terminal
And the 16th path terminal, the 8th control end is connected with the alternate path end of first switch element M1, the 15th path terminal and the 6th
12nd path terminal of switch element M6 is connected, and the 16th path terminal receives low reference voltage VGL.
5th control end, the 6th control end, the 7th switch element M7 of the 6th switch element M6 of the 5th switch element M5
The 7th control end and the 8th control end of the 8th switch element M8 be grid.9th path terminal of the 5th switch element M5,
11st path terminal of the 6th switch element M6, the tenth threeway terminal of the 7th switch element M7, the of the 8th switch element M8
15 path terminals are drain electrode.Tenth path terminal of the 5th switch element M5, the 12nd path terminal of the 6th switch element M6,
14th path terminal of seven switch element M7, the 16th path terminal of the 8th switch element M8 are source electrode.
Below so that the 5th switch element to the 8th switch element M5～M8 is for N-type list gate transistor as an example specifically introducing
The specific embodiment and its operation principle of the present invention.
Fig. 4 is referred to, it is the time diagram of the drive element of the grid of second embodiment, specifically now introduce such as Fig. 4
The course of work of shown every one-level drive element of the grid, it can be divided into electric charge and reset stage 1, pre-charging stage 2, pull-up stage
3rd, drop-down stage 4,5 five stages of stabilization sub stage：
Electric charge resets the stage 1：First pulse signal Gn-4 is high level, and first switch element M1 conductings, the first sequential is believed
Number VA is low level, and voltage node Q at is pulled down to low level by the first switch element M1 of conducting.
Pre-charging stage 2：First pulse signal Gn-4 is high level, and first switch element M1 is turned on, the first clock signal
VA is high level, and node Q is precharged by the first switch element M1 for turning on.
The pull-up stage 3：First pulse signal Gn-4 is ended by high step-down, first switch element M1, but due in preliminary filling
Electric stage node Q has been electrically charged, thus second switch element M2 turn on, the second clock signal VB be high level, raster data model
The gate drive signal Gn of unit output is driven high, and due to the boot strap of the first electric capacity C1, the voltage at node Q is entered one
Step is drawn high.
It should be noted that in the present invention, can directly using the fourth passage end and second of second switch element M2
Parasitic capacitance between control end as the first electric capacity C1, or in order to lift pull-up effect, can be with second switch element
Separate storage electric capacity is set between second control end of M2 and fourth passage end, wherein, the separate storage electric capacity and second switch
The parasitic capacitance in parallel of element M2 is simultaneously equal to the parasitism of second switch element M2 collectively as the first electric capacity C1, i.e. the first electric capacity C1
Electric capacity and independent storage capacitance sum.
The drop-down stage 4：The level of the 4th clock signal VD is uprised by low, the 4th switch element M4 conductings, raster data model list
The gate drive signal Gn of unit's output is pulled low to low reference voltage VGL by the 4th switch element M4 of conducting, opens when second
It is low level to close element M2 output ends, and due to boot strap, the voltage of node Q is pulled low.
Stabilization sub stage 5：When the second pulse signal Gn+1 is by high step-down, the 3rd clock signal VC is height, the 3rd switch unit
Part M3 is turned on, and the voltage of node Q is dragged down again by the 3rd switch element M3 of conducting.Therefore, within the follow-up time, i.e., surely
Determine the stage, need to make node Q maintain low level, so as to obtain preferable waveform.
But, because the second clock signal VB is clock signal, it goes back within the follow-up time (i.e. after the stabilization sub stage)
Pulse can ceaselessly be produced, it will impact is produced on node Q, in order to eliminate these impacts, the embodiment of the present invention is using switch unit
Part M3, M5～M8 is being improved.
Specifically, within the follow-up time, when the second clock signal VB is by low uprising, due to the bootstrapping of the first electric capacity C1
Effect, node Q can be coupled by the first electric capacity C1 and be produced noise, but work as the 3rd clock signal VC for high level, and the second pulse
When signal Gn+1 is low level, the 3rd switch element M3 conductings, the voltage of node Q is dragged down by the 3rd switch element M3 for turning on
To low level, and the 5th switch element M5 is turned on, therefore the 5th switch element M5 exports high level to the 6th switch element M6,
6th switch element M6 is turned on, and P2 point voltages are pulled to high level by the 6th switch element M6 for turning on, therefore the 7th opens
Element M7 conductings are closed, and due to the boot strap of the first electric capacity C1, node Q can be coupled by the first electric capacity C1 and be produced noise, but
It is the 7th switch element M7 conductings, therefore the noises that produced due to coupling of node Q are by the 7th switch element M7 that turns on
Reduce.
Therefore, although being affected by the second clock signal VB high level, node Q can produce noise due to coupling,
It is that, due to the effect of switch element M3, it can be such that node Q noises are able to maintain that compared with low spot, and in the 3rd switch element
Switch element M5～M8 is further used on the basis of M3 so that noise is maintained compared with low spot, stability height.
Can be seen by the description to one embodiment of the invention SECO, the raster data model list of one embodiment of the invention
The switch element M3 of utilization the 3rd and the 5th switch element of unit to the 8th switch element M5～M8 so that node Q is due to coupling
The noise for acting on and producing is reduced.
In an embodiment of the present invention, the 5th switch element is N-type double-gated transistor to the 8th switch element M5～M8, when
So, it will be appreciated by persons skilled in the art that the 5th switch element can also adopt other to the 8th switch element M5～M8
Switch element and realize, such as P-type transistor.
Fig. 5 a are the cross-sectional view of the double-gate structure thin film transistor (TFT) of first embodiment of the invention.As shown in Figure 5 a,
Double-gate structure thin film transistor (TFT) 1 includes substrate 10, bottom gate layer 11, the first conductive layer 12, the second conductive layer 13, top gate layer 14 and the
Three conductive layers 15.Bottom gate layer 11 it is trapezoidal setting on the substrate 10, the 3rd conductive layer 15 is attached in bottom gate layer 11, and both sides with
Substrate 10 is fitted, and the second conductive layer 13 is attached on the 3rd conductive layer 15, and the first conductive layer is attached with again on the second conductive layer 13
12, top gate layer 14 is arranged on the first conductive layer 12.As shown in Figure 5 a, when 14 applied voltage of top gate layer, transistor equivalent to
Double-gated transistor, when 14 not applied voltage of top gate layer, transistor is equivalent to single gate transistor.
Fig. 5 b illustrate for the Current Voltage transfer characteristic curve of the double-gate structure thin film transistor (TFT) of first embodiment of the invention
Figure.Fig. 5 a and Fig. 5 b are please also refer to, as shown in Figure 5 b, a represents the voltage V of the applying of top gate layer 14GTFor 10V when and source-drain current
IDSCurve map, b represent top gate layer 14 applying voltage VGTFor 5V when with source-drain current IDSCurve map, c represents top gate layer 14
The voltage V of applyingGTFor 0V when with source-drain current IDSCurve map, d represent top gate layer 14 applying voltage VGTFor -5V when and source
Leakage current IDSCurve map, e represent top gate layer 14 applying voltage VGTFor -10V when with source-drain current IDSCurve map, by crystalline substance
The principle of body pipe and with reference to Fig. 5 b can be seen that when bottom gate layer 11 apply voltage VGBDuring less than 0V, transistor is equivalent to closing
State, its source-drain current IDSVery little, as the voltage V that bottom gate layer 11 appliesGBDuring more than 0V, transistor is opened and with bottom gate layer
The 11 voltage V for applyingGBIncrease and top gate layer 14 apply voltage VGTIncrease, source and drain electrode current also increases, therefore, when
When top gate layer 14 applies the voltage of identical polar with bottom gate layer 11, the source-drain current I of TFTDSImprove, the present invention adopts double grid crystal
Pipe increases the ON state current of gate driver circuit output end designing gate driver circuit.
Fig. 6 a export contrast schematic diagram for the simulation result of the drive element of the grid of first embodiment of the invention.Fig. 6 b are this
The simulation result output contrast schematic diagram of the drive element of the grid of invention second embodiment.As shown in Figure 6 a, Gn1 represents existing skill
The change of output signal Gn of the drive element of the grid of art, Gn3 represents the drive element of the grid of first embodiment of the invention
The change of output signal Gn；As shown in Figure 6 b, Gn1 represents the change of output signal Gn of the drive element of the grid of prior art,
Gn2 represents the change of output signal Gn of the drive element of the grid of second embodiment of the invention.Therefore can be with by Fig. 6 a and 6b
Find out, the grid of the more single gate transistor composition of signal of the output stage output of the drive element of the grid of double grid transistor npn npn composition drives
The signal stabilization of the output stage output of moving cell.
Fig. 7 a are the simulation result output noise contrast schematic diagram of the drive element of the grid of first embodiment of the invention.Fig. 7 a
Oscillogram can be obtained according to simulation software, as shown in Figure 7a, T1 for prior art drive element of the grid output noise
Change curve, T2 for the output noise of the drive element of the grid of first embodiment of the invention change curve, it is and imitative from this
The voltage variety obtained at node Q can be measured in true software, the drive element of the grid of the present invention, the voltage at node Q becomes
Change amount △ VQ1=0.1300 volts (V), and the drive element of the grid of prior art, the voltage variety △ VQ=at node Q
0.3833V.Therefore as can be seen from the above results, every one-level drive element of the grid interior joint Q of the present invention is coupled by electric capacity C1
The equal very little of degree, so as to the impact to the output end of drive element of the grid is little, that is to say, that the present invention gate driver circuit
Output noise is little.
Fig. 7 b are the simulation result output noise contrast schematic diagram of the drive element of the grid of second embodiment of the invention.Fig. 7 b
Oscillogram can be obtained according to simulation software, as shown in Figure 7b, T3 for prior art drive element of the grid output noise
Change curve, T4 for the output noise of the drive element of the grid of second embodiment of the invention change curve, it is and imitative from this
Measurement in true software obtains the voltage variety at node Q, the drive element of the grid of the present invention, the voltage variety at node Q
△ VQ2=0.13207 volts (V), and the drive element of the grid of prior art, the voltage variety △ VQ=at node Q
0.3833V.Therefore as can be seen from the above results, every one-level drive element of the grid interior joint Q of the present invention is coupled by electric capacity C1
The equal very little of degree, so as to the impact to the output end of drive element of the grid is little, that is to say, that the present invention gate driver circuit
Output noise is little.
Fig. 8 a export fall time contrast schematic diagram for the simulation result of the drive element of the grid of first embodiment of the invention.
The oscillogram of Fig. 8 a can be obtained according to simulation software, and as shown in Figure 8 a, t1 believes for the drive element of the grid output of prior art
Number voltage decline time dependent curve, t2 for the drive element of the grid output signal of first embodiment of the invention voltage
Decline time dependent curve, and measurement is obtained under the voltage of drive element of the grid output signal from the simulation software
The drop time, fall time △ t1=0.86 microseconds (us) of the voltage of the drive element of the grid output signal of the present invention, and it is existing
Voltage falling time △ t=1.54 microseconds (us) of the drive element of the grid output signal of technology.Therefore, can be with by result above
Find out, every one-level drive element of the grid output stage fall time of first embodiment of the invention is rapid, that is to say, that grid of the present invention
Pole driver element causes output stage stability more preferable using the transistor of double-gate structure.
Fig. 8 b export fall time contrast schematic diagram for the simulation result of the drive element of the grid of second embodiment of the invention.
The oscillogram of Fig. 8 b can be obtained according to simulation software, and as shown in Figure 8 b, t3 believes for the drive element of the grid output of prior art
Number voltage decline time dependent curve, t4 for the drive element of the grid output signal of second embodiment of the invention voltage
Decline time dependent curve, and measurement is obtained under the voltage of drive element of the grid output signal from the simulation software
The drop time, fall time △ t2=0.86 microseconds (us) of the voltage of the drive element of the grid output signal of the present invention, and it is existing
Voltage falling time △ t=1.62 microseconds (us) of the drive element of the grid output signal of technology.Therefore, can be with by result above
Find out, every one-level drive element of the grid output stage fall time of second embodiment of the invention is rapid, that is to say, that grid of the present invention
Pole driver element causes output stage stability more preferable using the transistor of double-gate structure.
In sum, drive element of the grid of the invention and the device using it, using the transistor conduct of double-gate structure
Input pipe (first switch element M1) and efferent duct (second switch element M2), increase ON state current, reduce leakage current,
So as to without using complicated stabilizing circuit, simple structure；Simultaneous Stabilization pipe (the 3rd switch element M3) is using double-gate structure
Transistor, and then make the noise signal of output end by reasonable control, reliability is high.
The above, is only presently preferred embodiments of the present invention, and any pro forma restriction is not made to the present invention, though
So the present invention is disclosed above with preferred embodiment, but is not limited to the present invention, any to be familiar with this professional technology people
Member, in the range of without departing from technical solution of the present invention, when making a little change or modification using the technology contents of the disclosure above
For the Equivalent embodiments of equivalent variations, as long as being without departing from technical solution of the present invention content, according to the technical spirit pair of the present invention
Any simple modification, equivalent variations and modification that above example is made, still fall within the range of technical solution of the present invention.
Claims (10)
1. a kind of drive element of the grid, it is characterised in that the drive element of the grid includes：
First switch element, including the first control end, the first path terminal and alternate path end, first control end receives first
Pulse signal, first path terminal receives the first clock signal；
Second switch element, including the second control end, third path end and fourth passage end, second control end and described
The alternate path end of one switch element is connected, and the third path end receives the second clock signal, the fourth passage end
It is connected with the alternate path end of the first switch element by the first electric capacity, the fourth passage end is used to export this level
Gate drive signal；
3rd switch element, including the 3rd control end, fifth passage end and the 6th path terminal, the 3rd control end receives the 3rd
Clock signal, the fifth passage end is connected with the alternate path end of the first switch element, the 6th path terminal
Receive the second pulse signal；
4th switch element, including the 4th control end, the 7th path terminal and the 8th path terminal, the 4th control end receives the 4th
Clock signal, the 7th path terminal is connected with the fourth passage end of the second switch element, the 8th path terminal
Receive low reference voltage；
Wherein, the first switch element, the second switch element and the 3rd switch element are double-gated transistor.
2. drive element of the grid as claimed in claim 1, it is characterised in that the 4th switch element is double-gated transistor.
3. drive element of the grid as claimed in claim 2, it is characterised in that first electric capacity is the second switch element
Third path end and fourth passage end between parasitic capacitance.
4. drive element of the grid as claimed in claim 2, it is characterised in that the third path of the second switch element
Separate storage electric capacity is provided between end and the fourth passage end, first electric capacity is the described of the second switch element
Parasitic capacitance between third path end and the fourth passage end and the separate storage electric capacity sum.
5. drive element of the grid as claimed in claim 1, it is characterised in that first control of the first switch element
3rd control end of end, second control end of the second switch element and the 3rd switch element is double grid
Pole, the 4th control end of the 4th switch element is single grid or bigrid, described the of the first switch element
One path terminal, the third path end of the second switch element, the fifth passage end of the 3rd switch element and
7th path terminal of the 4th switch element is drain electrode, the alternate path end of the first switch element, institute
State the fourth passage end, the 6th path terminal of the 3rd switch element and the 4th switch of second switch element
8th path terminal of element is source electrode.
6. drive element of the grid as claimed in claim 1, it is characterised in that the 4th switch element is single gate transistor,
The drive element of the grid also includes：
Second stable module, including first input end, the second input and the first output end, the first input end receives described
Second clock signal, second input receives the low reference voltage, first output end and second switch unit
Second control end of part is connected.
7. drive element of the grid as claimed in claim 6, it is characterised in that second stable module includes：
5th switch element, including the 5th control end, the 9th path terminal and the tenth path terminal, the 5th control end and described
Nine path terminals receive second clock signal；
6th switch element, including the 6th control end, the 11st path terminal and the 12nd path terminal, the 6th control end and institute
The tenth path terminal for stating the 5th switch element is connected, and the 11st path terminal receives second clock signal；
7th switch element, including the 7th control end, the tenth threeway terminal and the 14th path terminal, the 7th control end and institute
State the 6th switch element the 12nd path terminal be connected, the tenth threeway terminal with described in the second switch element
Second control end is connected, and the 14th path terminal receives the low reference voltage；And
8th switch element, including the 8th control end, the 15th path terminal and the 16th path terminal, the 8th control end and institute
The alternate path end for stating first switch element is connected, and described the of the 15th path terminal and the 6th switch element
12 path terminals are connected, and the 16th path terminal receives the low reference voltage.
8. drive element of the grid as claimed in claim 7, it is characterised in that the 5th switch element, the 6th switch
Element, the 7th switch element and the 8th switch element are single gate transistor.
9. drive element of the grid as claimed in claim 7, it is characterised in that the 5th control of the 5th switch element
End, the 6th control end of the 6th switch element, the 7th control end of the 7th switch element and described
8th control end of eight switch elements is single grid, the 9th path terminal of the 5th switch element, described
11st path terminal of six switch elements, the tenth threeway terminal of the 7th switch element and the 8th switch
15th path terminal of element is drain electrode, the tenth path terminal of the 5th switch element, the 6th switch
12nd path terminal of element, the 14th path terminal of the 7th switch element and the 8th switch element
16th path terminal is source electrode.
10. a kind of display device, it is characterised in that including the multistage drive element of the grid as described in any one of claim 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510070813.2A CN104732935B (en) | 2015-02-10 | 2015-02-10 | Gate driving unit and display device with gate drive unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510070813.2A CN104732935B (en) | 2015-02-10 | 2015-02-10 | Gate driving unit and display device with gate drive unit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104732935A CN104732935A (en) | 2015-06-24 |
| CN104732935B true CN104732935B (en) | 2017-05-10 |
Family
ID=53456777
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510070813.2A Active CN104732935B (en) | 2015-02-10 | 2015-02-10 | Gate driving unit and display device with gate drive unit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104732935B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105261341B (en) * | 2015-11-11 | 2017-11-03 | 昆山龙腾光电有限公司 | A kind of gate driving circuit and display device |
| CN113196368B (en) * | 2019-09-25 | 2023-05-23 | 京东方科技集团股份有限公司 | Shift register unit, driving method, grid driving circuit and display device |
| WO2021179329A1 (en) * | 2020-03-13 | 2021-09-16 | 京东方科技集团股份有限公司 | Shift register, driving method, gate drive circuit, and display device |
| CN116802725A (en) * | 2021-12-29 | 2023-09-22 | 京东方科技集团股份有限公司 | Display substrate, driving method thereof and display panel |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5090008B2 (en) * | 2007-02-07 | 2012-12-05 | 三菱電機株式会社 | Semiconductor device and shift register circuit |
| US9129576B2 (en) * | 2008-05-06 | 2015-09-08 | Himax Technologies Limited | Gate driving waveform control |
| CN102682692B (en) * | 2012-05-21 | 2014-11-05 | 京东方科技集团股份有限公司 | Shift register, drive device and displayer |
| CN104077992B (en) * | 2013-03-29 | 2016-12-28 | 北京京东方光电科技有限公司 | A kind of shift register cell, shift register, display floater and display |
| CN203179555U (en) * | 2013-04-27 | 2013-09-04 | 京东方科技集团股份有限公司 | Shifting register unit, shifting register and display device |
| TWI512740B (en) * | 2014-05-07 | 2015-12-11 | Au Optronics Corp | Shift register apparatus and voltage regulating device thereof |
-
2015
- 2015-02-10 CN CN201510070813.2A patent/CN104732935B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN104732935A (en) | 2015-06-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103208263B (en) | Shift register, display device, gate drive circuit and driving method | |
| CN103310755B (en) | Array base palte horizontal drive circuit | |
| CN103413531B (en) | A kind of shift register cell, gate driver circuit and display device | |
| CN105185292B (en) | Gate driving circuit and display device | |
| CN105261341B (en) | A kind of gate driving circuit and display device | |
| CN105469763B (en) | Drive element of the grid, gate driving circuit and display device | |
| CN103065592B (en) | Shift register unit and driving method, gate drive circuit and displaying device thereof | |
| CN107958656A (en) | GOA circuits | |
| CN104318909A (en) | Shift register unit, gate drive circuit, drive method thereof, and display panel | |
| CN104715730B (en) | A kind of gate driving circuit and display device | |
| CN104715732B (en) | Grid driving circuit and display device | |
| CN104299591B (en) | Array substrate line driving circuit and liquid crystal display device | |
| CN104637461B (en) | A kind of gate driver circuit and display device | |
| CN105469759B (en) | A kind of shift register | |
| CN103151013B (en) | Gate driver circuit | |
| CN204189456U (en) | Shift register cell, gate driver circuit, display panel | |
| CN104732935B (en) | Gate driving unit and display device with gate drive unit | |
| CN105788553A (en) | GOA circuit based on LTPS semiconductor thin film transistor | |
| CN108062935A (en) | A kind of gate driving circuit and display device | |
| CN105047118A (en) | Reversing circuit and driving method thereof and a touch control display panel and device | |
| CN106611582A (en) | Shift register, grid driving circuit, display panel and driving method | |
| CN103996390B (en) | A kind of gate driver circuit and the display device using which | |
| CN106486075A (en) | Goa circuit | |
| CN106409243A (en) | GOA driving circuit | |
| CN103854622A (en) | Gate drive circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Patentee after: InfoVision Optoelectronics(Kunshan)Co.,Ltd. Address before: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Patentee before: INFOVISION OPTOELECTRONICS (KUNSHAN) Co.,Ltd. |
|
| CP01 | Change in the name or title of a patent holder |