CN104425583B - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate, a first doped region (doping region), a first well (well), a first heavily doped region (doping region), a second heavily doped region, a third heavily doped region, and a resistive element. The first doped region is disposed on the substrate, and the first well is disposed in the first doped region. The first heavily doped region is disposed in the first well. The second heavily doped region is arranged in the first well and is spaced from the first heavily doped region. The third heavily doped region is disposed in the first doped region, and the second heavily doped region is electrically connected to the third heavily doped region through a resistor element. The substrate, the first well and the second heavily doped region have a first doping type, the first doped region, the first heavily doped region and the third heavily doped region have a second doping type, and the first doping type is complementary to the second doping type.

Description

Semiconductor device and manufacturing method thereof

technical field

The present disclosure relates to a semiconductor device and its manufacturing method, and more particularly to a semiconductor device with low substrate leakage and its manufacturing method.

Background technique

With the development of semiconductor technology, various semiconductor components are constantly being introduced. For example, components such as memories, transistors, and diodes have been widely used in various electronic devices.

In the development of semiconductor technology, researchers are constantly trying to improve various components, such as reducing volume, increasing/decreasing startup voltage, increasing/decreasing breakdown voltage, reducing leakage, electrostatic protection and other issues.

Contents of the invention

The disclosure is related to a semiconductor device and a manufacturing method thereof. In an embodiment, the semiconductor device includes a thyristor, and the base of the equivalent NPN transistor of the thyristor is electrically connected to the collector (equivalent to the base of the equivalent PNP transistor) through a resistance element, so that the two There is a voltage difference between them, so unnecessary current can be directed to the collector of the equivalent NPN transistor, thereby reducing the substrate leakage of the semiconductor device and improving the electrostatic discharge (ESD) protection effect.

According to an embodiment of the disclosure, a semiconductor device is provided. The semiconductor device includes a substrate, a first doping region, a first well, a first heavily doping region, a second heavily doping region, a third heavily doped region and a resistance element. The first doped region is arranged on the substrate, and the first well is arranged in the first doped region. The first heavily doped region is disposed in the first well. The second heavily doped region is arranged in the first well, and the second heavily doped region is separated from the first heavily doped region. The third heavily doped region is disposed in the first doped region, and the second heavily doped region is electrically connected to the third heavily doped region through a resistance element. The substrate, the first well and the second heavily doped region have a first doping type, the first doping region, the first heavily doped region and the third heavily doped region have a second doping type, The first doping type is complementary to the second doping type.

According to another embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device includes a thyristor and a resistor. The thyristor has an equivalent NPN transistor and an equivalent PNP transistor. The base of the equivalent NPN transistor is electrically connected to the base of the equivalent PNP transistor via the resistance element.

According to yet another embodiment of the disclosure, a method for manufacturing a semiconductor device is provided. A method of manufacturing a semiconductor device includes the following steps. providing a substrate; forming a first doped region on the substrate; forming a first well in the first doped region; forming a first heavily doped region in the first well; forming a second heavily doped The impurity region is in the first well, the second heavily doped region is separated from the first heavily doped region; a third heavily doped region is formed in the first doped region; and a resistance element is formed, the second The heavily doped region is electrically connected to the third heavily doped region via a resistance element. The substrate, the first well and the second heavily doped region have a first doping type, the first doping region, the first heavily doped region and the third heavily doped region have a second doping type, The first doping type is complementary to the second doping type.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the preferred embodiments are specifically cited below, together with the attached drawings, and are described in detail as follows:

Description of drawings

FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment.

2A to 2D are flow charts of the manufacturing method of the semiconductor device of the first embodiment.

FIG. 3 is a cross-sectional view of the semiconductor device of the second embodiment.

4A-4F are flow charts of the manufacturing method of the semiconductor device of the second embodiment.

FIG. 5 is a cross-sectional view of the semiconductor device of the third embodiment.

FIG. 6 is a cross-sectional view of a semiconductor device of a fourth embodiment.

FIG. 7 is a schematic diagram of an equivalent transistor of the semiconductor device of the second embodiment.

FIG. 8 illustrates an equivalent circuit diagram of a semiconductor device according to some embodiments of the present disclosure.

FIG. 9 shows an I-V curve of the semiconductor device of the second embodiment.

【Symbol Description】

100, 200, 300, 400: semiconductor device

110P: Substrate

120: epitaxial layer

121P: first well

123P: second well

125N: the third well

130N, 230N: the first doped region

141N: the first heavily doped region

143P: Second heavily doped region

145N: the third heavily doped region

147P: the fourth heavily doped region

150: resistance element

160, 161: field oxide layer

171: first electrode

172: second electrode

173: third electrode

181, 183: Equivalent NPN transistor

231N: buried layer

I, II: curve

ML1, ML2: metal layer

Vanode: anode voltage

Detailed ways

In an embodiment of this summary of the invention, a semiconductor device and a manufacturing method thereof are provided. In an embodiment, the semiconductor device includes a thyristor, and the base of the equivalent NPN transistor of the thyristor is electrically connected to the collector (equivalent to the base of the equivalent PNP transistor) through a resistance element, so that the two There is a voltage difference between them, so unnecessary current can be directed to the collector of the equivalent NPN transistor, thereby reducing the substrate leakage of the semiconductor device and improving the electrostatic discharge protection effect. However, the embodiments are only used for illustration and shall not limit the scope of protection of the present invention. In addition, the drawings in the embodiments omit some important components to clearly show the technical characteristics of the present invention.

first embodiment

Please refer to FIG. 1 , which shows a cross-sectional view of a semiconductor device 100 according to a first embodiment. The semiconductor device 100 includes a substrate 110P, a first doping region (doping region) 130N, a first well (well) 121P, a first heavily doping region (heavily doping region) 141N, a second heavily doping region 143P, a third heavily doping region The doped region 145N and the resistive element 150 .

The material of the substrate 110P is, for example, P-type silicon or N-type silicon. The first doped region 130N is disposed on the substrate 110P, and the first well 121P is disposed in the first doped region 130N. The first doped region 130N and the first well 121P are, for example, P type wells (P type wells) or N type wells (N type wells), and the first doped region 130N can also be, for example, N type deep wells (deep N type wells). The first well 121P can also be, for example, a P-type well/P-type heavily doped buried layer (P+buried layer) laminated layer, a P-type heavily doped layer (P+implant layer), an N-type well/N-type heavily doped layer Doped buried layer (N+buried layer) stacked layer, N-type heavily doped layer (N+implant layer) or N-type deep well.

The first heavily doped region 141N is disposed in the first well 121P, the second heavily doped region 143P is disposed in the first well 121P, and the second heavily doped region 143P is separated from the first heavily doped region 141N. The third heavily doped region 145N is disposed in the first doped region 130N. The doping concentration of the first heavily doped region 141N, the second heavily doped region 143P and the third heavily doped region 145N is greater than that of the first well 121P and the first doped region 130N, so as to provide a good ohmic contact (Ohmic contact). The first heavily doped region 141N, the second heavily doped region 143P and the third heavily doped region 145N are, for example, a P type heavily doped region (P+) or an N type heavily doped region (N type heavily doped region, P+). doping region, N+).

The second heavily doped region 143P is electrically connected to the third heavily doped region 145N through the resistance element 150 . The resistor element 150 is, for example, a polysilicon layer.

The substrate 110P, the first well 121P and the second heavily doped region 143P have a first doping type (such as P type or N type), and the first doped region 130N, the first heavily doped region 141N and the second The triple doped region 145N has a second doping type (for example, N-type or P-type), and the first doping type is complementary to the second doping type. In this embodiment, the first doping type is P type, and the second doping type is N type.

As shown in FIG. 1 , in the embodiment, the semiconductor device 100 may further include a field oxide (FOX) 161, the field oxide layer 161 is disposed on the first well 121P, and is located in the first heavily doped region 141N and the second well. Between the double doped region 143P, the two are spaced apart. In addition, the semiconductor device 100 of this embodiment may further include a field oxide layer 160 , and the field oxide layer 160 may be disposed on the adjacent portion of the first well 121P and the first doped region 130N. The material of the field oxide layers 160 and 161 is, for example, silicon dioxide (Si0 ₂ ), and its structure is, for example, area oxide of silicon (LOCOS) as shown in FIG. 1 , or shallow trench isolation (STI).

In an embodiment, the resistance element 150 may be disposed in the internal structure of the semiconductor device 100 or in an external structure. In this embodiment, as shown in FIG. 1 , the polysilicon layer (resistive element 150 ) is disposed on the field oxide layer 161 above the first well 121P. Compared with the external structure, the resistive element 150 is disposed on the semiconductor device 100 In the internal structure, the size of the overall structure can be effectively reduced.

In an embodiment, as shown in FIG. 1 , the semiconductor device 100 may further include a second well 123P. The second well 123P is disposed on the substrate 110P. The first doped region 130N is disposed between the first well 121P and the second well 123P, and the second well 123P has a first doping type.

In an embodiment, as shown in FIG. 1 , the semiconductor device 100 may further include a fourth heavily doped region 147P. The fourth heavily doped region 147P is disposed in the second well 123P, and the fourth heavily doped region 147P has the first doping type.

As shown in FIG. 1, the paths of the first electrode 171, the first heavily doped region 141N, the first well 121P, the second heavily doped region 143P, the resistance element 150 and the second electrode 172 form an isolation diode. . In forward bias, there will be at least 0.7 volts (V) of impedance; in reverse bias, there will be at least 30 volts of impedance.

In addition, the first heavily doped region 141N can be electrically connected to the first electrode 171, and the second heavily doped region 143P can be electrically connected to the second electrode 172 through the resistance element 150, and the second electrode 172 is also electrically connected to the first electrode 172. The triple doped region 145N is electrically connected to the fourth heavily doped region 147P with the third electrode 173 . The first electrode 171 is, for example, a cathode, the second electrode 172 is, for example, an anode, and the third electrode 173 is, for example, a ground terminal. Due to the resistance element 150, there is a voltage difference between the first doped region 130N where the third heavily doped region 145N is located and the first well 121P, so that in forward bias, the potential of the first doped region 130N is higher than The potential of the first well 121P can guide unnecessary current to the second electrode 172, thereby reducing substrate leakage and improving the protection effect of electrostatic discharge (ESD). The detailed mechanism of action is discussed in the following paragraphs of this article.

In addition, the configuration of the polysilicon layer (resistor element 150), in addition to the effect of reducing substrate leakage and improving ESD protection as mentioned above, can also improve the performance of the insulating transistor because the polysilicon layer still has the effect of a field effect plate. breakdown voltage.

Please refer to FIG. 2A to FIG. 2D , which illustrate the flowchart of the manufacturing method of the semiconductor device 100 according to the first embodiment. First, as shown in FIG. 2A, a substrate 110P is provided.

Next, as shown in FIG. 2B , a first doped region 130N is formed on the substrate 110P, and a first well 121P is formed in the first doped region 130N. In an embodiment, the second well 123P may be further formed on the substrate 110P, and the first doped region 130N is formed between the first well 121P and the second well 123P. In an embodiment, the first doped region 130N, the first well 121P, and the second well 123P are manufactured by, for example, a triple well process, which does not require additional epitaxy steps and can reduce manufacturing costs.

Next, as shown in FIG. 2C, a field oxide layer 161 is formed on the first well 121P between the first heavily doped region 141N and the second heavily doped region 143P, and a field oxide layer 160 can also be formed on the first well. 121P and adjacent to the first doped region 130N.

Then, as shown in FIG. 2C, a first heavily doped region 141N and a second heavily doped region 143P are formed in the first well 121P, and the second heavily doped region 143P is spaced apart from the first heavily doped region 141N, A third heavily doped region 145N is formed in the first doped region 130N. In an embodiment, the fourth heavily doped region 147P may also be formed in the second well 123P.

Next, as shown in FIG. 2D , a resistive element 150 is formed on the field oxide layer 161 . In another embodiment, the anode element 150 may also be formed on the field oxide layer 161 before forming the heavily doped regions 141N, 143P, 145N and 147P. In an embodiment, the resistance element 150 is formed by a polysilicon layer, for example. Through the above steps, the semiconductor device 100 of this embodiment can be successfully completed.

second embodiment

Please refer to FIG. 3 , which shows a cross-sectional view of a semiconductor device 200 according to a second embodiment. The difference between the semiconductor device 200 of this embodiment and the semiconductor device 100 of the first embodiment lies in the design of the first doped region 230N, and the rest of the similarities will not be described again.

As shown in FIG. 3 , the first doped region 230N includes a buried layer 231N and a third well 125N. In an embodiment, the doping concentration of the buried layer 231N is greater than that of the third well 125N. The buried layer 231N is disposed under the first well 121P, the third well 125N is disposed on the buried layer 231N, and the third well 125N is disposed between the first well 121P and the second well 123P. The materials of the buried layer 231N and the third well 125N in this embodiment are substantially the same. In this embodiment, the buried layer 231N is, for example, an N type buried layer (NBL), an N type epitaxial layer (N-epi), an N type deep well (deep N type well) or an N type Doped stacked layer (multiple N+stacked layer).

Please refer to FIG. 4A˜FIG. 4F , which illustrate the flowchart of the manufacturing method of the semiconductor device 200 according to the second embodiment. First, as shown in FIG. 4A, a substrate 110P is provided.

Then, as shown in FIG. 4B , a buried layer 231N is formed on the substrate 110P. In an embodiment, the buried layer 231N is formed under the first well 121P to be formed.

Then, as shown in FIG. 4C , an epitaxial layer 120 is formed on the substrate 110P and the buried layer 231N.

Next, as shown in FIG. 4D , a first well 121P and a third well 125N are formed on the buried layer 231N, and the buried layer 231N and the third well 125N form a first doped region 230N. In an embodiment, the second well 123P may be formed on the substrate 110P, and the third well 125N is formed between the first well 121P and the second well 123P. In an embodiment, the first well 121P and the second well 123P are manufactured by, for example, a twin well process, without adding additional masks or steps.

Next, as shown in FIG. 4E, a field oxide layer 161 is formed on the first well 121P between the first heavily doped region 141N and the second heavily doped region 143P, and a field oxide layer 160 can also be formed on the first well. 121P and adjacent to the first doped region 230N (third well 125N).

Then, as shown in FIG. 4E, a first heavily doped region 141N and a second heavily doped region 143P are formed in the first well 121P, and the second heavily doped region 143P is separated from the first heavily doped region 141N. Next, the third heavily doped region 145N is formed in the first doped region 230N. In an embodiment, the fourth heavily doped region 147P may also be formed in the second well 123P.

Next, as shown in FIG. 4F , a resistive element 150 is formed on the field oxide layer 161 . In an embodiment, the resistance element 150 is formed by a polysilicon layer, for example. Through the above steps, the semiconductor device 200 of this embodiment can be successfully completed.

third embodiment

Please refer to FIG. 5 , which shows a cross-sectional view of a semiconductor device 300 according to a third embodiment. The difference between the semiconductor device 300 of this embodiment and the semiconductor device 100 of the first embodiment lies in the configuration of the resistance element 150 , and the rest of the similarities will not be described again.

In an embodiment, as shown in FIG. 5 , the polysilicon layer (resistive element 150 ) is disposed on the first well 121P, and is located between the first heavily doped region 141N and the second heavily doped region 143P, and the two spaced out.

As far as the manufacturing method of the semiconductor device 300 of this embodiment is concerned, the main difference from the semiconductor device 100 of the first embodiment is that the field oxide layer 161 as shown in FIG. 1 is not formed. In other words, during the manufacturing process of the semiconductor device 300, the field oxide layer 160 is formed, and the resistance element 150 is formed on the first well 121P. Between the doped regions 143P, each heavily doped region is formed next. The resistance element 150 formed earlier can also have an effect similar to that of the field oxide layer (such as the field oxide layer 161 shown in FIG. . The remaining similarities between the manufacturing method of this embodiment and the manufacturing method of the first embodiment will not be repeated.

Fourth embodiment

Please refer to FIG. 6 , which shows a cross-sectional view of a semiconductor device 400 according to a fourth embodiment. The difference between the semiconductor device 400 of this embodiment and the semiconductor device 200 of the second embodiment lies in the configuration of the resistance element 150 , and the rest of the similarities will not be described again.

In an embodiment, as shown in FIG. 6, the polysilicon layer (resistive element 150) is disposed on the first well 121P, and is located between the first heavily doped region 141N and the second heavily doped region 143P, and the two spaced out.

As far as the manufacturing method of the semiconductor device 400 of this embodiment is concerned, the main difference from the semiconductor device 200 of the first embodiment is that the field oxide layer 161 as shown in FIG. 2 is not formed. In other words, during the manufacturing process of the semiconductor device 400, the field oxide layer 160 is formed, and the resistance element 150 is formed on the first well 121P. Between the doped regions 143P, each heavily doped region is formed next. The resistance element 150 formed earlier can also have an effect similar to that of the field oxide layer (for example, the field oxide layer 161 shown in FIG. . The remaining similarities between the manufacturing method of this embodiment and the manufacturing method of the second embodiment will not be repeated.

The following takes the semiconductor device 200 as an example to illustrate the electrical characteristics of the structure of the present invention. However, the electrical characteristics described above are not limited to the semiconductor device 200 , and structural changes and modifications of the semiconductor device 100 to the semiconductor device 400 are applicable without departing from the spirit and scope of the present application.

Please refer to FIG. 7 , which shows a schematic diagram of an equivalent transistor of the semiconductor device 200 according to the second embodiment. As shown in FIG. 7 , the substrate 110P, the first doped region 230N, the first well 121P and the first heavily doped region 141N form a thyristor, which has an equivalent NPN transistor (for example are equivalent NPN transistors 181, 183) and an equivalent PNP transistor (such as equivalent NPN transistors 185, 187). The equivalent NPN transistor is formed by, for example, the first doped region 230N, the first well 121P and the first heavily doped region 141N, and the equivalent PNP transistor is formed by, for example, the substrate 110P, the first doped region 230N and the first well 121P. The base of the equivalent NPN transistor (for example, the second heavily doped region 143P) is electrically connected to the base of the equivalent PNP transistor (for example, the third heavily doped region 145N) via the resistance element 150 . In a thyristor, the base of the equivalent PNP transistor is also the collector of the equivalent NPN transistor.

As shown in FIG. 7, the resistance element 150 is disposed on the field oxide layer 161, and the first doped region 230N (such as the third well 125N and/or the buried layer 231N) is electrically connected through the metal layer ML2, the resistance element 150, and the metal layer ML1. is connected to the first well 121P, and the resistance element 150 makes the first well 121P (such as the base of the equivalent NPN transistor 181, 183) and the first doped region 230N (such as the collector of the equivalent NPN transistor 181, 183 ), and the potential of the first doped region 230N is higher than the potential of the first well 121P, so that the first well 121P (such as the bases of the equivalent NPN transistors 181, 183) and the first doped region A depletion region is generated in the middle of the impurity region 230N (such as the collectors of the equivalent NPN transistors 181 and 183), which is conducive to the flow of current, and then is beneficial to the equivalent NPN transistor (such as the equivalent NPN transistor 181 and the equivalent NPN transistor 183) operation. In this way, based on the operation of the equivalent NPN transistor, the current is driven to flow through the first doped region 230N and then through the metal layer ML2 to the second electrode 172 (for example, the collectors of the equivalent NPN transistors 181 and 183 ), so that The flow of current to the end of the third electrode 173 through the second well 123P and/or the substrate 110P is reduced, so as to reduce the leakage of the substrate and improve the protection effect of the overall electrostatic discharge.

Please refer to FIG. 8 , which illustrates an equivalent circuit diagram of a semiconductor device according to some embodiments of the present invention. As shown in FIG. 8 , the resistance element 150 causes a voltage difference between the base and the collector of the NPN equivalent transistor, thereby achieving the effect of reducing substrate leakage.

Please refer to FIG. 9 , which shows the I-V curve diagram of the semiconductor device 200 of the second embodiment, wherein the curve I represents the relationship between the known substrate leakage of the insulating transistor and the applied anode voltage Vanode, and the curve II represents the relationship between the semiconductor device 200. The relationship between the substrate leakage of the device 200 and the anode voltage Vanode applied to the second electrode 172 . In an embodiment, the third electrode 173 shown in FIG. 7 is, for example, a test electrode, and the current value of the substrate leakage is measured through the third electrode 173 . As shown in Figure 9, when the anode voltage Vanode rises from 5 volts to more than about 6.2 volts, the substrate leakage shown in curve I has reached the milliampere (mA) level, while the substrate leakage shown in curve II is still At the microampere (μA) level, the two differ by more than two orders. In other words, the semiconductor device according to the embodiments of the present invention can effectively and greatly reduce the substrate leakage of the insulating transistor.

In summary, although the present invention has been described above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (16)

1. a kind of semiconductor device, including：

One substrate；

One first doped region (doping region), is arranged on the substrate；

One first trap (well), is arranged in first doped region；

One first heavily doped region (heavily doping region), is arranged in first trap；

One second heavily doped region, is arranged in first trap, which be spaced apart with first heavily doped region；

One the 3rd heavily doped region, is arranged in first doped region；And

One resistive element, second heavily doped region are electrically connected at the 3rd heavily doped region via the resistive element；

Wherein the resistive element is a polysilicon layer, and the substrate, first trap and second heavily doped region have one first doping Kenel, first doped region, first heavily doped region and the 3rd heavily doped region have one second dopant profile, first doping Kenel is complementary to second dopant profile.

2. semiconductor device according to claim 1, further includes one second trap, is arranged on the substrate, wherein this first Doped region is arranged between first trap and second trap, which has first dopant profile.

3. semiconductor device according to claim 2, further includes one the 4th heavily doped region, it is arranged in second trap, should 4th heavily doped region has first dopant profile.

4. semiconductor device according to claim 1, the wherein polysilicon layer be arranged on first trap and positioned at this Between one heavily doped region and second heavily doped region.

5. semiconductor device according to claim 1, further includes a field oxide (field oxide, FOX), this oxygen Change layer to be arranged on first trap and between first heavily doped region and second heavily doped region.

6. semiconductor device according to claim 5, the wherein resistive element are a polysilicon layer, which is set In on the field oxide.

7. semiconductor device according to claim 2, wherein first doped region include：

One buried regions (buried layer), is arranged at the lower section of first trap；And

One the 3rd trap, is arranged on the buried regions, and wherein the 3rd trap is arranged between first trap and second trap.

8. a kind of semiconductor device, including：

One thyristor (thyristor), has an equivalent NPN transistor and an equivalent PNP transistor；And

One resistive element, the base stage of the equivalent NPN transistor are directly electrically connected at the equivalent PNP crystal via the resistive element The base stage of pipe；

Wherein the resistive element is a polysilicon layer, and the collector of the equivalent NPN transistor is electrically connected at a second electrode, and The emitter of the equivalent PNP transistor is electrically connected at via the resistive element, the emitter of the equivalent NPN transistor electrically connects It is connected to first electrode；The emitter of the equivalent PNP transistor is electrically connected to the second electrode via the resistive element, this is equivalent The collector of PNP transistor is electrically connected at the 3rd electrode.

9. semiconductor device according to claim 8, the wherein thyristor include：

One substrate；

One first doped region, is arranged on the substrate；

One first trap, is arranged in first doped region；And

One first heavily doped region, is arranged in first trap；

Wherein the substrate and first trap have one first dopant profile, and first doped region and first heavily doped region have one Second dopant profile, first dopant profile are complementary to second dopant profile.

10. a kind of manufacture method of semiconductor device, including：

One substrate is provided；

One first doped region is formed on the substrate；

One first trap is formed in first doped region；

One first heavily doped region is formed in first trap；

One second heavily doped region is formed in first trap, which be spaced apart with first heavily doped region；

One the 3rd heavily doped region is formed in first doped region；And

A resistive element is formed, which is electrically connected at the 3rd heavily doped region via the resistive element；

Wherein the resistive element is a polysilicon layer, and the substrate, first trap and second heavily doped region have one first doping Kenel, first doped region, first heavily doped region and the 3rd heavily doped region have one second dopant profile, first doping Kenel is complementary to second dopant profile.

11. the manufacture method of semiconductor device according to claim 10, further includes：

One second trap is formed on the substrate, wherein first doped region is formed between first trap and second trap, this Two traps have first dopant profile.

12. the manufacture method of semiconductor device according to claim 11, further includes：

One the 4th heavily doped region is formed in second trap, the 4th heavily doped region has first dopant profile.

13. the manufacture method of semiconductor device according to claim 10, wherein the step of forming the resistive element includes：

The polysilicon layer is formed on first trap and between first heavily doped region and second heavily doped region.

14. the manufacture method of semiconductor device according to claim 10, further includes：

A field oxide is formed on first trap and between first heavily doped region and second heavily doped region.

15. the manufacture method of semiconductor device according to claim 14, wherein the step of forming the resistive element includes：

The polysilicon layer is formed on the field oxide.

16. the manufacture method of semiconductor device according to claim 11, wherein forming first doped region in the substrate On step include：

A buried regions is formed in the lower section of first trap；And

One the 3rd trap is formed on the buried regions, wherein the 3rd trap is formed between first trap and second trap.