CN104393759A - DC-DC (direct current-direct current) converter with line loss compensation function - Google Patents

Abstract

The invention discloses a DC-DC (direct current-direct current) converter with a line loss compensation function. The converter comprises a control circuit, a filter circuit, a feed circuit and a line loss compensation circuit, wherein chip-end output voltage is generated after input voltage passes through the control circuit and the filter circuit, and load-end output voltage is generated after the input voltage passes through a line loss resistor and used for supplying power to a load end; the chip-end output voltage is fed back to the control circuit through a feedback resistor and a compensation resistor; the line loss compensation circuit is used for obtaining load current by detecting the voltage of the output end of an error amplifier in the control circuit, extracting compensation current proportional to the load current from a feedback port of the compensation resistor, and compensating the line loss voltage drop of the load-end output voltage. According to the converter, linear line loss compensation can be performed and compensation voltage can be completely equal to loss voltage, so that the output voltage cannot be changed along with the load current and remains unchanged; the compensation value can be flexibly set by an external resistor, and the converter can be applied to a system with different line loss resistors.

Description

With the dc-dc of line loss compensation

Technical field

The present invention relates to the line loss compensation technology of output voltage in electric pressure converter, especially a kind of dc-dc with line loss compensation function.

Background technology

As shown in Figure 1, the output voltage of electric pressure converter makes feedback voltage FB and internal reference voltage V by control loop _rEFequal realization, the output voltage of DC-DC chip is:

$V_{\mathrm{OUT}1}=V_{\mathrm{REF}}(1+\frac{R_{F1}}{R_{F2}})---\left(1\right)$

But electric pressure converter is when powering to external loading, and the output of DC-DC chip exists the line loss resistance R formed by interface resistance, wire dead resistance etc. to load end _p, this resistance produces voltage loss, causes the output voltage of load end to be:

$V_{\mathrm{OUT}}=V_{\mathrm{REF}}(1+\frac{R_{F1}}{R_{F2}})-I_O{R}_P---\left(2\right)$

Finally, the output voltage of load end is lower than chip output voltage, and when big current is powered, this effect is more serious, often makes the output voltage of load end be low to moderate and exceeds acceptable scope, therefore need to compensate this loss voltage.

Summary of the invention

The present invention is intended to the deficiency solving prior art existence, and provide one can keep load end output voltage not with load current change, namely load end output voltage can keep the dc-dc of constant band line loss compensation.

Technical scheme of the present invention is as follows:

With a dc-dc for line loss compensation, comprise control circuit and filter circuit, feedback circuit, line loss compensation circuit; Input voltage produces die terminals output voltage after described control circuit and filter circuit, and described die terminals output voltage produces load end output voltage after line loss resistance, and described load end output voltage is that load end is powered; Described die terminals output voltage feeds back to control circuit through the feedback resistance of feedback circuit and the compensating resistance of line loss compensation circuit simultaneously; Described line loss compensation circuit obtains load current by the voltage of the error amplifier output in detection control circuit, and extract one with the proportional offset current of described load current from the feedback port of described compensating resistance, compensate to control circuit, the line loss pressure drop of load end output voltage is compensated.

Its further technical scheme is:

Described line loss compensation circuit comprises operational amplifier, the input in the same way of operational amplifier connects the output end voltage of error amplifier, the reverse input end of operational amplifier is connected with the source electrode of the first NMOS tube, and the output of operational amplifier is connected with the grid of the first NMOS tube;

First PMOS is connected with the grid of the second PMOS, and the second NMOS tube is connected with the grid of the 3rd NMOS tube, and the 4th NMOS tube is connected with the grid of the 5th NMOS tube; The grid of the first PMOS is connected with drain electrode, and the grid of the second NMOS tube is connected with drain electrode, and the grid of the 4th NMOS tube is connected with drain electrode; The drain electrode of the first NMOS tube, the first PMOS is connected, and the drain electrode of the 3rd NMOS tube, the 4th NMOS tube, the second PMOS is connected;

The source electrode of the first PMOS, the second PMOS connects supply voltage; The source ground of the second NMOS tube, the 3rd NMOS tube, the 4th NMOS tube, the 5th NMOS tube; The source electrode of the first NMOS tube connects ground connection after the second resistance;

The drain electrode of the first NMOS tube connects direct current I _dC2; The drain electrode of the second NMOS tube connects direct current I _slop2; The feedback port of described compensating resistance is connected after drain electrode connection the 3rd resistance of the 5th NMOS tube.

And its further technical scheme is:

Described direct current I _slop2the slope compensation current I produced with described control circuit _slopequal;

Described direct current I _dC2the fixing direct current I produced with described control circuit _dCratio be: I _dC: I _dC2=n:1;

Slope compensation current I is connected in described second resistance and described control circuit _slopthe resistance type of the first drop-down resistance of output is identical, and the ratio of the resistance of the first resistance and the second resistance is: R1:R2=1:n;

The ratio of the breadth length ratio of described second NMOS tube and the 3rd NMOS tube is: (W/L) ₂: (W/L) ₃=n:1;

The ratio of the breadth length ratio of described 4th NMOS tube and the 5th NMOS tube is: (W/L) ₄: (W/L) ₅=1:m.

Advantageous Effects of the present invention is:

One, the present invention can realize linear line loss compensation, and bucking voltage can be completely the same with loss voltage, makes output voltage not with load current change, keeps constant.

Two, offset of the present invention can be set flexibly by outer meeting resistance, can be applicable to the system of different line loss resistance.

Three, current sample of the present invention is realized by chip internal, and chip, without the need to increasing extra PIN, reduces chip complexity, saves cost.

Advantage of the present invention provides in the description of embodiment part below, and part will become obvious from the following description, or be recognized by practice of the present invention.

Accompanying drawing explanation

Fig. 1 is the system block diagram of existing electric pressure converter.

Fig. 2 is block diagram of the present invention.

Fig. 3 is the physical circuit figure of line loss compensation module of the present invention.

Fig. 4 is offset current of the present invention and load current relation curve.

Fig. 5 is that existing electric pressure converter compares with output voltage curve of the present invention.

Embodiment

Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described further.

Fig. 2 shows block diagram of the present invention.As shown in Figure 2, the dc-dc of band line loss compensation of the present invention comprises: control and filter circuit, feedback circuit, line loss compensation circuit, wherein line loss compensation circuit is core of the present invention.Control and filter circuit comprise control circuit and filter circuit two parts.Control circuit comprises the main modular of conventional peak current mode DC-DC: base modules (REF), oscillator and slope compensation module (OSC & Slope Comp), current detection module (CS), error amplifier (EA), PWM comparator (PWM), application of logic circuit module (Logic) and power tube (MH, ML); Filter circuit comprises inductance L and electric capacity C1.Feedback circuit comprises resistance R _f1, R _f2.Line loss compensation circuit comprises line loss compensation module (G _m) and resistance R _c.

Input voltage V _iNinput above-mentioned control and filter circuit, produce voltage V _oUT1.Voltage V _oUT1through resistance R _f1, R _f2, R _cafter dividing potential drop, produce voltage FB and input to control circuit.Voltage V _oUT1through line loss resistance R _pafter output voltage be V _oUT.Line loss compensation module G _mthe output V of input termination error amplifier EA _c, line loss compensation module G _moutput termination voltage FB.Line loss compensation module G _mcan according to V _cvalue extract the electric current I of different value from FB port _c, thus the line loss pressure drop of output voltage is compensated, keep the output voltage V of load end _oUTconstant.

In Fig. 2, resistance R _f1, R _f2, R _cthe resistor network formed, with line loss compensation module G _mcommon formation collocation structure.

FB _xthe voltage of point is:

FB _X＝FB+I _CR _C

(3)

＝REF+I _CR _C

Then V _oUT1the voltage of point is:

$V_{\mathrm{OUT}1}={\mathrm{FB}}_X+(\frac{{\mathrm{FB}}_X}{R_{F2}}+I_C)R_{F1}---\left(4\right)$

Bring formula (3) into formula (4):

$V_{\mathrm{OUT}1}=\mathrm{REF}\frac{R_{F1}+R_{F2}}{R_{F2}}+I_C(\frac{R_{F1}}{R_{F2}}{R}_{F1}+R_C)---\left(5\right)$

In formula (5), Section 1 is without die terminals output voltage during line loss compensation, and Section 2 is compensate the voltage produced.

In control circuit, open power tube MH by clock edge, after power tube MH opens, the electric current of inductance L linearly rises, the voltage V that current detecting and slope compensation are formed jointly _rAMPraise gradually, voltage V _rAMPbe elevated to V _ctime, PWM comparator overturns, and its output signal makes power tube MH turn off, power tube ML conducting.V _rAMPvoltage expression be:

V _RAMP＝I _DC+I _SLOP1R ₁+I _SenseR ₁

(6)

＝I _DC+I _SLOP1R ₁+I _LR _SG _CSR ₁

Wherein, I _dCbe a fixing DC quantity, I _lrepresent inductive current, R _sfor current sense resistor, G _cSrepresent the mutual conductance of current sense amplifier.In the DC-DC of current-mode, in a switch periods, V _cvalue and V _rAMPpeak value substantially equal.Therefore, can think:

V _C＝V _RAMP

(7)

＝I _DC+I _SLOP1R ₁+I _LR _SG _CSR ₁

Fig. 3 shows a kind of specific embodiment circuit diagram of line loss compensation module of the present invention.As shown in Figure 3, voltage V _cin input line loss compensating module, the input signal of this line loss compensation module also has and above-mentioned I simultaneously _dCproportional DC quantity I _dC2, I _dC: I _dC2=n:1, with slope compensation current I _slopequal electric current I _slop2, these two for offsetting above-mentioned voltage V _cthe item that middle slope compensation current is relevant to direct current, makes the final offset current I exported _cwith inductive current I _lcompletely linear.

Resistance R1 in resistance R2 and Fig. 2 in Fig. 3 adopts the resistance of identical type, and its value relatable is R1:R2=1:n.In Fig. 3, power tube MN2 with the ratio of the breadth length ratio of power tube MN3 is: (W/L) ₂: (W/L) ₃the ratio of the breadth length ratio of=n:1, power tube MN4 and power tube MN5 is: (W/L) ₄: (W/L) ₅=1:m.Power tube MN3 and power tube MN4 forms current subtractor.Then the final offset current exported is:

$\begin{array}{c}{I}_C=(\frac{V_C}{R_2}-I_{\mathrm{DC}2}-\frac{I_{\mathrm{SLOP}2}}{n})*m\\ =(\frac{I_{\mathrm{DC}}+I_{\mathrm{SLOP}1}{R}_1+I_L{R}_S{G}_{\mathrm{CS}}{R}_1}{n{R}_1}-\frac{I_{\mathrm{DC}}}{n}-\frac{I_{\mathrm{SLOP}2}}{n})*m\\ =I_L{R}_S{G}_{\mathrm{CS}}*m\end{array}---\left(8\right)$

Visible, this offset current I _cwith inductive current I _llinear.Because inductive current is approximate suitable with load current, then offset current I _calso with load current I _loadlinear, as shown in Figure 4.

Convolution (5) and formula (8), compensating the voltage produced is:

$V_X=I_L{R}_S{G}_{\mathrm{CS}}*m*(\frac{R_{F1}}{R_{F2}}{R}_{F1}+R_C)---\left(9\right)$

Output V is kept if wish _oUTconstant, then above-mentioned bucking voltage V _xneed and resistance R _pon pressure drop I _o* R _pequal.

$V_X=I_L{R}_S{G}_{\mathrm{CS}}*m*(\frac{R_{F1}}{R_{F2}}{R}_{F1}+R_C)=I_O{R}_P---\left(9\right)$

Select larger inductance, the impact of inductive current ripple can be ignored, get approximate I _l=I _o.

Then can be obtained by formula (9):

$R_C=\frac{R_P}{{\mathrm{mI}}_L{R}_S{G}_{\mathrm{CS}}}-\frac{R_{F1}}{R_{F2}}{R}_{F1}---\left(10\right)$

According to the resistance R in different application _p, R _f1, R _f2, choose compensating resistance R according to formula (10) _c, then can full remuneration line loss resistance R _pon pressure drop, make output end voltage V _oUTall can keep constant under different loads electric current.

Existing dc-dc and the present invention with the die terminals of the dc-dc of compensate function and load end output voltage as shown in Figure 5.Wherein scheme the chip output voltage V that (a) is existing dc-dc _oUT1with load terminal voltage V _oUT; Figure (b) is for the present invention is with the chip output voltage V of the dc-dc of compensate function _oUT1with load terminal voltage V _oUT.Comparison diagram (a) is visible with figure (b), and the present invention can make load terminal voltage V _oUTkeep constant, eliminate the impact of line loss.

Above-described is only the preferred embodiment of the present invention, the invention is not restricted to above embodiment.Be appreciated that the oher improvements and changes that those skilled in the art directly derive without departing from the basic idea of the present invention or associate, all should think and be included within protection scope of the present invention.

Claims (3)

1. the dc-dc with line loss compensation, is characterized in that, comprises control circuit and filter circuit, feedback circuit, line loss compensation circuit; Input voltage produces die terminals output voltage after described control circuit and filter circuit, and described die terminals output voltage produces load end output voltage after line loss resistance, and described load end output voltage is that load end is powered; Described die terminals output voltage feeds back to control circuit through the feedback resistance of feedback circuit and the compensating resistance of line loss compensation circuit simultaneously; Described line loss compensation circuit obtains load current by the voltage of the error amplifier output in detection control circuit, and extract one with the proportional offset current of described load current from the feedback port of described compensating resistance, compensate to control circuit, the line loss pressure drop of load end output voltage is compensated.

2. the dc-dc according to claim 1 with line loss compensation, it is characterized in that, described line loss compensation circuit comprises operational amplifier, the input in the same way of operational amplifier connects the output end voltage of error amplifier, the reverse input end of operational amplifier is connected with the source electrode of the first NMOS tube, and the output of operational amplifier is connected with the grid of the first NMOS tube;

First PMOS is connected with the grid of the second PMOS, and the second NMOS tube is connected with the grid of the 3rd NMOS tube, and the 4th NMOS tube is connected with the grid of the 5th NMOS tube; The grid of the first PMOS is connected with drain electrode, and the grid of the second NMOS tube is connected with drain electrode, and the grid of the 4th NMOS tube is connected with drain electrode; The drain electrode of the first NMOS tube, the first PMOS is connected, and the drain electrode of the 3rd NMOS tube, the 4th NMOS tube, the second PMOS is connected;

The source electrode of the first PMOS, the second PMOS connects supply voltage; The source ground of the second NMOS tube, the 3rd NMOS tube, the 4th NMOS tube, the 5th NMOS tube; The source electrode of the first NMOS tube connects ground connection after the second resistance;

The drain electrode of the first NMOS tube connects direct current I _dC2; The drain electrode of the second NMOS tube connects direct current I _slop2; The feedback port of described compensating resistance is connected after drain electrode connection the 3rd resistance of the 5th NMOS tube.

3. the dc-dc according to claim 2 with line loss compensation, is characterized in that, described direct current I _slop2the slope compensation current I produced with described control circuit _slopequal; Described direct current I _dC2the fixing direct current I produced with described control circuit _dCratio be: I _dC: I _dC2=n:1; Slope compensation current I is connected in described second resistance and described control circuit _slopthe resistance type of the first drop-down resistance of output is identical, and the ratio of the resistance of the first resistance and the second resistance is: R1:R2=1:n; The ratio of the breadth length ratio of described second NMOS tube and the 3rd NMOS tube is: (W/L) ₂: (W/L) ₃=n:1; The ratio of the breadth length ratio of described 4th NMOS tube and the 5th NMOS tube is: (W/L) ₄: (W/L) ₅=1:m.