CN104217985A - Semiconductor device and fabrication method of shallow trench - Google Patents

Abstract

The application provides a semiconductor device and a shallow trench manufacturing method. The depth of the main part of the first trench of the semiconductor device is 50% to 95% of the depth of the first shallow trench isolation, and the angle between the first side wall and the second side wall of the first shallow trench isolation and their axis is α ; the end of the first sidewall extension at the bottom of the first groove away from the first sidewall intersects with the end of the second sidewall extension away from the second sidewall, and the first sidewall extension and the second sidewall extension are connected to The included angle between the axes of the first shallow trench isolation is β, wherein, 0°<α<β<90°; the depth of the main part of the second trench is 50-95% of the depth of the first shallow trench isolation , the angle between the third sidewall and the fourth sidewall of the second shallow trench isolation and its axis is γ; The angle between them is θ, where 0°<γ<θ<90°. The electrical performance of the first shallow trench isolation is improved.

Description

Semiconductor device and shallow trench fabrication method

technical field

The present application relates to the field of semiconductor device manufacturing, in particular, to a method for manufacturing a semiconductor device and a shallow trench.

Background technique

In the field of semiconductor device manufacturing, a device circuit generally includes a memory cell array region and a logic circuit region. The cells in the memory cell array area are isolated from each other by a shallow trench isolation (STI) structure; at the same time, in the logic circuit area, the semiconductor devices also need to be isolated by STI insulation to prevent leakage. Due to the different environments used, and the line width of the memory cell array area is smaller than that of the logic circuit area of the peripheral circuit, and the device density is higher, the width of the shallow trench isolation in the memory cell array area is also smaller than that of the logic circuit area. smaller and shallower in depth.

In the existing device manufacturing process, there are two basic manufacturing methods for shallow trench isolation of device circuits. One is to adopt the method of sub-area manufacturing, that is, to make shallow trench isolation in the memory cell array area and the shallow trench isolation in the logic circuit area respectively. This method has the following problems: when forming shallow trench isolation in sub-regions, it needs Two masks are used, and the mask patterns correspond to the memory cell array area and the logic circuit area respectively, so the cost of making the mask is relatively high, and two mask alignments are required, and the alignment accuracy of the formed shallow trench isolation is relatively low. Low.

Chinese patent application 200910194794.9 proposes a "dual-depth shallow trench isolation manufacturing method". Figures 1 to 8 show the schematic cross-sectional structure of the substrate after each step of the method is implemented. The method includes the following steps:

Step S1', providing a semiconductor substrate, the semiconductor substrate includes a substrate 100' and a dielectric layer 200' on the surface of the substrate, and the semiconductor substrate includes a first region I' and a second region II', the cross section of the obtained semiconductor substrate The structure is shown in Figure 1;

Step S2', forming a first mask layer 301' on the surface of the dielectric layer 200', and patterning the first mask layer 301', the cross-sectional structure of the obtained semiconductor substrate is shown in Figure 2;

Step S3', using the first mask layer 301' as a mask, etching the dielectric layer 200' and the substrate 100', forming the first trench 401' in the first region I' and the second region II', and obtaining The cross-sectional structure of the semiconductor substrate is as shown in Figure 3;

Step S4', removing the first mask layer 301', forming a second mask layer 302' on the surface of the first region I', and the cross-sectional structure of the obtained semiconductor substrate is shown in Figure 4;

Step S5', continue to etch the substrate 100' in the first trench 401' in the second region II' to form a second trench 402', and the cross-sectional structure of the obtained semiconductor substrate is shown in Figure 5;

In step S6', the second mask layer 302' is removed, and the cross-sectional structure of the obtained semiconductor substrate is shown in FIG. 6 .

In step S7', an insulating substance is filled in the first trench 401' and the second trench 402', and the surface of the device is planarized by chemical mechanical polishing (CMP). The cross-sectional structure of the obtained semiconductor substrate is shown in FIG. 7 .

In step S8', the dielectric layer 200' is removed, shallow trench isolation is formed on each region, and high-temperature annealing is performed for stabilization. The cross-sectional structure of the obtained semiconductor substrate is shown in FIG. 8 .

In the above method, it is still necessary to use the second mask 302' to protect the first groove 401' in the first region I', so as to avoid further etching process of the first groove 401' in the second region II'. Therefore, this method still needs to spend relatively high cost and complicated process to carry out separate processing on the shallow trench isolation of the memory cell array area and the shallow trench isolation of the logic circuit area, and, in this processing process, It is difficult to control the uniformity of the depth of shallow trenches in the same area.

Contents of the invention

The purpose of the present application is to provide a method for manufacturing a semiconductor device and a shallow trench, so that the depth of the shallow trenches in the same region is relatively consistent.

The semiconductor device provided by the present application includes a memory cell area and a logic circuit area, the memory cell area has a first shallow trench isolation, the logic circuit area has a second shallow trench isolation, and the first shallow trench isolation includes a first trench body part and the bottom of the first trench, the main part of the first trench includes a first side wall and a second side wall oppositely arranged, the depth of the main part of the first trench is 50% to 95% of the isolation depth of the first shallow trench, The angle between the first side wall and the second side wall and the axis of isolation of the first shallow trench is α; the bottom of the first trench includes a first side wall extension connected to the first side wall and a second side wall The second side wall extension part connected to the wall, the end of the first side wall extension part away from the first side wall intersects the end of the second side wall extension part far away from the second side wall, the first side wall extension part and the second side wall The included angle between the extension part and the axis of the first shallow trench isolation is β, wherein, 0°<α<β<90°; the second shallow trench isolation includes: a second trench body portion and a second trench At the bottom, the second trench main body part includes a third side wall and a fourth side wall oppositely arranged, the depth of the second trench main body part is 50-95% of the depth of the first shallow trench isolation, the third side wall and the fourth side wall The included angle between the fourth side wall and the axis isolated by the second shallow trench is γ; the bottom of the second trench includes a connecting wall, a third side wall extension connected to the third side wall and a third side wall connected to the fourth side wall The fourth side wall extension part, the end of the third side wall extension part away from the third side wall is connected with the end of the fourth side wall extension part far away from the fourth side wall through a connecting wall, the third side wall extension part and the fourth side wall An included angle between the wall extension and the axis of the second shallow trench isolation is θ, where 0°<γ<θ<90°.

The present application also provides a shallow trench fabrication method, the fabrication method comprising: dividing the substrate having a dielectric layer on the surface into a storage unit area and a logic circuit area; using the first etching gas to etch Forming the first trench body part and etching the logic circuit area to form the second trench body part, the first trench body part has a first side wall and a second side wall oppositely arranged, and the second trench body part has an opposite The third side wall and the fourth side wall are provided, the depth of the first groove body part and the second groove body part is 50-95% of the depth of the first shallow groove in the memory cell area, the first side wall and the second groove The included angle between the two sidewalls and the axis of the first groove main body is α, and the included angle between the third sidewall and the fourth sidewall and the axis of the second groove main body is γ; and using the second The etching gas is used to etch the bottoms of the first trench main body and the second trench main body to form corresponding first trench bottoms and second trench bottoms, wherein the first trench bottom includes the first sidewall and the first sidewall The first side wall extension part connected with the second side wall extension part connected with the second side wall, the end of the first side wall extension part far away from the first side wall and the end of the second side wall extension part far away from the second side wall intersection, the angle between the first side wall extension and the second side wall extension and the axis of the first groove main body is β, wherein, 0°<α<β<90°, the bottom of the second groove includes The connecting wall, the third side wall extension connected to the third side wall and the fourth side wall extension connected to the fourth side wall, the end of the third side wall extension away from the third side wall extends from the fourth side wall The end of the part far away from the fourth side wall is connected by a connecting wall, and the included angle between the extension part of the third side wall and the extension part of the fourth side wall and the axis of the main part of the second groove is θ where 0°<γ<θ <90°, the etching passivation ratio of the first etching gas is greater than the etching passivation ratio of the second etching gas.

Applying the technical solution of this application, in the process of forming shallow trenches by etching, the depth of shallow trenches directly depends on the opening size, because the etching rate is slower in small window patterns, even in small windows with high aspect ratios. Etching can stop on the size pattern, and the above phenomenon is called micro-loading effect; this application utilizes that the aspect ratio of the main part of the first trench is greater than that of the main part of the second trench, and controls the second trench under the action of the micro-loading effect. The shape of the bottom of the first groove makes it stop naturally after the etching angle gradually shrinks to a point during the etching process, and the bottom of the second groove can continue to be etched. A relatively consistent shape of the first groove can be obtained by using a simple etching method. The electrical performance of the first shallow trench isolation formed after filling the insulating material is improved.

Description of drawings

The accompanying drawings constituting a part of the present application are used to provide further understanding of the present application, and the schematic implementations and descriptions of the present application are used to explain the present application and do not constitute improper limitations to the present application. In the attached picture:

1 to 8 show schematic cross-sectional structure diagrams of semiconductor devices after implementing various steps of the prior art;

FIG. 9 shows a schematic cross-sectional structure diagram of a semiconductor device according to a preferred embodiment of the present application;

Fig. 10 shows an enlarged schematic view of the sidewall of the first shallow trench isolation in part A of the semiconductor device shown in Fig. 9, wherein the axes of the first sidewall and the second sidewall and the first shallow trench isolation and an angle β between the first sidewall extension and the second sidewall extension and the axis isolated from the first shallow trench;

11 shows an enlarged schematic view of the second shallow trench isolation sidewall in B in the semiconductor device shown in FIG. The included angle γ between, and the included angle θ between the axis of the third sidewall extension and the fourth sidewall extension and the isolation of the second shallow trench;

FIG. 12 shows a flow chart of a shallow trench fabrication method in a preferred embodiment provided by the present application;

FIG. 13 shows a schematic cross-sectional structure diagram of the semiconductor device after dividing the memory cell area and the logic circuit area;

FIG. 14 shows a schematic cross-sectional structure diagram of a semiconductor device after etching and forming a first trench body portion and a second trench body portion on the semiconductor device shown in FIG. 13 ;

FIG. 15 shows a schematic cross-sectional structure of the semiconductor device after the bottom of the first trench is formed by etching on the semiconductor device shown in FIG. 14; and

FIG. 16 shows a schematic cross-sectional structure diagram of the semiconductor device after the bottom of the second trench is formed by etching on the semiconductor device shown in FIG. 15 .

Detailed ways

It should be pointed out that the following detailed description is exemplary and intended to provide further explanation to the present application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

It should be noted that the terminology used here is only for describing specific implementations, and is not intended to limit the exemplary implementations according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should also be understood that when the terms "comprising" and/or "comprising" are used in this specification, it indicates There are features, steps, operations, means, components and/or combinations thereof.

For the convenience of description, spatially relative terms may be used here, such as "on ...", "over ...", "on the surface of ...", "above", etc., to describe the The spatial positional relationship between one device or feature shown and other devices or features. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, devices described as "above" or "above" other devices or configurations would then be oriented "beneath" or "above" the other devices or configurations. under other devices or configurations”. Thus, the exemplary term "above" can encompass both an orientation of "above" and "beneath". The device may be oriented in different ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Now, exemplary embodiments according to the present application will be described in more detail with reference to the accompanying drawings. These example embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of these exemplary embodiments to those of ordinary skill in the art. In the drawings, the layers are exaggerated for clarity and the thickness of the region, and the same reference numerals are used to designate the same devices, and thus their descriptions will be omitted.

As shown in FIG. 9 , in a preferred embodiment of the present application, a semiconductor device is provided, including a memory cell area and a logic circuit area, the memory cell area has a first shallow trench isolation, and the logic circuit area has a first shallow trench isolation. Two shallow trench isolations, the first shallow trench isolation includes a first trench main body and a first trench bottom, the first trench main body includes a first side wall and a second side wall oppositely arranged, the first trench The depth of the main body is 50-95% of the depth of the first shallow trench isolation. As shown in Figure 10, the angle between the first side wall and the second side wall and the axis of the first shallow trench isolation is α; A groove bottom includes a first side wall extension connected to the first side wall and a second side wall extension connected to the second side wall, the first side wall extension is far away from one end of the first side wall and the second side The end of the wall extension away from the second sidewall intersects. As shown in FIG. °<α<β<90°; the second shallow trench isolation includes: a second trench main body and a second trench bottom, the second trench main body includes a third side wall and a fourth side wall oppositely arranged, The depth of the main part of the second trench is 50% to 95% of the depth of the first shallow trench isolation. As shown in FIG. The angle is γ; the bottom of the second groove includes a connecting wall, a third side wall extension connected to the third side wall and a fourth side wall extension connected to the fourth side wall, the third side wall extension is far away from the third side wall One end of the side wall is connected to the end of the fourth side wall extension away from the fourth side wall through the connecting wall, as shown in FIG. The angle between them is θ, wherein, 0°<γ<θ<90°.

For semiconductor devices with the above structure, in the process of forming shallow trenches by etching, the depth of the shallow trenches directly depends on the size of the openings and the etching conditions used. When the etching conditions are determined, because the etching rate is within a small window Slower in the pattern, even on the small-sized pattern with high aspect ratio, the etching can stop, the above-mentioned phenomenon is called the micro-loading effect; the application utilizes that the aspect ratio of the first trench body part 111 is greater than that of the second trench body part The aspect ratio of 121 controls the shape of the first groove bottom 112 under the effect of micro-loading, so that the etching angle gradually shrinks to a point during the etching process and then stops naturally, while the second groove bottom 122 can continue to be etched. The first shallow trench 101 with a relatively uniform shape can be obtained by using a simple etching method, and then the first shallow trench 101 and the second shallow trench 102 are filled with insulating substances to form the first shallow trench isolation 1 and The second shallow trench isolation 2 improves the electrical performance of the first shallow trench isolation 1 .

The above-mentioned sidewalls of the first groove body part and the second groove body part refer to the two sidewalls perpendicular to the direction of the paper, and are not necessarily flat, with bends, grooves and/or protrusions Semiconductor devices with side walls are also within the protection scope of the present application.

The present application also provides a preferred implementation mode for manufacturing the above-mentioned semiconductor device. In this preferred implementation mode, the manufacturing method of the above-mentioned semiconductor device includes: dividing the substrate with a dielectric layer on the surface into a storage unit area and a logic circuit area; The first etching gas is used to etch to form the first trench main body in the memory cell area and to form the second trench main body in the logic circuit area. Two sidewalls, the second trench body part has a third sidewall and a fourth sidewall oppositely arranged, the depth of the first trench body part and the second trench body part is the first shallow trench depth of the memory cell area 50% to 95% of that; and use the second etching gas to etch the bottoms of the first trench main body and the second trench main body to form corresponding first trench bottoms and second trench bottoms, wherein the first A groove bottom includes a first side wall extension connected to the first side wall and a second side wall extension connected to the second side wall, the first side wall extension is far away from one end of the first side wall and the second side The end of the wall extension away from the second side wall intersects, the bottom of the second groove includes a connecting wall, a third side wall extension connected to the third side wall, and a fourth side wall extension connected to the fourth side wall, the second groove bottom One end of the three sidewall extensions away from the third sidewall is connected to an end of the fourth sidewall extension away from the fourth sidewall through a connecting wall, and the etching passivation ratio of the first etching gas is greater than that of the second etching gas. etch passivation ratio.

The etching passivation ratio in the above embodiment is the ratio between the etching rate and the passivation rate, and the etching process is the same as the conventional etching process. During the etching process, a dynamic balance is formed between the etching rate and the passivation rate, and the etched trench is determined by the position of the dynamic equilibrium point, such as at the midpoint of the etched trench or on the side close to the passivation layer The extension direction of the sidewall, such as adjusting the ratio of the etching rate to the passivation rate so that the dynamic equilibrium point is roughly at the midpoint of the etched trench, so as to ensure that the sidewall of the etched trench extends vertically downward or along with the etching The progression of depth has a slight inclination towards the axis.

FIG. 12 shows a flow chart of a shallow trench fabrication method in a preferred embodiment provided by the present application. 13 to 16 show schematic cross-sectional views of semiconductor devices in different steps of the shallow trench fabrication method provided by the present application. Wherein, as a preferred specific implementation, the semiconductor device includes a PMOS device and an NMOS device. The following will directly take this preferred specific implementation as an example to illustrate the specific steps of the preparation method provided by the present application. It should be noted that Figs. 13 to 16 are only schematic diagrams, the purpose of which is to concisely and clearly illustrate the inventive concepts proposed in this application.

FIG. 13 shows a schematic cross-sectional structure diagram of the semiconductor device including the substrate 100 and the dielectric layer 200 after dividing the memory cell region I and the logic circuit region II. Wherein, the substrate 100 may be a silicon substrate, and may also have doped regions, such as P-well and N-well regions.

FIG. 14 shows a schematic cross-sectional structure diagram of the semiconductor device after etching and forming the first trench body portion 111 and the second trench body portion 121 on the semiconductor device shown in FIG. 13 . At present, in order to meet different electrical performance requirements of different memory cell regions and logic circuit regions, the width and depth of the first shallow trenches located in the memory cell region are smaller than the width and depth of the second shallow trenches located in the logic circuit region. Corresponding to the size of the openings of the first shallow trench 101 and the second shallow trench 102 to be formed, use the first etching gas on the semiconductor substrate as shown in FIG. Etching out the first trench main body 111 of the first shallow trench 101 and etching the second trench main body 121 of the second shallow trench 102 in the logic circuit area II, wherein the first trench as shown in FIG. 11 The opening of the groove body part 111 is smaller than the opening of the second groove body part 121, and the angle α between the first side wall and the second side wall and the axis of the first shallow groove 101 is between 0° and 10°, The angle γ between the third sidewall and the fourth sidewall and the axis of the second shallow trench 102 is between 0° and 10°, which ensures that the first shallow trench 101 and the second shallow trench 102 are sufficiently depth.

FIG. 15 shows a schematic cross-sectional structure diagram of the semiconductor device after the bottom of the first trench is formed by etching on the semiconductor device shown in FIG. 14 . The second etching gas with an etching passivation ratio greater than that of the first etching gas is used to etch along the sidewalls of the first trench body part 111 and the second trench body part 121 in FIG. The first sidewall extension and the second sidewall extension of a trench bottom 112 and the third sidewall extension and fourth sidewall extension of the second trench bottom 122 extend toward the corresponding shallow trench along the etching direction. The axes of the grooves are gathered. In the above process, by increasing the etching passivation ratio, the dynamic equilibrium position is further approached to the side of the passivation layer, so that the side walls of the first trench bottom 112 and the side walls of the second trench bottom 122 The sidewall shrinks toward the corresponding axis at a larger inclination angle, because the aspect ratio of the first shallow trench 101 is large, and the sidewall of the bottom 112 of the first trench is under the action of the micro-loading effect in the etching process. After the predetermined positions are collected, the etching is naturally stopped, and the cross-sectional structure of the obtained semiconductor device is shown in Figure 15, the angle β between the first sidewall extension and the second sidewall extension and the axis of the first shallow trench 101 Between 10° and 60°, the included angle θ between the third sidewall extension and the fourth sidewall extension and the axis of the second shallow trench 102 is between 10° and 60°, avoiding the first The excessively sharp corners in the shallow trench 101 and the second shallow trench 102 cause electric leakage.

FIG. 16 shows a schematic cross-sectional structure diagram of the semiconductor device after the bottom of the second trench is formed by etching on the semiconductor device shown in FIG. 15 . After the etching of the first shallow trench 101 is completed, the etching of the first shallow trench 101 stops naturally due to the micro-loading effect, so when the second trench bottom 122 shown in FIG. 15 is continuously etched, Even without the protective effect of the mask layer, no further etching will be formed on the bottom of the first trench 112, so the bottom of the second trench 122 is continuously etched to a predetermined position to obtain the second shallow trench 102, and the obtained semiconductor The cross section of the substrate is shown in FIG. 16 , the depth of the second shallow trench 102 is greater than the depth of the first shallow trench 101 .

When performing the above etching, in order to facilitate the control of the etching process of the first shallow trench 101 and the second shallow trench 102, it is preferable that the corresponding positions of the first trench main body part 111 and the second trench main part 121 The side walls are parallel, that is, α and γ are basically the same, and the side walls at corresponding positions of the first trench bottom 112 and the second trench bottom 122 are parallel, that is, β and θ are basically the same. In order to avoid unnecessary loss of line width in the above-mentioned embodiment, it is preferable to use anisotropic etching for the above-mentioned etching, because anisotropic etching performs etching at different rates in various directions, making the etching along the depth direction to form a shallow trench with an ideal anisotropic etch profile.

The dynamic equilibrium position of etching the first trench main body 111 and the second trench main body 121 and the dynamic equilibrium position of etching the first trench bottom 112 and the second trench bottom 122 are changed by adjusting the first etching gas Compared with the etch passivation ratio of the second etching gas, the angles between the obtained sidewalls of the first trench body part 111 and the sidewalls of the second trench body part 121 and the corresponding axes are between 0°～ 10°, so that the angles between the obtained side walls of the first groove bottom 112 and the side walls of the second groove bottom 122 and the corresponding axes are between 10° and 60°. Under the above conditions, it is guaranteed The depth and width of the first shallow trench 101 and the second shallow trench 102 are ensured, and electric leakage phenomenon caused by too sharp corners in the first shallow trench 101 and the second shallow trench 102 is avoided.

The etching passivation ratio of the etching gas is adjusted by the ratio of the main etching gas and the passivation gas in the etching gas. Preferably, the first etching gas includes the first main etching gas with a volume ratio of 50:1 to 200:1. The etching gas and the first passivation gas, the second etching gas includes the second main etching gas and the second passivation gas with a volume ratio of 10:1˜100:1. The etching passivation ratio of the first etching gas is greater than the etching passivation ratio of the second etching gas, thereby further ensuring that 0°<α<β<90°, 0°<γ<θ<90° and α between 0° and 10°, γ between 0° and 10°, β between 10° and 60°, and θ between 10° and 60°.

When implementing the above embodiments, the main etching gas and passivation gas commonly used in this field can be selected as the main components of the above-mentioned first etching gas and the above-mentioned second etching gas. From one or more of Cl ₂ , SF ₆ , CF ₄ , the first passivation gas is selected from one or more of HBr, C ₄ F ₈ , CH ₂ F ₂ , CH ₃ F, C ₅ F ₈ The second etching gas includes a second main etching gas and a second passivation gas, the second main etching gas is selected from one or more of Cl ₂ , SF ₆ , CF ₄ , and the second passivation gas One or more selected from HBr, C ₄ F ₈ , CH ₂ F ₂ , CH ₃ F, and C ₅ F ₈ . The above-mentioned etching gases are generally commonly used etching gases. Those skilled in the art select the appropriate composition and ratio of the main etching gas and passivation gas in combination with the properties of various main etching gases and passivation gases to achieve the predetermined The etch passivation ratio, and then can obtain the predetermined first shallow trench 101 and the second shallow trench 102, for example, when using the mixed gas of HBr and _Cl2 as the etching gas, more HBr can be formed so that the etched Etched shallow trenches have sidewall slopes that are more angled, and less HBr creates more vertical angles. Also, the same effect as more HBr gas can be obtained when additional CxHyFz gas is added.

Taking a typical flash memory with a silicon substrate in this field as an example, with the silicon substrate as the substrate of the flash memory, the first etching gas includes Cl _and HBr with a volume ratio of 100:1, and the second etching gas includes _Cl2 and HBr in a volume ratio of 20:1. In order to ensure the performance of flash memory, the size of the shallow trenches needs to be precisely controlled, so the first etching gas of Cl ₂ and HBr with a volume ratio of 100:1 is used to control the etching passivation ratio at 1.3-1.5:1 In between, the second etching gas of Cl ₂ and HBr with a volume ratio of 20:1 is used to control the etching passivation ratio between 0.65-0.85:1, so that the first trench body part 111 and the second trench The sidewall of the main body portion 121 extends toward the substrate in a vertical direction as far as possible, while the sidewalls of the first trench bottom 112 and the second trench bottom 122 are inclined at an angle of 30° to 60°, so that the first shallow trench 101 has a sufficient depth, and etching stops naturally at a predetermined depth position.

When etching the shallow trenches of the above-mentioned flash memory with a silicon substrate, it is preferred to use the first etching gas for etching, the excitation power is 20-1500W, the bias voltage is 10-800V, and the pressure of the first etching gas 2-200mT, the total flow rate is 30-2000sccm; when the second etching gas is used for etching, the excitation power is 20-1500W, the bias voltage is 10-800V, the pressure of the second etching gas is 2-200mT, the total The flow rate is 30-2000 sccm. Alternatively, the steps of etching/passivating the silicon substrate are alternately performed using the Bosch process technology in the prior art to complete the etching of the shallow trench.

In a preferred embodiment of the present application, step S2 selects _Cl2 and HBr with a volume ratio of 100:1 as the first etching gas, the excitation power of etching is 1000W, the bias voltage is 600V, and the etching gas The pressure is 20mT, the total flow rate is 500sccm; in step S3 _, Cl2 and HBr with a volume ratio of 20:1 are selected as the second etching gas, the excitation power of etching is 1000W, the bias voltage is 600V, and the etching gas The pressure is 20mT, the total flow rate is 500sccm, and the structure of the first shallow groove and the second shallow groove is shown in Figure 16, wherein the angle between the side wall of the main body of the first groove and the axis is 5°, and the first groove The angle between the side wall of the bottom and the axis is 50°; the angle between the side wall of the main body of the second groove and the axis is 5°, and the angle between the side wall of the bottom of the second groove and the axis is 45°.

In another preferred embodiment of the present application, in order to insulate the gate and source of the semiconductor device, preferably the dielectric layer of the semiconductor device includes a gate dielectric layer and a floating gate layer, as shown in Figures 13 to 16 As shown, the process of preparing the dielectric layer includes: disposing a gate dielectric layer above the substrate; disposing a floating gate layer above the gate dielectric layer. The gate dielectric layer 201 provided on the upper surface of the substrate 100 provides a buffer for the subsequently formed floating gate layer 202, and avoids dislocations on the substrate surface due to high stress when the floating gate layer 202 is directly provided on the substrate 100. In view of the shortcomings of faults, the gate dielectric layer 201 can be formed by thermal oxidation or deposition, and the floating gate layer 202 can be formed by a deposition process.

Since the electrical properties of the memory cell region I and the logic circuit region II are different, the thickness of the gate dielectric layer 201 of the logic circuit region II is preferably greater than the thickness of the gate dielectric layer 201 of the memory cell region I. In logic circuit area II, there are usually circuits with relatively high driving voltage, which require deeper shallow trenches to isolate their active areas. When the thickness of the gate dielectric layer 201 in logic circuit area II is greater than that The thickness of the dielectric layer 201 can better realize the isolation effect on the active region.

The gate dielectric layer 201 of the present application can be selected from silicon dioxide, silicon nitride, high-K dielectric material or other suitable materials; the high-K dielectric material can be LaO, AlO, ZrO, TiO, Ta ₂ O ₅ , Y ₂ O ₃ , SrTiO ₃ , BaTiO ₃ , BaZrO, Hf ₃ ZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, Al ₂ O ₃ , Si ₃ N ₄ and other suitable materials. The method for forming the gate dielectric layer includes atomic layer deposition, chemical vapor deposition, physical vapor deposition, thermal oxidation, UV-ozone oxidation (UV-ozoneoxidation) or a combination of the above methods.

The material of the floating gate layer 202 of the present application may be metal, metal alloy, metal nitride or metal silicide, polysilicon, and other suitable materials. The method of forming the gate electrode includes conventional methods such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, or a combination of the above methods. The above methods have been known to those skilled in the art, and their common use or deformation are within the protection scope of the present application. I won't repeat them here.

In a preferred embodiment of the present application, the above-mentioned dielectric layer further includes an etch barrier layer and a mask layer, the etch barrier layer is located on the upper surface of the floating gate layer; the mask layer is located on the upper surface of the etch barrier layer, As shown in Figures 13 to 16. During the etching process, the mask layer 204, the etch stop layer 203, the floating gate layer 202, the gate dielectric layer 201 and the substrate 100 are sequentially etched to form the first trench main body portion 111 and the second trench main body portion 121 , the etching of each layer can be selected according to the corresponding etching process according to its material; the etching barrier layer 203 can protect the floating gate layer 202 from being damaged during the etching process, which affects the flatness of its surface, and ensures excellent subsequent formation performance semiconductor devices.

In order to strengthen the blocking effect of the etching stopper layer 203 and facilitate the formation of accurate shallow trench openings, it is preferred that the etching stopper layer 203 is a silicon nitride layer or a silicon oxide layer or formed by stacking a silicon oxide layer and a silicon nitride layer up and down. In the double-layer structure, the mask layer 204 is a photoresist layer. The photoresist layer is exposed and developed by using a mask corresponding to the position of the shallow trench to form a photoresist pattern and then etched.

FIG. 9 shows a schematic cross-sectional structure diagram of the semiconductor device after the first shallow trench and the second shallow trench of the semiconductor device shown in FIG. 16 are filled with an insulating substance. After removing the dielectric layer 200, fill the first shallow trench 101 and the second shallow trench 102 with an insulating substance to form the first shallow trench isolation 1 and the second shallow trench isolation 2, and use chemical mechanical polishing CMP to clean the surface of the semiconductor device Planarization and high temperature annealing are robust. It can be removed by selective wet etching layer by layer. For example, hydrofluoric acid can etch silicon oxide, and hot phosphoric acid can etch and remove silicon nitride. If the mask layer 204 is a hard mask layer, it can also be removed by combining chemical mechanical polishing and CMP. The insulating material filled in the first shallow trench 101 and the second shallow trench 102 is preferably silicon oxide. The inner surface of the second shallow trench 102 is deposited by chemical vapor deposition or a silicon oxide liner layer is formed on the inner surface of the trench by high temperature thermal oxidation.

In the process of forming the shallow trench by etching, the present application utilizes the large aspect ratio of the main body of the first trench to control the shape of the bottom of the first trench under the action of the micro-loading effect, so that it can be etched During the etching process, the etching angle gradually shrinks to a point and then stops naturally, while the bottom of the second trench can continue to be etched; and by adjusting the etching passivation ratio of the etching gas, the first shallow trench and the second shallow trench The control of the inclination angle of the side wall of the groove makes the whole etching process simple and easy to control, and the shape of the obtained first shallow trench is relatively consistent, so that the electrical performance of the first shallow trench isolation formed after filling the insulating material is improved.

The above are only preferred embodiments of the present application, and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this application shall be included within the protection scope of this application.

Claims (11)

1. A semiconductor device, comprising a memory cell area and a logic circuit area, the memory cell area has a first shallow trench isolation, and the logic circuit area has a second shallow trench isolation, characterized in that, The first shallow trench isolation includes: The first trench body part includes a first side wall and a second side wall oppositely arranged, the depth of the first trench body part is 50-95% of the first shallow trench isolation depth, and the first trench body part has a depth of 50% to 95% of the isolation depth of the first shallow trench. The included angle between one side wall and the axis separating the second side wall from the first shallow trench is α; The bottom of the first trench includes a first side wall extension connected to the first side wall and a second side wall extension connected to the second side wall, the first side wall extension is far away from the One end of the first side wall intersects with an end of the second side wall extension away from the second side wall, the first side wall extension and the second side wall extension intersect with the first shallow groove The angle between the axes separated by the slots is β, where 0°<α<β<90°; The second shallow trench isolation includes: The second trench body part includes a third side wall and a fourth side wall oppositely arranged, the depth of the second trench body part is 50-95% of the depth of the first shallow trench isolation, the said The included angle between the third sidewall and the axis isolated from the fourth sidewall and the second shallow trench is γ; The bottom of the second groove includes a connecting wall, a third side wall extension connected to the third side wall, and a fourth side wall extension connected to the fourth side wall, the third side wall extension An end away from the third side wall is connected to an end of the fourth side wall extension away from the fourth side wall through the connecting wall, and the third side wall extension and the fourth side wall extend The included angle between the portion and the axis of the second shallow trench isolation is θ, where 0°<γ<θ<90°. 2 . The semiconductor device according to claim 1 , wherein the α is between 0° and 10°, and the γ is between 0° and 10°. 3. The semiconductor device according to claim 1, wherein the β is between 10° and 60°, and the θ is between 10° and 60°. 4. A manufacturing method of a shallow trench, characterized in that the manufacturing method comprises: Dividing the substrate with a dielectric layer on the surface into a memory cell area and a logic circuit area; Using the first etching gas, etch to form a first trench main body in the memory cell area and etch to form a second trench main body in the logic circuit area, the first trench main body has an opposite arrangement The first side wall and the second side wall, the second groove body part has a third side wall and a fourth side wall oppositely arranged, the first groove body part and the second groove body part The depth is 50% to 95% of the depth of the first shallow trench in the memory cell area, and the included angle between the first side wall and the second side wall and the axis of the first trench main body is α, and the included angle between the third sidewall and the fourth sidewall and the axis of the second groove main body is γ; and Using a second etching gas, etching the bottoms of the first trench main body and the second trench main body to form corresponding first trench bottoms and second trench bottoms, wherein, The bottom of the first groove includes a first side wall extension connected to the first side wall and a second side wall extension connected to the second side wall, the first side wall extension is far away from the One end of the first side wall intersects with an end of the second side wall extension away from the second side wall, and the first side wall extension and the second side wall extension intersect with the first groove The included angle between the axes of the groove main body is β, wherein, 0°<α<β<90°, The bottom of the second groove includes a connecting wall, a third side wall extension connected to the third side wall, and a fourth side wall extension connected to the fourth side wall, and the third side wall extends One end of the part away from the third side wall is connected with an end of the fourth side wall extension away from the fourth side wall through the connecting wall, and the third side wall extension and the fourth side wall The angle between the extension part and the axis of the second groove body part is θ where 0°<γ<θ<90°, An etching passivation ratio of the first etching gas is greater than an etching passivation ratio of the second etching gas. 5. The manufacturing method according to claim 4, wherein the etching is anisotropic etching. 6. The manufacturing method according to claim 4, wherein the first etching gas comprises a first main etching gas and a first passivation gas with a volume ratio of 50:1 to 200:1, and the The second etching gas includes a second main etching gas and a second passivation gas in a volume ratio of 10:1˜100:1. 7. The preparation method according to claim 6, characterized in that, The first main etching gas is selected from one or more of Cl ₂ , SF ₆ , CF ₄ , and the first passivation gas is selected from HBr, C ₄ F ₈ , CH ₂ F ₂ , CH ₃ F , one or more of C ₅ F ₈ ; The second main etching gas is selected from one or more of Cl ₂ , SF ₆ , CF ₄ , and the second passivation gas is selected from HBr, C ₄ F ₈ , CH ₂ F ₂ , CH ₃ F , one or more of C ₅ F ₈ . 8. The manufacturing method according to claim 7, wherein the substrate is a silicon substrate, the first etching gas comprises Cl _and HBr with a volume ratio of 100:1, and the second etching gas comprises volume _Cl2 and HBr in a ratio of 20:1. 9. The preparation method according to claim 8, characterized in that, in the preparation method, When using the first etching gas for etching, the excitation power is 20-1500W, the bias voltage is 10-800V, the pressure of the first etching gas is 2-200mT, and the total flow rate is 30-2000sccm; When the second etching gas is used for etching, the excitation power is 20-1500 W, the bias voltage is 10-800 V, the pressure of the second etching gas is 2-200 mT, and the total flow rate is 30-2000 sccm. 10. The manufacturing method according to claim 4, wherein the dielectric layer comprises a gate dielectric layer and a floating gate layer, and the manufacturing method further comprises a process of preparing the dielectric layer, the process comprising: disposing a gate dielectric layer over the substrate; A floating gate layer is disposed above the gate dielectric layer. 11. The manufacturing method according to claim 10, wherein the thickness of the gate dielectric layer in the logic circuit region is greater than the thickness of the gate dielectric layer in the memory cell region.