CA1182930A - Field effect transistor with a high cut-off frequency - Google Patents
Field effect transistor with a high cut-off frequencyInfo
- Publication number
- CA1182930A CA1182930A CA000387748A CA387748A CA1182930A CA 1182930 A CA1182930 A CA 1182930A CA 000387748 A CA000387748 A CA 000387748A CA 387748 A CA387748 A CA 387748A CA 1182930 A CA1182930 A CA 1182930A
- Authority
- CA
- Canada
- Prior art keywords
- layer
- semiconductor
- field effect
- effect transistor
- semi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/82—Heterojunctions
- H10D62/824—Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
- H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
- H10D30/473—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT
- H10D30/4732—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT using Group III-V semiconductor material
- H10D30/4738—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT using Group III-V semiconductor material having multiple donor layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
- H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
- H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
- H10D30/4755—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/149—Source or drain regions of field-effect devices
Landscapes
- Junction Field-Effect Transistors (AREA)
- Bipolar Transistors (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
The invention relates to ultra-high frequency transistors on semiconductors of the III-V compound group. In order to increase the cut-off frequency of Schottky gate transistors, the invention uses for the active part of the channel a first layer of a semi-conductor of a first group and a second layer of a semi-conductor of a second group, the latter having the same crystalline mesh parameter and a wider forbidden band than the semiconductor of the first group. Application to devices and systems operating at ultra-high frequencies.
The invention relates to ultra-high frequency transistors on semiconductors of the III-V compound group. In order to increase the cut-off frequency of Schottky gate transistors, the invention uses for the active part of the channel a first layer of a semi-conductor of a first group and a second layer of a semi-conductor of a second group, the latter having the same crystalline mesh parameter and a wider forbidden band than the semiconductor of the first group. Application to devices and systems operating at ultra-high frequencies.
Description
_eld effect tra~ i.stor with~a hi~h cut off frequency B~KG~OUND OF THE INVENTION
_ _ ____ _ ~ _ _ _ _ __ .___ __ _ _ _ _ _ .
The present invention relates to field effect transistors and more particularly to those with a high cut-off frequency.
Field effect transistors in the group of III-V semiconductors are known which comprise on the one hand access regions called the source and drain and on the other hand a control region constituted by an active layer of weakly doped GaAs and juxtaposed with a layer of AlxGal xAs and supported in each case by a semi-insulating substrate. It is a characteristic of all these transistors that they have a high electrical accumulation in the GaAs layer due to the existence of the heterojunction and a high electron mobility on the transistor channel between the source and drain due to the weak doping of the active GaAs layer. Thus, these transistors have ahi~h cut-off frequenc~. In French patent no. ~ L165 317, ~ranted J~l~y 21 19~3 and Canadian patent 1 15~ 366 is~ued ~eo~m~er 6, lq83 to the pres~nt Applicant Company an insulatin~ la~er is inserted betwcen tlle ~ate contact metal and the AlxGal xAs layer. In French Patent2 465 31~ granted July 11, 19~3 to the ~pplicant Company, the Schottky gate contact is deposited on a G~As layer, the AlxGal xAs layer being positioned between the semi-insulating substrate and the active GaAs layer.
These transistors only apply to active GaAs layers. In the group of III-V semiconductor compounds there are materials having a higher mobility than ~ ?~ ~
GaAs, e.g. InAs) InSb or thelr alloys of the type Ga In As or InAs Sb . At ambient temperature, x l-x x l-~c these weakly doped materials respectively have a mobility of 20,000~ 80,000, 159000 and 50,000 cm2v ls 1.
The two latter values correspond to cornpositions such that x~ 0.5 0 For comparison purposes, weakly doped GaAs has a mobility of 8,000 cm~v s . It is therefore of interest to use these materials as the active part of the channel of a field effect transistor.
10GaxInl xA~ ield effect transistor~ have already been described in the literature. These are MESFET (Metal Schottky f~eld effect translstors) or JFET (junction field effect transistors~ ln whlch the active layer is doped to approximately 1017atoms/cm3 and ln which the electron mobili~y ~s approximately 10,000 cm2v ls 1~ To attain a mobillty of 15,000cm2v it ~s necessary ~o use weakly doped GaxInl As in accordance with the heterojunctions described in Canadian- -Patent Application 363 129 filed 23 October 1980 of the 20 ~pplicant company.
However3 these known semlconductors have forbidden bands of a limited width. However, in the case of those uslng InAs~ InSb and the alloy InAsl XSb~, the forbidden bands are so narrow (0.23 to 0.41 eV~ that it is not possible to work at ambient temperature. The advantage of the high moblllty compared with GaAs no ronger applies at low temperature ~77K~. From this standpoint, InAs9 InSb and InAsl XSbX are o no interest, but GaxInl As is still of interest. Furthermore, Schottky gates ~ 3~.~
deposited on these materials have high leakage currents, so that the use thereof is impossible in accordance with one of the structures described in French Patent 2 465 318.
BRIEF SUMMARY OF THE INVENTION
The object of the present invention is to obviate these disadvantages by using a special construction of the field effect transistor channel which comprises, besides the Schottky ~ate~ a hetero-junction formed between a first semiconductor materialsuch as GaxInl As and a second semiconductor material from the group of III-V compounds having the same crystalline mesh parameter as Ga Inl_ Asl but with a wider Eorbidden band. Thus, the pair of materials forms a N-N heterojunction and has an electron accumulation layer in the GaxInl xAs.
More specifically, the present invention relates to a field effect transistor with a high cut-off frequency which comprises, supported by a semi-insulating substrate, two access regions called the source and the drain and a control regioll con-stituted by a first active layer, a second layer and a metal Schottky gate, the second layer being positioned between the first layer and the metal gate, wherein the first layer which is made from a semi-conductor material of a first group and the second layer made from a semiconductor material of a second group form an isotype N-N heterojunction in which the semiconductor material of the second group has the same crystalline mesh parameter and a wider forbidden ~ 3 balld ~h~n Lhc sclllicc)nduc~or ma~cria] of ~ firs~
~roup and wh~rein the firs~ layc~r is dol)~d Lo a level eq~al to or below 101 atorrls/cm3 alld the second layer to a level equal to or above 1017/cm3.
BRIE.F DLSCRIPTlO~ OF THE DRAW]~GS
The invention is described in greater detail her~inafter relative Lo non-limitative e~bodiments and wi~h reference to the attached drawings, wherein show: 0 Fig 1 the b~nd diagram at equilibrium of a hetero-junction comprising a semiconductor with a small orbidden band, a semiconduc~or with a large forbidden band and a metal.
Fig 2 the band diagram of the heterostl~cture under negative polari7.ation of the metal side.
Fig 3 a diagran~natic section of a first embodiment of the transistor according to the invention.
Fig 4 a diagramrnatic section of a second embodiment of the transistor accordîng to the invention. 0 Fig 5 a diagrammatic section of a third ernbodiment of the transistor according to the invention.
Fig 6 a diagramrnatic section of a fourth embodiment of the transistor according to the ;nvention.
DETAILED DESCRIPTION OF THE PREFERRED F~lBODrMENTS
Fig 1 shows a heterostructure comprising on the one hand an isotype heterojunction ormed by a irst N type semiconductor 1 and a second N type semiconductor 2 having a wider forbidden band than ?3~
the first semiconductor 1, but the same mesh parameter as the latter9 and on the other hand a Schottky contact formed between a metal and the second semiconductor 2. In Fig 1, the system is at equilibrium, i.e. the Fermi levels EF are aligned.
Ec and Ev respectively represent the energy levels of the conduction band and the valence band as ~ Ec represents the discontinuity in the conduction band. As has been described in French Paten~ 2 452 791,
_ _ ____ _ ~ _ _ _ _ __ .___ __ _ _ _ _ _ .
The present invention relates to field effect transistors and more particularly to those with a high cut-off frequency.
Field effect transistors in the group of III-V semiconductors are known which comprise on the one hand access regions called the source and drain and on the other hand a control region constituted by an active layer of weakly doped GaAs and juxtaposed with a layer of AlxGal xAs and supported in each case by a semi-insulating substrate. It is a characteristic of all these transistors that they have a high electrical accumulation in the GaAs layer due to the existence of the heterojunction and a high electron mobility on the transistor channel between the source and drain due to the weak doping of the active GaAs layer. Thus, these transistors have ahi~h cut-off frequenc~. In French patent no. ~ L165 317, ~ranted J~l~y 21 19~3 and Canadian patent 1 15~ 366 is~ued ~eo~m~er 6, lq83 to the pres~nt Applicant Company an insulatin~ la~er is inserted betwcen tlle ~ate contact metal and the AlxGal xAs layer. In French Patent2 465 31~ granted July 11, 19~3 to the ~pplicant Company, the Schottky gate contact is deposited on a G~As layer, the AlxGal xAs layer being positioned between the semi-insulating substrate and the active GaAs layer.
These transistors only apply to active GaAs layers. In the group of III-V semiconductor compounds there are materials having a higher mobility than ~ ?~ ~
GaAs, e.g. InAs) InSb or thelr alloys of the type Ga In As or InAs Sb . At ambient temperature, x l-x x l-~c these weakly doped materials respectively have a mobility of 20,000~ 80,000, 159000 and 50,000 cm2v ls 1.
The two latter values correspond to cornpositions such that x~ 0.5 0 For comparison purposes, weakly doped GaAs has a mobility of 8,000 cm~v s . It is therefore of interest to use these materials as the active part of the channel of a field effect transistor.
10GaxInl xA~ ield effect transistor~ have already been described in the literature. These are MESFET (Metal Schottky f~eld effect translstors) or JFET (junction field effect transistors~ ln whlch the active layer is doped to approximately 1017atoms/cm3 and ln which the electron mobili~y ~s approximately 10,000 cm2v ls 1~ To attain a mobillty of 15,000cm2v it ~s necessary ~o use weakly doped GaxInl As in accordance with the heterojunctions described in Canadian- -Patent Application 363 129 filed 23 October 1980 of the 20 ~pplicant company.
However3 these known semlconductors have forbidden bands of a limited width. However, in the case of those uslng InAs~ InSb and the alloy InAsl XSb~, the forbidden bands are so narrow (0.23 to 0.41 eV~ that it is not possible to work at ambient temperature. The advantage of the high moblllty compared with GaAs no ronger applies at low temperature ~77K~. From this standpoint, InAs9 InSb and InAsl XSbX are o no interest, but GaxInl As is still of interest. Furthermore, Schottky gates ~ 3~.~
deposited on these materials have high leakage currents, so that the use thereof is impossible in accordance with one of the structures described in French Patent 2 465 318.
BRIEF SUMMARY OF THE INVENTION
The object of the present invention is to obviate these disadvantages by using a special construction of the field effect transistor channel which comprises, besides the Schottky ~ate~ a hetero-junction formed between a first semiconductor materialsuch as GaxInl As and a second semiconductor material from the group of III-V compounds having the same crystalline mesh parameter as Ga Inl_ Asl but with a wider Eorbidden band. Thus, the pair of materials forms a N-N heterojunction and has an electron accumulation layer in the GaxInl xAs.
More specifically, the present invention relates to a field effect transistor with a high cut-off frequency which comprises, supported by a semi-insulating substrate, two access regions called the source and the drain and a control regioll con-stituted by a first active layer, a second layer and a metal Schottky gate, the second layer being positioned between the first layer and the metal gate, wherein the first layer which is made from a semi-conductor material of a first group and the second layer made from a semiconductor material of a second group form an isotype N-N heterojunction in which the semiconductor material of the second group has the same crystalline mesh parameter and a wider forbidden ~ 3 balld ~h~n Lhc sclllicc)nduc~or ma~cria] of ~ firs~
~roup and wh~rein the firs~ layc~r is dol)~d Lo a level eq~al to or below 101 atorrls/cm3 alld the second layer to a level equal to or above 1017/cm3.
BRIE.F DLSCRIPTlO~ OF THE DRAW]~GS
The invention is described in greater detail her~inafter relative Lo non-limitative e~bodiments and wi~h reference to the attached drawings, wherein show: 0 Fig 1 the b~nd diagram at equilibrium of a hetero-junction comprising a semiconductor with a small orbidden band, a semiconduc~or with a large forbidden band and a metal.
Fig 2 the band diagram of the heterostl~cture under negative polari7.ation of the metal side.
Fig 3 a diagran~natic section of a first embodiment of the transistor according to the invention.
Fig 4 a diagramrnatic section of a second embodiment of the transistor accordîng to the invention. 0 Fig 5 a diagrammatic section of a third ernbodiment of the transistor according to the invention.
Fig 6 a diagramrnatic section of a fourth embodiment of the transistor according to the ;nvention.
DETAILED DESCRIPTION OF THE PREFERRED F~lBODrMENTS
Fig 1 shows a heterostructure comprising on the one hand an isotype heterojunction ormed by a irst N type semiconductor 1 and a second N type semiconductor 2 having a wider forbidden band than ?3~
the first semiconductor 1, but the same mesh parameter as the latter9 and on the other hand a Schottky contact formed between a metal and the second semiconductor 2. In Fig 1, the system is at equilibrium, i.e. the Fermi levels EF are aligned.
Ec and Ev respectively represent the energy levels of the conduction band and the valence band as ~ Ec represents the discontinuity in the conduction band. As has been described in French Paten~ 2 452 791,
2 465 317 and 2 465 318 of the Applicant Company at the heterojunction interface there is an electron accumulation zone on the side of semi-conductor 1 with the small forbidden band and an electron-free layer 4 on the side ~ the semiconductor 2 with the large forbidden band. As semiconductor 1 is weakly doped, the mobility of the electrons in zone 3 is high. There is an electron-free zone 5 at the interface between the metal and semiconductor 2.
In Fig 2, a negative voltage V is applied to the metal ;n the system. To obtain a sufficiently high voltage V in absolute values, the space charge region 5 is extended up to the heterojunction interface, thus destroying the accumulation layer 3 and enabling an electron-free zone 6 to appear.
In the specific case where semiconductor 2 is of GaxInl xAs, its compositior, mlst be such that its mesh parameter is adapted to a known substrate so as to obtain a high quality epitaxial layer.
GaAs or InAs substrates are obviously excepted 0 because their mesh parameter differs from that of
In Fig 2, a negative voltage V is applied to the metal ;n the system. To obtain a sufficiently high voltage V in absolute values, the space charge region 5 is extended up to the heterojunction interface, thus destroying the accumulation layer 3 and enabling an electron-free zone 6 to appear.
In the specific case where semiconductor 2 is of GaxInl xAs, its compositior, mlst be such that its mesh parameter is adapted to a known substrate so as to obtain a high quality epitaxial layer.
GaAs or InAs substrates are obviously excepted 0 because their mesh parameter differs from that of
3 ~
GaxInl xAs. For x ~ 0.5, the alloy GaxInl_ As is adapted with respect to the mesh parameter to InP.
For x ~ 0.5, the alloy GaxInl As has a forbidden band of approximately 0.75 eV. Thus, the semiconductor 2 with a wider forhidden band than GaxInl As can be InP (forbidden band 1.36 eV), Al Inl As (x ~ 0.5) (forbidden band 1.46 eV), GaAsySbl (y ~ 0O5)7 AlASYSbl (y ~ 0.5) or quaternary alloys GaxInl Sb Pl 3 AlxGal As Sbl . For reasons of convenience, these semiconductors with a wide forbidden band are called semiconductors 2. In addition, for the purpose of simpliEying the text, GaInAs is used instead of Ga In As.
x 1 x Fig 3 is a diagrammatic section of the flrst em-bodiment of the transistor according to the invention.
On an e.g. InP semi-insulating substrate 7 are successively deposited by epitaxy a GaInAs layer 8 and a layer 9 constituted by a semiconductor 2.
Layer 8 is weakly doped at a level below 10 atoms/
cm3 and layer 9 is doped to a level above 101 atoms/
cm3. The source electrode 10 and drain electrode 11 are deposited on either side of the Schottky gate electro~e 12. As has been stated in accordance with Figs 1 and 2, electrons accumulate in the GaInAs layer 8 and leave layer 9. In order that only the electrol~s of the accumulation zone are involved in the operation of the transistor, the thickness of layer 8 is equal to the thickness of the accumulation zone (approx. 0.1 ~m) and that of layer 9 is equal to the thickness of the electron-free zone (approx. O.l~m).
?;~
The source - drain current is modulated by mearls of the gate polarization. This transistor operates at high frequency in accordance with the essence of the invention.
However, it is known that the interface between a semi-insulating substrate and an active layer contains electrically active defects. It is therefore advantageous to insert between substrate 7 and GaInAs layer 8 a high resistivity epitaxial layer called a buffer layer so as to eliminate local defects.
Fig 4 represents a second embodiment of the transistor incorporating a first improvement according to the invention. Besides the features referred to hereinbefore, its structure has a high resistivity InP buffer layer 14 or a high resistivity semi-conductor 2 inserted between the semi-insulating InP
substrate 7 and the active layer 8.
Fig 5 shows a third embodiment of the transistor having a second improvement according to the invention. Besides the elements descrlbed in the second embodiment, this transistor comprises a layer 15 of semiconductor 2 inserted between the active layer 8 and the buffer layer 14. The N type layer 15 is doped to a level above 101 atoms/cm3 in order to increase the density of electrons accumulated in the GaInAs layer 8. Thus, the transconductance of the device is increased. The thickness of layer 15 is equal to the thickness of the electron-free 0 zone in the heterojunction (approx. 0~1 ~m).
In the structures described hereinbefore the ohmic source contact 10 and the ohmic drain contact 11 are deposited on semiconductor 2. Uowever, it is necessary for the electrons to overcome a potential barrier ~ E in orcler to pass from the source to the drain. Generally, ~ Ec is sufficiently low for the electrons to overcome it ? but neverthe-less said barrier decreases the source - drain conductance.
In order to increase this conductance t the apparent height of the heterojunction barrier is reduced by a tunnel e~ect by strongly doping the semiconductor 2 in regions located beneath the so-lrce and the drain.
Fig 6 shows such a structure in which compartments 16 and 17 positioned beneath the contacts and which are highly doped (above 10l atoms/
cm ) are obtained by an implantation prior to depositing contacts lO and 11. To be completely ef~ective, it is necessary for the compartments 16 and 17 to penetrate the active layer 8. In addition, compartments 16 and 17 make it posslbl.e to redllce the source and drain contact resistances and the series resistances constituted by the thick-ness of layer 9 beneath the source and the drain.
The structures shown in the ~irst threeembodiments are improved by adding compartments 16 and 17 beneath the access region contacts.
In the embodiments described~ the substrate is constituted by InP. ~owe~er? other substrates rall ~ 3 ~
within the scope of the lnvention and the other semiconductor layers referred to in connection with Fig 2, namely ternary and quaternary alloys as specifled in the following claims also fall within the scope of the inven~ion.
The transistors according to the invention are used in all ultra-high frequency fields and in particular in telecommlmicatlonsO
GaxInl xAs. For x ~ 0.5, the alloy GaxInl_ As is adapted with respect to the mesh parameter to InP.
For x ~ 0.5, the alloy GaxInl As has a forbidden band of approximately 0.75 eV. Thus, the semiconductor 2 with a wider forhidden band than GaxInl As can be InP (forbidden band 1.36 eV), Al Inl As (x ~ 0.5) (forbidden band 1.46 eV), GaAsySbl (y ~ 0O5)7 AlASYSbl (y ~ 0.5) or quaternary alloys GaxInl Sb Pl 3 AlxGal As Sbl . For reasons of convenience, these semiconductors with a wide forbidden band are called semiconductors 2. In addition, for the purpose of simpliEying the text, GaInAs is used instead of Ga In As.
x 1 x Fig 3 is a diagrammatic section of the flrst em-bodiment of the transistor according to the invention.
On an e.g. InP semi-insulating substrate 7 are successively deposited by epitaxy a GaInAs layer 8 and a layer 9 constituted by a semiconductor 2.
Layer 8 is weakly doped at a level below 10 atoms/
cm3 and layer 9 is doped to a level above 101 atoms/
cm3. The source electrode 10 and drain electrode 11 are deposited on either side of the Schottky gate electro~e 12. As has been stated in accordance with Figs 1 and 2, electrons accumulate in the GaInAs layer 8 and leave layer 9. In order that only the electrol~s of the accumulation zone are involved in the operation of the transistor, the thickness of layer 8 is equal to the thickness of the accumulation zone (approx. 0.1 ~m) and that of layer 9 is equal to the thickness of the electron-free zone (approx. O.l~m).
?;~
The source - drain current is modulated by mearls of the gate polarization. This transistor operates at high frequency in accordance with the essence of the invention.
However, it is known that the interface between a semi-insulating substrate and an active layer contains electrically active defects. It is therefore advantageous to insert between substrate 7 and GaInAs layer 8 a high resistivity epitaxial layer called a buffer layer so as to eliminate local defects.
Fig 4 represents a second embodiment of the transistor incorporating a first improvement according to the invention. Besides the features referred to hereinbefore, its structure has a high resistivity InP buffer layer 14 or a high resistivity semi-conductor 2 inserted between the semi-insulating InP
substrate 7 and the active layer 8.
Fig 5 shows a third embodiment of the transistor having a second improvement according to the invention. Besides the elements descrlbed in the second embodiment, this transistor comprises a layer 15 of semiconductor 2 inserted between the active layer 8 and the buffer layer 14. The N type layer 15 is doped to a level above 101 atoms/cm3 in order to increase the density of electrons accumulated in the GaInAs layer 8. Thus, the transconductance of the device is increased. The thickness of layer 15 is equal to the thickness of the electron-free 0 zone in the heterojunction (approx. 0~1 ~m).
In the structures described hereinbefore the ohmic source contact 10 and the ohmic drain contact 11 are deposited on semiconductor 2. Uowever, it is necessary for the electrons to overcome a potential barrier ~ E in orcler to pass from the source to the drain. Generally, ~ Ec is sufficiently low for the electrons to overcome it ? but neverthe-less said barrier decreases the source - drain conductance.
In order to increase this conductance t the apparent height of the heterojunction barrier is reduced by a tunnel e~ect by strongly doping the semiconductor 2 in regions located beneath the so-lrce and the drain.
Fig 6 shows such a structure in which compartments 16 and 17 positioned beneath the contacts and which are highly doped (above 10l atoms/
cm ) are obtained by an implantation prior to depositing contacts lO and 11. To be completely ef~ective, it is necessary for the compartments 16 and 17 to penetrate the active layer 8. In addition, compartments 16 and 17 make it posslbl.e to redllce the source and drain contact resistances and the series resistances constituted by the thick-ness of layer 9 beneath the source and the drain.
The structures shown in the ~irst threeembodiments are improved by adding compartments 16 and 17 beneath the access region contacts.
In the embodiments described~ the substrate is constituted by InP. ~owe~er? other substrates rall ~ 3 ~
within the scope of the lnvention and the other semiconductor layers referred to in connection with Fig 2, namely ternary and quaternary alloys as specifled in the following claims also fall within the scope of the inven~ion.
The transistors according to the invention are used in all ultra-high frequency fields and in particular in telecommlmicatlonsO
Claims (6)
1. A field effect transistor with a high cut-off frequency which comprises, supported by a semi-insulating substrate, two access regions called the source and the drain and a control region con-stituted by a first active layer, a second layer and a metal Schottky gate, the second layer being positioned between the first layer and the metal gate, wherein the first layer which is made from a semi-conductor material of a first group and the second layer made from a semiconductor material of a second group form an isotype N-N heterojunction in which the semiconductor material of the second group has the same crystalline mesh parameter and a wider forbidden band than the semiconductor material of the first group and wherein the first layer is doped to a level equal to or below 1016 atoms/cm3 and the second layer to a level equal to or above 1017 atoms/
cm3.
cm3.
2. A field effect transistor according to claim 1, wherein the semi-insulating substrate is constituted by InP, the first semiconductor of the first layer is GaxInl-xAs(x ? 0.5) and the second semiconductor of the second layer is chosen from among InP, A1xInl-xAs(x ? 0.5), AlAsySbl-y(y ? 0.5) or one of the quaternary alloys GaxInl-xAsyPl-y' AlxGal-xAsy Sbl-y.
3. A field effect transistor according to claim 1, wherein the semi-insulating substrate is constituted by GaAs, the first semiconductor of the first layer is GaAs and the second semiconductor of the second layer is AlxGal-x As with 0.1 < x < 0.8.
4. A field effect transistor according to claim 1, wherein a buffer layer of the second high resistivity semiconductor is positioned between the first layer and the semi-insulating substrate.
5. A field effect transistor according to claim 4, wherein a third layer of the second semiconductor doped to a level above 1017 atoms/cm3 is positioned between the buffer layer and the first layer.
6. A field effect transistor according to claim 1, wherein it comprises two compartments doped to a level above 1018 atoms/cm3 positioned beneath the source and drain contacts, said compartments having a thickness which is at least equal to the thickness of the second layer and at the most equal to the total thickness of the first and second layers.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR8021942 | 1980-10-14 | ||
| FR8021942A FR2492167A1 (en) | 1980-10-14 | 1980-10-14 | FIELD EFFECT TRANSISTOR WITH HIGH BREAKAGE FREQUENCY |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1182930A true CA1182930A (en) | 1985-02-19 |
Family
ID=9246865
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000387748A Expired CA1182930A (en) | 1980-10-14 | 1981-10-13 | Field effect transistor with a high cut-off frequency |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP0050064B1 (en) |
| JP (1) | JPS5795672A (en) |
| CA (1) | CA1182930A (en) |
| DE (1) | DE3170300D1 (en) |
| FR (1) | FR2492167A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5170230A (en) * | 1989-05-10 | 1992-12-08 | Fujitsu Limited | Semiconductor device and production method thereof |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5913376A (en) * | 1982-07-13 | 1984-01-24 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor thin film having hetero junction |
| FR2537781B1 (en) * | 1982-12-14 | 1986-05-30 | Thomson Csf | FIELD EFFECT TRANSISTOR, OPERATING IN AN ELECTRON GAS ACCUMULATION SYSTEM |
| JPS6052060A (en) * | 1983-08-31 | 1985-03-23 | Masataka Inoue | field effect transistor |
| JPS60113475A (en) * | 1983-11-24 | 1985-06-19 | Fujitsu Ltd | Semiconductor device |
| JPH07120790B2 (en) * | 1984-06-18 | 1995-12-20 | 株式会社日立製作所 | Semiconductor device |
| GB2166286B (en) * | 1984-10-26 | 1988-07-20 | Stc Plc | Photo-detectors |
| JPS61107758A (en) * | 1984-10-31 | 1986-05-26 | Fujitsu Ltd | GaAs integrated circuit and its manufacturing method |
| JPH0714056B2 (en) * | 1985-04-05 | 1995-02-15 | 日本電気株式会社 | Semiconductor device |
| JPH0216102Y2 (en) * | 1985-05-17 | 1990-05-01 | ||
| JPS62145779A (en) * | 1985-12-19 | 1987-06-29 | Sumitomo Electric Ind Ltd | field effect transistor |
| JPS6328072A (en) | 1986-07-21 | 1988-02-05 | Sumitomo Electric Ind Ltd | Field effect transistor |
| EP0264932A1 (en) * | 1986-10-24 | 1988-04-27 | Sumitomo Electric Industries Limited | Field effect transistor |
| US4839702A (en) * | 1987-11-20 | 1989-06-13 | Bell Communications Research, Inc. | Semiconductor device based on charge emission from a quantum well |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4160261A (en) * | 1978-01-13 | 1979-07-03 | Bell Telephone Laboratories, Incorporated | Mis heterojunction structures |
| US4163237A (en) * | 1978-04-24 | 1979-07-31 | Bell Telephone Laboratories, Incorporated | High mobility multilayered heterojunction devices employing modulated doping |
| FR2465318A1 (en) * | 1979-09-10 | 1981-03-20 | Thomson Csf | FIELD EFFECT TRANSISTOR WITH HIGH BREAKAGE FREQUENCY |
| EP0033037B1 (en) * | 1979-12-28 | 1990-03-21 | Fujitsu Limited | Heterojunction semiconductor devices |
| JPS577165A (en) * | 1980-06-17 | 1982-01-14 | Fujitsu Ltd | Semiconductor device |
-
1980
- 1980-10-14 FR FR8021942A patent/FR2492167A1/en active Granted
-
1981
- 1981-09-24 DE DE8181401484T patent/DE3170300D1/en not_active Expired
- 1981-09-24 EP EP81401484A patent/EP0050064B1/en not_active Expired
- 1981-10-13 JP JP56163353A patent/JPS5795672A/en active Pending
- 1981-10-13 CA CA000387748A patent/CA1182930A/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5170230A (en) * | 1989-05-10 | 1992-12-08 | Fujitsu Limited | Semiconductor device and production method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2492167B1 (en) | 1984-02-17 |
| EP0050064A3 (en) | 1982-05-05 |
| EP0050064B1 (en) | 1985-05-02 |
| FR2492167A1 (en) | 1982-04-16 |
| DE3170300D1 (en) | 1985-06-05 |
| JPS5795672A (en) | 1982-06-14 |
| EP0050064A2 (en) | 1982-04-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA1182930A (en) | Field effect transistor with a high cut-off frequency | |
| US4987462A (en) | Power MISFET | |
| JP3602150B2 (en) | High electron mobility transistor | |
| US4558337A (en) | Multiple high electron mobility transistor structures without inverted heterojunctions | |
| US4772925A (en) | High speed switching field effect transistor | |
| JPS6342864B2 (en) | ||
| US5105241A (en) | Field effect transistor | |
| JP2914049B2 (en) | Compound semiconductor substrate having heterojunction and field effect transistor using the same | |
| CA1208807A (en) | Semiconductor device | |
| US4942438A (en) | Compound semiconductor field-effect transistor | |
| US4980731A (en) | Atomic planar-doped field-effect transistor | |
| JPS62274783A (en) | semiconductor equipment | |
| US4600932A (en) | Enhanced mobility buried channel transistor structure | |
| US4903091A (en) | Heterojunction transistor having bipolar characteristics | |
| US5751029A (en) | Field-effect semiconductor device having heterojunction | |
| US20060102931A1 (en) | Field effect transistor having a carrier exclusion layer | |
| EP0250886B1 (en) | Semiconductor heterostructure adapted for low temperature operation | |
| JP2949518B2 (en) | Semiconductor device and manufacturing method thereof | |
| Prost et al. | High speed, high gain InP-based heterostructure FETs with high breakdown voltage and low leakage | |
| CA2090441A1 (en) | Field-effect transistor having a double pulse-doped structure | |
| Kuang et al. | High‐current lattice‐strained In0. 59Ga0. 41As/In0. 52Al0. 48As modulation‐doped field‐effect transistors grown by molecular beam epitaxy | |
| EP0486063B1 (en) | Field-effect transistor | |
| JP2761211B2 (en) | Semiconductor device | |
| EP0569259A2 (en) | Multiquantum barrier field effect transistor | |
| JPS6149476A (en) | Field-effect transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |