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SRIDHARAN, 2011 - Google Patents

Hierarchical Design of Control in Custom Built Heterogeneous Multi-Core Architectures

SRIDHARAN, 2011

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Document ID
14718219704223226729
Author
SRIDHARAN A
Publication year

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Snippet

Current day multi-core processors grow more complex with sophistication of individual cores. The reasons for such sophistication are due to both performance requirement and technological constraints. Recently, several multi-core processor designs have incorporated …
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Classifications

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    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
    • G06F9/3891—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters
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