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Chawla et al., 2004 - Google Patents

A 531 nw/mhz, 128/spl times/32 current-mode programmable analog vector-matrix multiplier with over two decades of linearity

Chawla et al., 2004

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Document ID
12698221388324920125
Author
Chawla R
Bandyopadhyay A
Srinivasan V
Hasler P
Publication year
Publication venue
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No. 04CH37571)

External Links

Snippet

We present a 128/spl times/32 four-quadrant programmable current-mode analog vector- matrix multiplier (VMM). The proposed multiplier cell operates on a 3.3 V supply, consumes 531 nW/MHz and is linear over two decades of current range. Programmability and non …
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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06GANALOGUE COMPUTERS
    • G06G7/00Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/14Arrangements for performing computing operations, e.g. operational amplifiers for addition or subtraction
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C27/00Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02Sample-and-hold arrangements
    • G11C27/024Sample-and-hold arrangements using a capacitive memory element

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