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Krestinskaya et al., 2018 - Google Patents

Feature extraction without learning in an analog spatial pooler memristive-cmos circuit design of hierarchical temporal memory

Krestinskaya et al., 2018

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Document ID
1052116182676011231
Author
Krestinskaya O
James A
Publication year
Publication venue
Analog Integrated Circuits and Signal Processing

External Links

Snippet

Hierarchical temporal memory (HTM) is a neuromorphic algorithm that emulates sparsity, hierarchy and modularity resembling the working principles of neocortex. Feature encoding is an important step to create sparse binary patterns. This sparsity is introduced by the binary …
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Classifications

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    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/0635—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means using analogue means
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