8000 xiaoweish (xiaoweish) / Repositories · GitHub
[go: up one dir, main page]
More Web Proxy on the site http://driver.im/
Skip to content
View xiaoweish's full-sized avatar

Block or report xiaoweish

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
  • opene902 Public

    Forked from XUANTIE-RV/opene902

    OpenXuantie - OpenE902 Core

    Verilog Apache License 2.0 Updated May 9, 2025
  • lerobot Public

    Forked from huggingface/lerobot

    🤗 LeRobot: Making AI for Robotics more accessible with end-to-end learning

    Python Apache License 2.0 Updated Apr 25, 2025
  • x-heep Public

    Forked from esl-epfl/x-heep

    eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V

    C Other Updated Apr 8, 2025
  • Performance and diagnostic tools for Arm CMN on-chip interconnects

    Python Other Updated Mar 28, 2025
  • bedrock-rtl Public

    Forked from xlsynth/bedrock-rtl

    High quality and composable RTL libraries in SystemVerilog

    SystemVerilog Apache License 2.0 Updated Mar 28, 2025
  • taxi Public

    Forked from fpganinja/taxi

    AXI, AXI stream, Ethernet, and PCIe components in System Verilog

    SystemVerilog CERN Open Hardware Licence Version 2 - Strongly Reciprocal Updated Mar 27, 2025
  • Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.githu…

    Verilog Apache License 2.0 Updated Mar 26, 2025
  • vortex Public

    Forked from vortexgpgpu/vortex
    Verilog Apache License 2.0 Updated Mar 16, 2025
  • py2hwsw Public

    Forked from IObundle/py2hwsw

    a Python framework for managing embedded HW/SW projects

    Python MIT License Updated Mar 11, 2025
  • iob-soc Public

    Forked from IObundle/iob-soc

    RISC-V System on Chip Template

    Makefile MIT License Updated Mar 10, 2025
  • cva6 Public

    Forked from openhwgroup/cva6

    The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

    Assembly Other Updated Mar 7, 2025
  • vrq-code Public

    Verilog Updated Mar 5, 2025
  • IOMMU IP compliant with the RISC-V IOMMU Specification v1.0

    SystemVerilog Apache License 2.0 Updated Feb 25, 2025
  • coverview Public

    Forked from antmicro/coverview
    Vue Apache License 2.0 Updated Feb 18, 2025
  • Bus functional model of an Enhanced Serial Peripheral Interface (eSPI) master

    VHDL BSD 3-Clause "New" or "Revised" License Updated Jan 18, 2025
  • Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)

    Makefile Creative Commons Attribution 4.0 International Updated Jan 10, 2025
  • opentitan Public

    Forked from lowRISC/opentitan

    OpenTitan: Open source silicon root of trust

    SystemVerilog Apache License 2.0 Updated Jan 8, 2025
  • SweRV EH1 core

    SystemVerilog Apache License 2.0 Updated Dec 27, 2024
  • Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)

    Shell Updated Dec 18, 2024
  • 在GD32VF103移植FreeRTOSV10,支持使用中断栈机制,支持sysview

    C BSD 3-Clause "New" or "Revised" License Updated Dec 18, 2024
  • Hazard3 Public

    Forked from Wren6991/Hazard3

    3-stage RV32IMACZb* processor with debug

    Verilog Apache License 2.0 Updated Nov 29, 2024
  • libmetal Public

    Forked from OpenAMP/libmetal

    An abstraction layer across RTOS, baremetal, and user-space Linux environments

    C Other Updated Nov 26, 2024
  • RISC-V Functional ISA Simulator

    C Other Updated Nov 25, 2024
  • Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, accelerators, compilers and operating systems. You probably …

    C Other Updated Nov 20, 2024
  • scr1 Public

    Forked from syntacore/scr1

    SCR1 is a high-quality open-source RISC-V MCU core in Verilog

    SystemVerilog Other Updated Nov 15, 2024
  • vim-pathogen Public

    Forked from tpope/vim-pathogen

    pathogen.vim: manage your runtimepath

    Vim Script Vim License Updated Nov 11, 2024
  • riscv.vim Public

    Forked from laurelmay/riscv.vim

    RISC-V Assembly Syntax Highlighting for Vim

    Vim Script MIT License Updated Nov 11, 2024
  • SystemVerilog Updated Nov 5, 2024
  • qemu Public

    Forked from qemu/qemu

    Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

    C Other Updated Oct 25, 2024
  • SystemC/TLM-2.0 Co-simulation framework

    Verilog Other Updated Oct 25, 2024
0