8000 Commits · xesscorp/VHDL_Lib · GitHub

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Commits

Commits on Oct 10, 2023

Create LICENSE
xesscorp
authored

Commits on Jan 9, 2017

PulseGen fixed so output pulse stays high when re-triggered before the end of a pulse.
Dave Vandenbout
committed

Commits on Jul 11, 2016

Modified the HostIoToRam module so that done and operation-begun inputs aren't needed if the external RAM or register can complete read/write operations in a single clock cycle.
Dave Vandenbout
committed

Commits on Jun 16, 2016

Merge branch 'master' of https://github.com/xesscorp/VHDL_Lib
Dave Vandenbout
committed
SPI data word is now set by width of input data vector.
Dave Vandenbout
committed

Commits on Mar 11, 2015

Updated VHDL library.
Dave Vandenbout
committed

Commits on Mar 10, 2015

+ Panel refresh rate now takes into account the number of row repetitions.
Dave Vandenbout
committed

Commits on Mar 3, 2015

Revised documentation.
Dave Vandenbout
committed
LED panel driver now uses only a single block RAM to store pixels for the upper and lower half of the panel.
Dave Vandenbout
committed
LED panel RGB + clk + latch timing appears correct, no inter-row bleeding, and FSM is simpler.
Dave Vandenbout
committed

Commits on Mar 1, 2015

Almost working (first pixel of line N is showing partially on line N+1), but too complicated.
Dave Vandenbout
committed

Commits on Feb 20, 2015

Reorganized LED panel driver to use a clock-enable instead of driving it with a lower-speed clock. This implementation still doesn't work.
Dave Vandenbout
committed
Added clock-enable input to delays.
Dave Vandenbout
committed

Commits on Feb 19, 2015

God-awful, piece-of-shit implementation of a 32x32 LED panel driver.
Dave Vandenbout
committed
Added a module for transferring a single-ended clock signal to the logic fabric.
Dave Vandenbout
committed

Commits on Feb 17, 2015

Initial commit of LED panel driver.
Dave Vandenbout
committed
Randon number register initializes to all-ones as the default seed so the generator will start even without an explicit reset.
Dave Vandenbout
committed

Commits on Feb 4, 2015

Added serial BREAK capability to HostIoComm module.
Dave Vandenbout
committed

Commits on Jan 26, 2015

Simplified EchoTest for HostIoComm.
Dave Vandenbout
committed

Commits on Jan 5, 2015

Added a bit of documentation to the RGB LED driver.
Dave Vandenbout
committed

Commits on Jan 2, 2015

Added RGB LED driver with adjustable intensity for each color.
Dave Vandenbout
committed

Commits on Oct 30, 2014

Commits on Sep 17, 2014

Added signals to the process sensitivity list to remove warnings during synthesis.
Dave Vandenbout
committed

Commits on Aug 26, 2014

Added a version of HostIoComm with a Wishbone interface to the rest of the FPGA.
Dave Vandenbout
committed
+ Delayed done signal so it doesn't immediately terminate read/write control signal.
Dave Vandenbout
committed
Added a generic parameter to set the reset value of the HostIoToDut outputs.
Dave Vandenbout
committed
Made FifoCc synchronous so large FIFOs can be implemented in block RAM.
Dave Vandenbout
committed

Commits on May 24, 2014

Added generic parameters to set input source to either microphone or line input, and to set the preamplifier gain on the input source.
Dave Vandenbout
committed

Commits on May 21, 2014

Updated README for the new Misc.vhd file.
Dave Vandenbout
committed
Added file for storing miscellaneous VHDL modules.
Dave Vandenbout
committed
Added module to record & playback audio streams from a stereo codec to/from RAM.
Dave Vandenbout
committed
Changed license from GPL to LGPL.
Dave Vandenbout
committed
Added module to convert R/W control signals to handshake mode.
Dave Vandenbout
committed

Commits on May 6, 2014

Added synchronizer to done signal that goes from SDRAM clock domain back to JTAG clock domain.
Dave Vandenbout
committed

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