8000 Remove AXI4 from Gemmini · Issue #389 · ucb-bar/gemmini · GitHub
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Remove AXI4 from Gemmini #389
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Remove AXI4 from Gemmini#389
@Ben-INL

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@Ben-INL
Ben-INL
opened on May 12, 2025

I am currently trying to implement Gemmini on an FPGA, but it uses too many I/Os - 363 in total, of which 268 are used solely by AXI4.
Additionally, 64 I/Os are used by the Serial TileLink interface and 31 for scalar ports.
Therefore, I am wondering: is it possible to use only the Serial TileLink interface? If so, how much would this impact performance?

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