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- 9 commits
- 12 files changed
- 1 contributor
Commits on Aug 18, 2022
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Attempt to unbreak project build, so far futile, as Synplify Pro quits
with the doomed "Synthesis exit by9 / error code 9" message, without any further traces or insight. While here, prune unused signals and fix indentation.
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Unbreak buld by adding an include path for sdrc_top.v
Remove sdrc_top.v from project file list, since it is being referenced / included by other Verilog modules directly.
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Commits on Aug 20, 2022
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