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ESP8266 as controller uses a very tight timing after a start condition. Analysis with a logic analyzer shows that the ESP8266 will pull SDA up very soon after pulling SCL low. Addresses >= 0x40 will result in a '1' bit sent immediately after that.
Logic Analyzer output from Pulseview (remove ".zip" from file extension): 0x40 24Mhz 20k samples.sr.zip
The original code will erroneously interpret this as a stop condition because it does not buffer the state of SDA between detecting a pin change and interpreting this change as a stop condition. Also, it ignores SCL in doing so.
// Wait until end of start condition or begin of stop condition
while ((PINB & 128) && !(PINB & 32));
// Break when a stop condition has been received while waiting
if (PINB & 32) {
break;
}
After the false detection of a stop detection the above break; command will cause an exit from the main loop, putting the device in an undefined, non reactive state.
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