8000 Commits · cjprince/verilog-axi · GitHub

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Commits

Commits on Feb 27, 2025

Add deprecation notice
alexforencich
committed

Commits on Mar 30, 2023

Fix reset CDC in AXI VFIFO
alexforencich
committed

Commits on Mar 29, 2023

Commits on Feb 18, 2023

Remove recursively-expanded macros for module parameters in makefiles
alexforencich
committed

Commits on Feb 13, 2023

Commits on Jan 30, 2023

Rework parameter handling in testbench makefiles
alexforencich
committed

Commits on Jan 17, 2023

Update timing constraints to handle clocks from OOC IP that are not constrained during synthesis
alexforencich
committed

Commits on Sep 8, 2022

Update package versions
alexforencich
committed

Commits on Dec 28, 2021

Commits on Dec 11, 2021

Use start_soon instead of fork
alexforencich
committed

Commits on Nov 15, 2021

Remove deprecated assigments
alexforencich
committed

Commits on Nov 8, 2021

Fix typos
alexforencich
committed

Commits on Nov 6, 2021

Add FIFO output register in AXI lite crossbar modules
alexforencich
committed

Commits on Nov 5, 2021

Add attributes to RAMs for proper synthesis in Quartus
alexforencich
committed

Commits on Oct 20, 2021

Commits on Aug 30, 2021

Commits on Aug 26, 2021

Update interconnect address handling
alexforencich
committed

Commits on Aug 11, 2021

Commits on Aug 3, 2021

Commits on Aug 1, 2021

Commits on Jun 3, 2021

Update test durations
alexforencich
committed

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