Closed
Description
Type of issue: Bug Report
Please provide the steps to reproduce the problem:
//> using scala 2.13.15
//> using repository https://s01.oss.sonatype.org/content/repositories/snapshots
//> using dep org.chipsalliance::chisel:7.0.0-M2+432-486b55dc-SNAPSHOT
//> using plugin org.chipsalliance:::chisel-plugin:7.0.0-M2+432-486b55dc-SNAPSHOT
//> using options -unchecked -deprecation -language:reflectiveCalls -feature -Xcheckinit -Xfatal-warnings -Ywarn-dead-code -Ywarn-unused -Ymacro-annotations
import chisel3._
class Foo(x: BigInt, width: Int) extends Module {
val out1 = IO(Output(UInt(width.W)))
val out2 = IO(Output(UInt(width.W)))
val out3 = IO(Output(UInt(width.W)))
out1 := x.asUInt(width)
out2 := x.asUInt
out3 := x.U(width.W)
}
object Main extends App {
import _root_.circt.stage.ChiselStage
val width = 8
println(
ChiselStage.emitSystemVerilog(
gen = new Foo((1 << width) - 1, width),
firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info", "-default-layer-specialization=enable")
)
)
}Running this with scala-cli generates this result:
// Generated by CIRCT firtool-1.107.0
module Foo(
input clock,
reset,
output [7:0] out1,
out2,
out3
);
assign out1 = 8'h0;
assign out2 = 8'hFF;
assign out3 = 8'hFF;
endmoduleWhat is the current behavior?
Running x.asUInt(width) always returns a Bool (the same happens if you change x from a BigInt to an Int). If you change the out1 := x.asUInt(width) line above to use the :<= operator, you'll get this error:
[error] ./chisel-example.scala:13:3
[error] Cannot prove that chisel3.UInt =:= chisel3.Bool.
[error] out1 :<= x.asUInt(width)
[error] ^^^^^^^^^^^^^^^^^^^^^^^^
What is the expected behavior?
x.asUInt(width) should return a UInt of the specified width. I would expect the resulting Verilog to say assign out1 = 8'hFF;, like out2 and out3.
Please tell us about your environment:
- version:
7.0.0-M2+432-486b55dc-SNAPSHOT - OS: macOS 15.3.1
Other Information
What is the use case for changing the behavior?
This should match the behavior of x.U(width.W).
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