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I've been trying to use the --split-verilog parameter in the EmitVerilog function of Chisel, but I've encountered some issues. Here is a screenshot detailing the problem:
Upon searching for related issues, I found issue #3029 which seems to suggest that this could be an internal bug within Chisel.
Updating to the experimental version v6.0.0M3 of Chisel appears to resolve the problem, but I'd prefer not to rely on an experimental version for my project.
Could anyone confirm whether this is a bug? If it is, are there any known workarounds for this issue? Additionally, are there any alternative methods for splitting Verilog files when using Chisel?
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I've been trying to use the --split-verilog parameter in the EmitVerilog function of Chisel, but I've encountered some issues. Here is a screenshot detailing the problem:
Upon searching for related issues, I found issue #3029 which seems to suggest that this could be an internal bug within Chisel.
Updating to the experimental version v6.0.0M3 of Chisel appears to resolve the problem, but I'd prefer not to rely on an experimental version for my project.
Could anyone confirm whether this is a bug? If it is, are there any known workarounds for this issue? Additionally, are there any alternative methods for splitting Verilog files when using Chisel?
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