Description
First of all, thanks for writing this tool.
I just want to verify that I am using this tool properly in my test environment. My current setup is two TI EX-TM4C123GXL boards. One board runs the sketch, and the other board is just for the JTAG interface. This JTAG interface has been tested using the JTAGulator to make sure it functions as expected. The pinout for this board can be found here. The GPIOs of the first board are connected to the second board, with the proper pin numbers placed in the sketch.
After successfully connecting to the terminal, I run a loopback check, which gives no results. Then I run a scan, and icodescan. Still nothing. Then I do a boundary scan (mentioned to be broken, can I help fix?) and get some results:
> b
================================
Starting shift of pattern through bypass...
Assumes bypass is the default DR on reset.
Hence, no need to check for TMS. Also, currently
not checking for nTRST, which might not work
active tck:PA5 tdo:PB5 tdi:PE5 bits toggled:12
The only one of these that was correct is TDO. Again, I saw that this was mentioned as broken so this is not surprising. However, was I supposed to be getting results for the other commands? I have tried with pullup resistors on and off, as well as the prescale define there or not. I would love to use this project as part of my pentest routine. Can you please tell me what I am doing wrong?