8000 axi_dmac: AXI3 support on Intel qsys · analogdevicesinc/hdl@ad05a5e · GitHub
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axi_dmac: AXI3 support on Intel qsys
Exposed AXI3 interface on the Intel version of the IP for UI and feature consistency. Some of the signals that are defined as optional in the AMBA standard are marked as mandatory in Qsys in case of AXI3. Because of this such signals were added to the interface of the DMAC and driven with default values. For Xilinx in order to keep existing behavior the newly added signals are hidden from the interface. New parameters are added to define the width of the AXI transaction IDs; these are hidden from the UI; We can add them to the UI if the fixed size of the IDs will cause port incompatibility issues.
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‎library/axi_dmac/axi_dmac.v

+30-1
Original file line numberDiff line numberDiff line change
@@ -54,8 +54,9 @@ module axi_dmac #(
5454
parameter DMA_AXI_ADDR_WIDTH = 32,
5555
parameter MAX_BYTES_PER_BURST = 128,
5656
parameter FIFO_SIZE = 4, // In bursts
57+
parameter AXI_ID_WIDTH_SRC = 4,
58+
parameter AXI_ID_WIDTH_DEST = 4,
5759
parameter DISABLE_DEBUG_REGISTERS = 0)(
58-
5960
// Slave AXI interface
6061
input s_axi_aclk,
6162
input s_axi_aresetn,
@@ -96,18 +97,22 @@ module axi_dmac #(
9697
output [ 3:0] m_dest_axi_awcache,
9798
output m_dest_axi_awvalid,
9899
input m_dest_axi_awready,
100+
output [AXI_ID_WIDTH_DEST-1:0] m_dest_axi_awid,
101+
output [DMA_AXI_PROTOCOL_DEST:0] m_dest_axi_awlock,
99102

100103
// Write data
101104
output [DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_wdata,
102105
output [(DMA_DATA_WIDTH_DEST/8)-1:0] m_dest_axi_wstrb,
103106
input m_dest_axi_wready,
104107
output m_dest_axi_wvalid,
105108
output m_dest_axi_wlast,
109+
output [AXI_ID_WIDTH_DEST-1:0] m_dest_axi_wid,
106110

107111
// Write response
108112
input m_dest_axi_bvalid,
109113
input [ 1:0] m_dest_axi_bresp,
110114
output m_dest_axi_bready,
115+
input [AXI_ID_WIDTH_DEST-1:0] m_dest_axi_bid,
111116

112117
// Unused read interface
113118
output m_dest_axi_arvalid,
@@ -122,6 +127,10 @@ module axi_dmac #(
122127
input [ 1:0] m_dest_axi_rresp,
123128
input [DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_rdata,
124129
output m_dest_axi_rready,
130+
output [AXI_ID_WIDTH_DEST-1:0] m_dest_axi_arid,
131+
output [DMA_AXI_PROTOCOL_DEST:0] m_dest_axi_arlock,
132+
input [AXI_ID_WIDTH_DEST-1:0] m_dest_axi_rid,
133+
input m_dest_axi_rlast,
125134

126135
// Master AXI interface
127136
input m_src_axi_aclk,
@@ -136,12 +145,16 @@ module axi_dmac #(
136145
output [ 1:0] m_src_axi_arburst,
137146
output [ 2:0] m_src_axi_arprot,
138147
output [ 3:0] m_src_axi_arcache,
148+
output [AXI_ID_WIDTH_SRC-1:0] m_src_axi_arid,
149+
output [DMA_AXI_PROTOCOL_SRC:0] m_src_axi_arlock,
139150

140151
// Read data and response
141152
input [DMA_DATA_WIDTH_SRC-1:0] m_src_axi_rdata,
142153
output m_src_axi_rready,
143154
input m_src_axi_rvalid,
144155
input [ 1:0] m_src_axi_rresp,
156+
input [AXI_ID_WIDTH_SRC-1:0] m_src_axi_rid,
157+
input m_src_axi_rlast,
145158

146159
// Unused write interface
147160
output m_src_axi_awvalid,
@@ -160,6 +173,12 @@ module axi_dmac #(
160173
input m_src_axi_bvalid,
161174
input [ 1:0] m_src_axi_bresp,
162175
output m_src_axi_bready,
176+
output [AXI_ID_WIDTH_SRC-1:0] m_src_axi_awid,
177+
output [DMA_AXI_PROTOCOL_SRC:0] m_src_axi_awlock,
178+
output [AXI_ID_WIDTH_SRC-1:0] m_src_axi_wid,
179+
input [AXI_ID_WIDTH_SRC-1:0] m_src_axi_bid,
180+
181+
163182

164183
// Slave streaming AXI interface
165184
input s_axis_aclk,
@@ -296,6 +315,11 @@ assign m_dest_axi_arsize = 'd0;
296315
assign m_dest_axi_arburst = 'd0;
297316
assign m_dest_axi_arcache = 'd0;
298317
assign m_dest_axi_arprot = 'd0;
318+
assign m_dest_axi_awid = 'h0;
319+
assign m_dest_axi_awlock = 'h0;
320+
assign m_dest_axi_wid = 'h0;
321+
assign m_dest_axi_arid = 'h0;
322+
assign m_dest_axi_arlock = 'h0;
299323
assign m_src_axi_awaddr = 'd0;
300324
assign m_src_axi_awlen = 'd0;
301325
assign m_src_axi_awsize = 'd0;
@@ -305,6 +329,11 @@ assign m_src_axi_awprot = 'd0;
305329
assign m_src_axi_wdata = 'd0;
306330
assign m_src_axi_wstrb = 'd0;
307331
assign m_src_axi_wlast = 'd0;
332+
assign m_src_axi_awid = 'h0;
333+
assign m_src_axi_awlock = 'h0;
334+
assign m_src_axi_wid = 'h0;
335+
assign m_src_axi_arid = 'h0;
336+
assign m_src_axi_arlock = 'h0;
308337

309338
up_axi #(
310339
.AXI_ADDRESS_WIDTH (12),

‎library/axi_dmac/axi_dmac_hw.tcl

+79-67
Original file line numberDiff line numberDiff line change
@@ -87,6 +87,12 @@ foreach {suffix group} { \
8787
{ "0:Memory-Mapped AXI" "1:Streaming AXI" "2:FIFO Interface" }
8888
set_parameter_property DMA_TYPE_$suffix GROUP $group
8989

90+
add_parameter DMA_AXI_PROTOCOL_$suffix INTEGER 0
91+
set_parameter_property DMA_AXI_PROTOCOL_$suffix DISPLAY_NAME "AXI Protocol"
92+
set_parameter_property DMA_AXI_PROTOCOL_$suffix HDL_PARAMETER true
93+
set_parameter_property DMA_AXI_PROTOCOL_$suffix ALLOWED_RANGES { "0:AXI4" "1:AXI3" }
94+
set_parameter_property DMA_AXI_PROTOCOL_$suffix GROUP $group
95+
9096
add_parameter DMA_DATA_WIDTH_$suffix INTEGER 64
9197
set_parameter_property DMA_DATA_WIDTH_$suffix DISPLAY_NAME "Bus Width"
9298
set_parameter_property DMA_DATA_WIDTH_$suffix UNITS Bits
@@ -234,6 +240,14 @@ proc axi_dmac_validate {} {
234240
set_parameter_property ${p}_MANUAL VISIBLE [expr $auto_clk ? false : true]
235241
set_parameter_property $p VISIBLE $auto_clk
236242
}
243+
foreach suffix {SRC DEST} {
244+
if {[get_parameter_value DMA_TYPE_$suffix] == 0} {
245+
set show_axi_protocol true
246+
} else {
247+
set show_axi_protocol false
248+
}
249+
set_parameter_property DMA_AXI_PROTOCOL_$suffix VISIBLE $show_axi_protocol
250+
}
237251
}
238252

239253
# conditional interfaces
@@ -247,38 +261,6 @@ add_interface m_dest_axi_reset reset end
247261
set_interface_property m_dest_axi_reset associatedClock m_dest_axi_clock
248262
add_interface_port m_dest_axi_reset m_dest_axi_aresetn reset_n Input 1
249263

250-
add_interface m_dest_axi axi4 start
251-
set_interface_property m_dest_axi associatedClock m_dest_axi_clock
252-
set_interface_property m_dest_axi associatedReset m_dest_axi_reset
253-
set_interface_property m_dest_axi readIssuingCapability 1
254-
add_interface_port m_dest_axi m_dest_axi_awvalid awvalid Output 1
255-
add_interface_port m_dest_axi m_dest_axi_awaddr awaddr Output 32
256-
add_interface_port m_dest_axi m_dest_axi_awready awready Input 1
257-
add_interface_port m_dest_axi m_dest_axi_wvalid wvalid Output 1
258-
add_interface_port m_dest_axi m_dest_axi_wdata wdata Output DMA_DATA_WIDTH_DEST
259-
add_interface_port m_dest_axi m_dest_axi_wstrb wstrb Output DMA_DATA_WIDTH_DEST/8
260-
add_interface_port m_dest_axi m_dest_axi_wready wready Input 1
261-
add_interface_port m_dest_axi m_dest_axi_bvalid bvalid Input 1
262-
add_interface_port m_dest_axi m_dest_axi_bresp bresp Input 2
263-
add_interface_port m_dest_axi m_dest_axi_bready bready Output 1
264-
add_interface_port m_dest_axi m_dest_axi_arvalid arvalid Output 1
265-
add_interface_port m_dest_axi m_dest_axi_araddr araddr Output 32
266-
add_interface_port m_dest_axi m_dest_axi_arready arready Input 1
267-
add_interface_port m_dest_axi m_dest_axi_rvalid rvalid Input 1
268-
add_interface_port m_dest_axi m_dest_axi_rresp rresp Input 2
269-
add_interface_port m_dest_axi m_dest_axi_rdata rdata Input DMA_DATA_WIDTH_DEST
270-
add_interface_port m_dest_axi m_dest_axi_rready rready Output 1
271-
add_interface_port m_dest_axi m_dest_axi_awlen awlen Output 8
272-
add_interface_port m_dest_axi m_dest_axi_awsize awsize Output 3
273-
add_interface_port m_dest_axi m_dest_axi_awburst awburst Output 2
274-
add_interface_port m_dest_axi m_dest_axi_awcache awcache Output 4
275-
add_interface_port m_dest_axi m_dest_axi_awprot awprot Output 3
276-
add_interface_port m_dest_axi m_dest_axi_wlast wlast Output 1
277-
add_interface_port m_dest_axi m_dest_axi_arlen arlen Output 8
278-
add_interface_port m_dest_axi m_dest_axi_arsize arsize Output 3
279-
add_interface_port m_dest_axi m_dest_axi_arburst arburst Output 2
280-
add_interface_port m_dest_axi m_dest_axi_arcache arcache Output 4
281-
add_interface_port m_dest_axi m_dest_axi_arprot arprot Output 3
282264

283265
add_interface m_src_axi_clock clock end
284266
add_interface_port m_src_axi_clock m_src_axi_aclk clk Input 1
@@ -287,41 +269,6 @@ add_interface m_src_axi_reset reset end
287269
set_interface_property m_src_axi_reset associatedClock m_src_axi_clock
288270
add_interface_port m_src_axi_reset m_src_axi_aresetn reset_n Input 1
289271

290-
add_interface m_src_axi axi4 start
291-
set_interface_property m_src_axi associatedClock m_src_axi_clock
292-
set_interface_property m_src_axi associatedReset m_src_axi_reset
293-
set_interface_property m_src_axi readIssuingCapability 1
294-
set_interface_property m_src_axi writeIssuingCapability 1
295-
set_interface_property m_src_axi combinedIssuingCapability 1
296-
add_interface_port m_src_axi m_src_axi_awvalid awvalid Output 1
297-
add_interface_port m_src_axi m_src_axi_awaddr awaddr Output 32
298-
add_interface_port m_src_axi m_src_axi_awready awready Input 1
299-
add_interface_port m_src_axi m_src_axi_wvalid wvalid Output 1
300-
add_interface_port m_src_axi m_src_axi_wdata wdata Output DMA_DATA_WIDTH_SRC
301-
add_interface_port m_src_axi m_src_axi_wstrb wstrb Output DMA_DATA_WIDTH_SRC/8
302-
add_interface_port m_src_axi m_src_axi_wready wready Input 1
303-
add_interface_port m_src_axi m_src_axi_bvalid bvalid Input 1
304-
add_interface_port m_src_axi m_src_axi_bresp bresp Input 2
305-
add_interface_port m_src_axi m_src_axi_bready bready Output 1
306-
add_interface_port m_src_axi m_src_axi_arvalid arvalid Output 1
307-
add_interface_port m_src_axi m_src_axi_araddr araddr Output 32
308-
add_interface_port m_src_axi m_src_axi_arready arready Input 1
309-
add_interface_port m_src_axi m_src_axi_rvalid rvalid Input 1
310-
add_interface_port m_src_axi m_src_axi_rresp rresp Input 2
311-
add_interface_port m_src_axi m_src_axi_rdata rdata Input DMA_DATA_WIDTH_SRC
312-
add_interface_port m_src_axi m_src_axi_rready rready Output 1
313-
add_interface_port m_src_axi m_src_axi_awlen awlen Output 8
314-
add_interface_port m_src_axi m_src_axi_awsize awsize Output 3
315-
add_interface_port m_src_axi m_src_axi_awburst awburst Output 2
316-
add_interface_port m_src_axi m_src_axi_awcache awcache Output 4
317-
add_interface_port m_src_axi m_src_axi_awprot awprot Output 3
318-
add_interface_port m_src_axi m_src_axi_wlast wlast Output 1
319-
add_interface_port m_src_axi m_src_axi_arlen arlen Output 8
320-
add_interface_port m_src_axi m_src_axi_arsize arsize Output 3
321-
add_interface_port m_src_axi m_src_axi_arburst arburst Output 2
322-
add_interface_port m_src_axi m_src_axi_arcache arcache Output 4
323-
add_interface_port m_src_axi m_src_axi_arprot arprot Output 3
324-
325272
# axis destination/source
326273

327274
ad_alt_intf clock m_axis_aclk input 1 clk
@@ -354,10 +301,75 @@ ad_alt_intf signal fifo_wr_overflow output 1 ovf
354301
ad_alt_intf signal fifo_wr_sync input 1 sync
355302
ad_alt_intf signal fifo_wr_xfer_req output 1 xfer_req
356303

304+
proc add_axi_master_interface {axi_type port suffix} {
305+
add_interface $port $axi_type start
306+
set_interface_property $port associatedClock ${port}_clock
307+
set_interface_property $port associatedReset ${port}_reset
308+
set_interface_property $port readIssuingCapability 1
309+
add_interface_port $port ${port}_awvalid awvalid Output 1
310+
add_interface_port $port ${port}_awaddr awaddr Output 32
311+
add_interface_port $port ${port}_awready awready Input 1
312+
add_interface_port $port ${port}_wvalid wvalid Output 1
313+
add_interface_port $port ${port}_wdata wdata Output DMA_DATA_WIDTH_${suffix}
314+
add_interface_port $port ${port}_wstrb wstrb Output DMA_DATA_WIDTH_${suffix}/8
315+
add_interface_port $port ${port}_wready wready Input 1
316+
add_interface_port $port ${port}_bvalid bvalid Input 1
317+
add_interface_port $port ${port}_bresp bresp Input 2
318+
add_interface_port $port ${port}_bready bready Output 1
319+
add_interface_port $port ${port}_arvalid arvalid Output 1
320+
add_interface_port $port ${port}_araddr araddr Output 32
321+
add_interface_port $port ${port}_arready arready Input 1
322+
add_interface_port $port ${port}_rvalid rvalid Input 1
323+
add_interface_port $port ${port}_rresp rresp Input 2
324+
add_interface_port $port ${port}_rdata rdata Input DMA_DATA_WIDTH_${suffix}
325+
add_interface_port $port ${port}_rready rready Output 1
326+
add_interface_port $port ${port}_awlen awlen Output "8-(4*DMA_AXI_PROTOCOL_${suffix})"
327+
add_interface_port $port ${port}_awsize awsize Output 3
328+
add_interface_port $port ${port}_awburst awburst Output 2
329+
add_interface_port $port ${port}_awcache awcache Output 4
330+
add_interface_port $port ${port}_awprot awprot Output 3
331+
add_interface_port $port ${port}_wlast wlast Output 1
332+
add_interface_port $port ${port}_arlen arlen Output "8-(4*DMA_AXI_PROTOCOL_${suffix})"
333+
add_interface_port $port ${port}_arsize arsize Output 3
334+
add_interface_port $port ${port}_arburst arburst Output 2
335+
add_interface_port $port ${port}_arcache arcache Output 4
336+
add_interface_port $port ${port}_arprot arprot Output 3
337+
# Some signals are mandatory in Altera's implementation of AXI3
338+
# awid, awlock, wid, bid, arid, arlock, rid, rlast
339+
# Hide them in AXI4
340+
add_interface_port $port ${port}_awid awid Output 4
341+
add_interface_port $port ${port}_awlock awlock Output "1+DMA_AXI_PROTOCOL_${suffix}"
342+
add_interface_port $port ${port}_wid wid Output 4
343+
add_interface_port $port ${port}_arid arid Output 4
344+
add_interface_port $port ${port}_arlock arlock Output "1+DMA_AXI_PROTOCOL_${suffix}"
345+
add_interface_port $port ${port}_rid rid Input 4
346+
add_interface_port $port ${port}_bid bid Input 4
347+
add_interface_port $port ${port}_rlast rlast Input 1
348+
if {$axi_type == "axi4"} {
349+
set_port_property ${port}_awid TERMINATION true
350+
set_port_property ${port}_awlock TERMINATION true
351+
set_port_property ${port}_wid TERMINATION true
352+
set_port_property ${port}_arid TERMINATION true
353+
set_port_property ${port}_arlock TERMINATION true
354+
set_port_property ${port}_rid TERMINATION true
355+
set_port_property ${port}_bid TERMINATION true
356+
set_port_property ${port}_rlast TERMINATION true
357+
}
358+
}
357359
proc axi_dmac_elaborate {} {
358360
set fifo_size [get_parameter_value FIFO_SIZE]
359361
set disabled_intfs {}
360362

363+
# add axi3 or axi4 interface depending on user selection
364+
foreach {suffix port} {SRC m_src_axi DEST m_dest_axi} {
365+
if {[get_parameter_value DMA_AXI_PROTOCOL_${suffix}] == 0} {
366+
set axi_type axi4
367+
} else {
368+
set axi_type axi
369+
}
370+
add_axi_master_interface $axi_type $port $suffix
371+
}
372+
361373
# axi4 destination/source
362374

363375
if {[get_parameter_value DMA_TYPE_DEST] == 0} {

‎library/axi_dmac/axi_dmac_ip.tcl

+23
Original file line numberDiff line numberDiff line change
@@ -107,6 +107,27 @@ set dummy_axi_ports [list \
107107
"m_src_axi_bresp" \
108108
]
109109

110+
# These are in the design to keep the Altera tools happy which require
111+
# certain signals in AXI3 mode even if these are defined as optinal in the standard.
112+
lappend dummy_axi_ports \
113+
"m_dest_axi_awid" \
114+
"m_dest_axi_awlock" \
115+
"m_dest_axi_wid" \
116+
"m_dest_axi_bid" \
117+
"m_dest_axi_arid" \
118+
"m_dest_axi_arlock" \
119+
"m_dest_axi_rid" \
120+
"m_dest_axi_rlast" \
121+
"m_src_axi_arid" \
122+
"m_src_axi_arlock" \
123+
"m_src_axi_rid" \
124+
"m_src_axi_rlast" \
125+
"m_src_axi_awid" \
126+
"m_src_axi_awlock" \
127+
"m_src_axi_wid" \
128+
"m_src_axi_bid"
129+
130+
110131
foreach p $dummy_axi_ports {
111132
adi_set_ports_dependency $p "false"
112133
}
@@ -343,6 +364,8 @@ set_property -dict [list \
343364
] $p
344365

345366
ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "DMA_AXI_ADDR_WIDTH" -component $cc]
367+
ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "AXI_ID_WIDTH_SRC" -component $cc]
368+
ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "AXI_ID_WIDTH_DEST" -component $cc]
346369

347370

348371
ipx::create_xgui_files [ipx::current_core]

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