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Hi, |
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See $FFF0 IRQ in the RIA docs. |
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A small thankyou for the rather terse reply. For completeness, I'll explain what I've understood. Setting bit 7 (0x80) in the IRQ register 0xFFF0 will enable the RIA to generate an interrupt every 60th of a second. The VSYNC counter, 0xFFE3 is incremented every time the period expires, and can be used to check if it's the RIA that interrupted, or the VIA. |
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A small thankyou for the rather terse reply. For completeness, I'll explain what I've understood.
Setting bit 7 (0x80) in the IRQ register 0xFFF0 will enable the RIA to generate an interrupt every 60th of a second. The VSYNC counter, 0xFFE3 is incremented every time the period expires, and can be used to check if it's the RIA that interrupted, or the VIA.
I'm assuming that VSYNC always increments, even if the IRQ register is set to zero. All this also assumes that the VGA pico is connected and functioning.
Glenn