Description
What's happen? Please describe the problem you met.
The opll_buf.h provides a message queue (FIFO) to write to the OPLL registers.
On the other hand, ay_3_8910.h and scc_buf.h provide the PSG and SCC/SCC+ register caches.
These assume that the sound driver only writes the most recent register values each frame.
However, the sound driver may write to the same register more than once in a frame.
For example, when playing very short pulses or very short mutes,
the sound driver may write to PSG register No.7 or the SCC/SCC+ channel mask register two or more times in the same frame.
Describe the solution you'd like
PSG and SCC/SCC+ also require a message queue (FIFO) API.
Describe alternatives you've considered
Also, sound drivers may write to the PSG, SCC/SCC+, and OPLL registers in various orders.
Therefore, a unified message queue API may be needed for these sound chips.
Additional context
(none)