Stars
A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
Self checking RISC-V directed tests
The purpose of the repo is to support CORE-V Wally architectural verification
Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
RISC-V Double Trap Fast-Track Extension
RISC-V cryptography extensions standardisation work.
Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.
This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
Benchmark for measuring the performance of sparse and irregular memory access.
The multi-core cluster of a PULP system.
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Functional verification project for the CORE-V family of RISC-V cores.
RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
Proposed RISC-V Composable Custom Extensions Specification
Multi-platform nightly builds of open source digital design and verification tools
CoreMark® is an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcrontrollers (MCU).
SystemVerilog Functional Coverage for RISC-V ISA
Working Draft of the RISC-V Debug Specification Standard