Floating-point unit

In 1954, the IBM 704 had floating-point arithmetic as a standard feature, one of its major improvements over its predecessor the IBM 701. This was carried forward to its successors the 709, 7090, and 7094.

In 1963, Digital announced the PDP-6, which had floating point as a standard feature.^[5]

In 1963, the GE-235 featured an "Auxiliary Arithmetic Unit" for floating point and double-precision calculations.^[6]

Historically, some systems implemented floating point with a coprocessor rather than as an integrated unit (but now in addition to the CPU, e.g. GPUs – that are coprocessors not always built into the CPU – have FPUs as a rule, while first generations of GPUs did not). This could be a single integrated circuit, an entire circuit board or a cabinet. Where floating-point calculation hardware has not been provided, floating-point calculations are done in software, which takes more processor time, but avoids the cost of the extra hardware. For a particular computer architecture, the floating-point unit instructions may be emulated by a library of software functions; this may permit the same object code to run on systems with or without floating-point hardware. Emulation can be implemented on any of several levels: in the CPU as microcode, as an operating system function, or in user-space code. When only integer functionality is available, the CORDIC methods are most commonly used for transcendental function evaluation.^{[citation needed]}

In most modern computer architectures, there is some division of floating-point operations from integer operations. This division varies significantly by architecture; some have dedicated floating-point registers, while some, like Intel x86, go as far as independent clocking schemes.^[7]

CORDIC routines have been implemented in Intel x87 coprocessors (8087,^{[8][9][10][11][12]} 80287,^[12][13] 80387^[12][13]) up to the 80486^[8] microprocessor series, as well as in the Motorola 68881^[8][9] and 68882 for some kinds of floating-point instructions, mainly as a way to reduce the gate counts (and complexity) of the FPU subsystem.

Floating-point operations are often pipelined. In earlier superscalar architectures without general out-of-order execution, floating-point operations were sometimes pipelined separately from integer operations.

The modular architecture of Bulldozer microarchitecture uses a special FPU named FlexFPU, which uses simultaneous multithreading. Each physical integer core, two per module, is single-threaded, in contrast with Intel's Hyperthreading, where two virtual simultaneous threads share the resources of a single physical core.^[14][15]

 

Wikibooks has a book on the topic of: Floating Point/Soft Implementations

 

Wikibooks has a book on the topic of: Embedded Systems/Floating Point Unit

Some floating-point hardware only supports the simplest operations: addition, subtraction, and multiplication. But even the most complex floating-point hardware has a finite number of operations it can support – for example, no FPUs directly support arbitrary-precision arithmetic.

When a CPU is executing a program that calls for a floating-point operation that is not directly supported by the hardware, the CPU uses a series of simpler floating-point operations. In systems without any floating-point hardware, the CPU emulates it using a series of simpler fixed-point arithmetic operations that run on the integer arithmetic logic unit.

The software that lists the necessary series of operations to emulate floating-point operations is often packaged in a floating-point library.

In some cases, FPUs may be specialized, and divided between simpler floating-point operations (mainly addition and multiplication) and more complicated operations, like division. In some cases, only the simple operations may be implemented in hardware or microcode, while the more complex operations are implemented as software.

In some current architectures, the FPU functionality is combined with SIMD units to perform SIMD computation; an example of this is the augmentation of the x87 instructions set with SSE instruction set in the x86-64 architecture used in newer Intel and AMD processors.

Several models of the PDP-11, such as the PDP-11/45,^[16] PDP-11/34a,^{[17]: 184–185} PDP-11/44,^{[17]: 195, 211} and PDP-11/70,^{[17]: 277, 286–287} supported an add-on floating-point unit to support floating-point instructions. The PDP-11/60,^[17]: 261 MicroPDP-11/23^[18] and several VAX models^[19][20] could execute floating-point instructions without an add-on FPU (the MicroPDP-11/23 required an add-on microcode option),^[18] and offered add-on accelerators to further speed the execution of those instructions.

In the 1980s, it was common in IBM PC/compatible microcomputers for the FPU to be entirely separate from the CPU, and typically sold as an optional add-on. It would only be purchased if needed to speed up or enable math-intensive programs.

The IBM PC, XT, and most compatibles based on the 8088 or 8086 had a socket for the optional 8087 coprocessor. The AT and 80286-based systems were generally socketed for the 80287, and 80386/80386SX-based machines – for the 80387 and 80387SX respectively, although early ones were socketed for the 80287, since the 80387 did not exist yet. Other companies manufactured co-processors for the Intel x86 series. These included Cyrix and Weitek. Acorn Computers opted for the WE32206 to offer single, double and extended precision^[21] to its ARM powered Archimedes range, introducing a gate array to interface the ARM2 processor with the WE32206 to support the additional ARM floating-point instructions.^[22] Acorn later offered the FPA10 coprocessor, developed by ARM, for various machines fitted with the ARM3 processor.^[23]

Coprocessors were available for the Motorola 68000 family, the 68881 and 68882. These were common in Motorola 68020/68030-based workstations, like the Sun-3 series. They were also commonly added to higher-end models of Apple Macintosh and Commodore Amiga series, but unlike IBM PC-compatible systems, sockets for adding the coprocessor were not as common in lower-end systems.

There are also add-on FPU coprocessor units for microcontroller units (MCUs/μCs)/single-board computer (SBCs), which serve to provide floating-point arithmetic capability. These add-on FPUs are host-processor-independent, possess their own programming requirements (operations, instruction sets, etc.) and are often provided with their own integrated development environments (IDEs).

• Arithmetic logic unit (ALU)
• Address generation unit (AGU)
• Load–store unit
• CORDIC routines are used in many FPUs to implement functions but not greatly increase gate count
• Execution unit
• IEEE 754 floating-point standard
• IBM hexadecimal floating point
• Graphics processing unit
• Multiply–accumulate operation

• Filiatreault, Raymond (2003). "SIMPLY FPU".