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- research-articleMay 2019
STAT: Mean and Variance Characterization for Robust Inference of DNNs on Memristor-based Platforms
GLSVLSI '19: Proceedings of the 2019 Great Lakes Symposium on VLSIPages 339–342https://doi.org/10.1145/3299874.3318032An emerging solution to accelerate the inference phase of deep neural networks (DNNs) is to utilize memristor crossbar arrays (MCAs) to perform highly efficient matrix-vector multiplication in the analog domain. An adverse challenge is that memristor ...
- ArticleNovember 2014
An Efficient Diagnosis Pattern Generation Procedure to Distinguish Stuck-at Faults and Bridging Faults
ATS '14: Proceedings of the 2014 IEEE 23rd Asian Test SymposiumPages 306–311https://doi.org/10.1109/ATS.2014.56Fault Diagnosis is a critical process to identify the locations of physical defects in advanced integrated circuits. Current diagnosis tools often report multiple types of faults as defect candidates. Thus an efficient method to distinguish different ...
- ArticleAugust 1997
Memory array testing through a scannable configuration
We have previously proposed a scannable memory configuration which is useful in testing logic blocks around memory arrays. In this paper, from a viewpoint of memory testing, we investigate the testability of the scannable memory configuration and ...
- research-articleAugust 1981
Syndrome-Testability Can be Achieved by Circuit Modification
IEEE Transactions on Computers (ITCO), Volume 30, Issue 8Pages 604–606https://doi.org/10.1109/TC.1981.1675848In [1] and [2] Savir developed many facets of syndrome-testing (checking the number of minterms realized by a circuit against the number realized by a fault-free version of that circuit) and presented evidence showing that syndrome-testing can be used ...
- research-articleNovember 1980
Dual-Mode Logic for Function-Independent Fault Testing
IEEE Transactions on Computers (ITCO), Volume 29, Issue 11Pages 1025–1029https://doi.org/10.1109/TC.1980.1675500This correspondence presents a oncept of function-independent testing of digital networks. It is based on the idea of dual-mode logic where the network is tested in one mode while the normal function of the network is performed in another mode, with ...
- surveyAugust 1980
Test Sets for Combinational Logic The Edge-Tracing Approach
IEEE Transactions on Computers (ITCO), Volume 29, Issue 8Pages 741–746https://doi.org/10.1109/TC.1980.1675660A method for fault analysis of multilevel combinational logic circuits with single stuck-at-faults is described. It determines the sensitizing input combinations (separating edges) from the output function and then traces their paths from the output ...
- surveyDecember 1978
Fault Detection Capabilities of Alternating Logic
IEEE Transactions on Computers (ITCO), Volume 27, Issue 12Pages 1093–1098https://doi.org/10.1109/TC.1978.1675011This paper details the fault detection capability of a design technique named "alternating logic design." The technique achieves its fault detection capability by utilizing a redundancy in time instead of the conventional redundancy in space and is ...
- surveyMay 1978
On the Detection of Terminal Stuck-Faults
IEEE Transactions on Computers (ITCO), Volume 27, Issue 5Pages 467–469https://doi.org/10.1109/TC.1978.1675129Two lower bounds on the length of terminal stuck-fault tests and a technique to facilitate detection of terminal stuck-faults are given.
- research-articleJanuary 1976
Identification of Multiple Stuck-Type Faults in Combinational Networks
IEEE Transactions on Computers (ITCO), Volume 25, Issue 1Pages 44–54https://doi.org/10.1109/TC.1976.5009204This paper deals with the problem of identifying multiple stuck-type hardware failures in combinational switching networks. Our work is an extension of that of Poage, and Bossen and Hong, and we employ the cause-effect equation for representing faulty ...
- research-articleNovember 1974
On the Design of Logic Networks with Redundancy and Testability Considerations
IEEE Transactions on Computers (ITCO), Volume 23, Issue 11Pages 1139–1149https://doi.org/10.1109/T-C.1974.223821The presence of redundancy in combinational networks increases the cardinality of the test set to detect all stuck-at-faults. A solution to this problem is to identify and remove all redundancies in the networks before deriving test sets. It is shown in ...
- research-articleJanuary 1974
Easily Testable Cellular Realizations for the (Exactly P)-out-of n and (p or More)-out-of n Logic Functions
IEEE Transactions on Computers (ITCO), Volume 23, Issue 1Pages 98–100https://doi.org/10.1109/T-C.1974.223787Networks to realize all n-variable symmetric threshold functions and elementary symmetric functions are given. It is also shown that only 2n test inputs are necessary and sufficient to test any number of faults in these networks.
- research-articleNovember 1973
Complete Test Sets for Logic Functions
IEEE Transactions on Computers (ITCO), Volume 22, Issue 11Pages 1016–1020https://doi.org/10.1109/T-C.1973.223638The problem of designing fault detecting test sets from the functional description rather than the structural description of the networks realizing the logic function is studied. The concept of an expanded truth table for logic functions is introduced. ...
- research-articleSeptember 1973
Universal Test Sets for Logic Networks
IEEE Transactions on Computers (ITCO), Volume 22, Issue 9Pages 835–839https://doi.org/10.1109/TC.1973.5009174This paper examines the problem of finding a single universal test set that will test any of a variety of different implementations of a given switching function. It is shown that, for AND/OR networks, universal test sets may be found that detect not ...