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- research-articleJanuary 2021
Proving termination by k-induction
ASE '20: Proceedings of the 35th IEEE/ACM International Conference on Automated Software EngineeringPages 1239–1243https://doi.org/10.1145/3324884.3418929We propose a novel approach to proving the termination of imperative programs by k-induction. By our approach, the termination proving problem can be formalized as a k-inductive invariant synthesis task. On the one hand, k-induction uses weaker ...
- ArticleOctober 2020
Model Checking a Distributed Interlocking System Using k-induction with RT-Tester
Leveraging Applications of Formal Methods, Verification and Validation: ApplicationsPages 449–466https://doi.org/10.1007/978-3-030-61467-6_29AbstractThis paper investigates the use of k-induction with RT-Tester for tackling the challenge of verifying the safety of a distributed railway interlocking system. For a real-world case study, it is described how a generic and reconfigurable model of ...
- ArticleJune 2020
Formal Verification of Invariants for Attributed Graph Transformation Systems Based on Nested Attributed Graph Conditions
AbstractThe behavior of various kinds of dynamic systems can be formalized using typed attributed graph transformation systems (GTSs). The states of these systems are then modelled using graphs and the evolution of the system from one state to another is ...
- research-articleOctober 2018
Towards counterexample-guided k-induction for fast bug detection
ESEC/FSE 2018: Proceedings of the 2018 26th ACM Joint Meeting on European Software Engineering Conference and Symposium on the Foundations of Software EngineeringPages 765–769https://doi.org/10.1145/3236024.3264840Recently, the k-induction algorithm has proven to be a successful approach for both finding bugs and proving correctness. However, since the algorithm is an incremental approach, it might waste resources trying to prove incorrect programs. In this paper,...
- research-articleMarch 2018
A Unifying View on SMT-Based Software Verification
Journal of Automated Reasoning (JAUR), Volume 60, Issue 3Pages 299–335https://doi.org/10.1007/s10817-017-9432-6AbstractAfter many years of successful development of new approaches for software verification, there is a need to consolidate the knowledge about the different abstract domains and algorithms. The goal of this paper is to provide a compact and accessible ...
- research-articleSeptember 2017
Incremental bounded model checking for embedded software
Formal Aspects of Computing (FAC), Volume 29, Issue 5Pages 911–931https://doi.org/10.1007/s00165-017-0419-1AbstractProgram analysis is on the brink of mainstream usage in embedded systems development. Formal verification of behavioural requirements, finding runtime errors and test case generation are some of the most common applications of automated ...
- articleFebruary 2017
Handling loops in bounded model checking of C programs via k-induction
International Journal on Software Tools for Technology Transfer (STTT) (STTT), Volume 19, Issue 1Pages 97–114https://doi.org/10.1007/s10009-015-0407-9The first attempts to apply the k-induction method to software verification are only recent. In this paper, we present a novel proof by induction algorithm, which is built on the top of a symbolic context-bounded model checker and uses an iterative ...
- articleFebruary 2013
SMT-based scenario verification for hybrid systems
Formal Methods in System Design (FMSD), Volume 42, Issue 1Pages 46–66https://doi.org/10.1007/s10703-012-0158-0Hybrid automata are a widely used framework to model complex critical systems, where continuous physical dynamics are combined with discrete transitions. The expressive power of Satisfiability Modulo Theories (SMT) solvers can be used to symbolically ...
- articleSeptember 2012
SAT-solving in CSP trace refinement
Science of Computer Programming (SCPR), Volume 77, Issue 10-11Pages 1178–1197https://doi.org/10.1016/j.scico.2011.07.008In this paper, we address the problem of applying SAT-based bounded model checking (BMC) and temporal k-induction to asynchronous concurrent systems. We investigate refinement checking in the process-algebraic setting of Communicating Sequential ...
- articleAugust 2011
Automatic analysis of DMA races using model checking and k-induction
Formal Methods in System Design (FMSD), Volume 39, Issue 1Pages 83–113https://doi.org/10.1007/s10703-011-0124-2Modern multicore processors, such as the Cell Broadband Engine, achieve high performance by equipping accelerator cores with small "scratch-pad" memories. The price for increased performance is higher programming complexity --- the programmer must ...
- posterFebruary 2011
SCRATCH: a tool for automatic analysis of dma races
PPoPP '11: Proceedings of the 16th ACM symposium on Principles and practice of parallel programmingPages 311–312https://doi.org/10.1145/1941553.1941604We present the SCRATCH tool, which uses bounded model checking and k-induction to automatically analyse software for multicore processors such as the Cell BE, in order to detect DMA races.
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ACM SIGPLAN Notices: Volume 46 Issue 8 - articleOctober 2010
SMT-AI: an Abstract Interpreter as Oracle for k-induction
Electronic Notes in Theoretical Computer Science (ENTCS) (ENTCS), Volume 267, Issue 2Pages 55–68https://doi.org/10.1016/j.entcs.2010.09.018The last decade has seen a major development of verification techniques based on SMT solvers used to prove inductive invariants on systems. This approach allows to prove functional properties and scale up to handle industrial problems. However, it often ...
- research-articleJuly 2010
Robust QBF Encodings for Sequential Circuits with Applications to Verification, Debug, and Test
IEEE Transactions on Computers (ITCO), Volume 59, Issue 7Pages 981–994https://doi.org/10.1109/TC.2010.74Formal CAD tools operate on mathematical models describing the sequential behavior of a VLSI design. With the growing size and state-space of modern digital hardware designs, the conciseness of this mathematical model is of paramount importance in ...
- ArticleSeptember 2008
Timed and Hybrid Automata in SAL
SYNASC '08: Proceedings of the 2008 10th International Symposium on Symbolic and Numeric Algorithms for Scientific ComputingPages 480–486https://doi.org/10.1109/SYNASC.2008.9Various methodologies to model and analyze timed and hybrid systems using SAL are reported. We assume that the system is specified as a network of timed/hybrid automata with synchronized transitions and urgency. We show how to translate the system into ...
- articleAugust 2007
Comparison of Maude and SAL by Conducting Case Studies Model Checking a Distributed Algorithm
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (FECCS), Volume E90-A, Issue 8Pages 1690–1703https://doi.org/10.1093/ietfec/e90-a.8.1690SAL is a toolkit for analyzing transition systems, providing several different tools. Among the tools are a BDD-based symbolic model checker (SMC) and an SMT-based infinite bounded model checker (infBMC). The unique functionality provided by SAL is k -...