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A secure processor requires that no secret, undocumented instructions be executed. Unfortunately, as today's processor design and supply chain are increasingly complex, undocumented instructions that can execute some specific functions can still ...

The Internet continues to flourish, while an increasing number of network applications are found deploying Bloom filters. However, the heterogeneity of the Bloom filter realisations complicates the utilisation of relevant applications. Moreover, when ...

With the wide deployment of embedded systems and constant increase in their inter‐connections, embedded systems tend to be confronted with attacks through security holes that are hard to predict using typical security measures such as access control or ...

With the proliferation of wireless devices with embedded processors, there is an increasing desire to deploy applications that run transparently over the varied architectures of these devices. Virtual machines are one solution for code mobility, ...

In order to improve the quality of microprocessor tests, the use of instruction sets for testing is indispensable. This paper discusses how fault coverage can be improved with a short test pattern that repeatedly samples an R number of instructions as L ...

Recently introduced "SIMD on registers" extensions to commodity microprocessors instruction sets promise (according to the makers) high potential speed-ups for multimedia processing tasks. This paper introduces the complex programming model of MMX/SSE ...

Instruction prefetching can effectively reduce instruction cache misses, thus improving the performance. In this paper, we propose a prefetching scheme, which employs a branch predictor to run ahead of the execution unit and to prefetch potentially ...

This abstract presents a design aid called ReCode, and describes its use in the analysis of existing instruction-set processors. ReCode allows the exploration of the relationship between the instruction-set and the corresponding application code of ...

Intel's MMX/sup TM/ technology is designed to accelerate multimedia and communications software. The Pentium(R) processor with MMX/sup TM/ technology (design code name P55C) is the first micro-processor to implement the new architecture, enabling the ...

An overview of various media processors' architecture is presented in this short tutorial. The media processors discussed here provide compute powers in terms of billions of operations per second along with the memory bandwidth required to sustain those ...

Cache memories are commonly avoided in real time systems because of their unpredictable behavior. Recently, some research has been done to obtain tighter bounds on the worst case execution time (WCET) of cached programs. These techniques usually assume ...

Recent progress in worst case timing analysis of programs has made it possible to perform accurate timing analysis of pipelined execution and instruction caching. However there has not been much progress in worst case timing analysis of data caching. ...

Global scheduling and optimization techniques are proposed to get more enough speedup for superscalar and VLIW (Very Long Instruction Word) processors. When we consider global scheduling and optimization, one of the most important issue is how to ...

The paper discusses the simulation system used to verify the architecture of the Mwave folded array signal transform (M.f.a.s.t.) processor, a single chip scalable very long instruction word (VLIW) processor array being developed by IBM ...

Today's advanced architectures increasingly rely on accurate instruction fetch and branch prediction to maintain optimum pipeline performance. In this paper, dynamic branch prediction techniques are investigated and methods to increase branch prediction ...

As more and more transistors are incorporated into processor chips, the circuits are becoming more and more error-prone, necessitating the introduction of fault tolerance techniques. This paper investigates techniques to incorporate fault tolerance in ...

With demands for reliability and further integration, reducing power consumption becomes a critical concern in today's processor design. Considering the different techniques to minimize power consumption and promote system's reliability, reducing ...

Abstract: This paper describes the application of a measurement based power analysis technique for an embedded DSP processor. An instruction-level power model for the processor has been developed using this technique. Significant points of difference ...

Abstract: The increasing usage of application-specific instruction set processors (ASIPs) in audio and video telecommunications has made strong demands on the rapid availability of dedicated compilers. A rule-driven approach to code generation may have ...

Abstract: This paper examines the problem of code generation for expression trees on non-homogeneous register set architectures. It proposes and proves the optimality of an O(n) algorithm for the tasks of instruction selection, register allocation and ...